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[llvm-readobj/ELF] fix: add correct test inputs
2015-10-13 Matt ArsenaultDAGCombiner: Don't stop finding better chain on 2 aliases
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2015-10-13 Matt ArsenaultAMDGPU: Refactor isVGPRToSGPRCopy
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2015-10-12 Matt ArsenaultDAGCombiner: Combine extract_vector_elt from build_vector
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2015-10-12 Matt ArsenaultAMDGPU: Register some more passes so -print-before...
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2015-10-12 Matt ArsenaultEnable verifier after PeepholeOptimizer
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2015-10-07 Matt ArsenaultAMDGPU: Fix missing implicit m0 uses on movrel instructions
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2015-10-07 Matt ArsenaultAMDGPU: Add comment for VOP2b operand class
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2015-10-07 Matt ArsenaultAMDGPU: Properly register passes
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2015-10-07 Matt ArsenaultAMDGPU: Use explicit register size indirect pseudos
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2015-10-07 Matt ArsenaultAMDGPU: Remove inferRegClassFromUses / inferRegClassFromDefs
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2015-10-02 Matt ArsenaultAMDGPU/SI: Add verifier check for exec reads
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2015-10-02 Matt ArsenaultAdd way to test for generic TargetOpcodes
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2015-10-01 Matt ArsenaultAMDGPU: Fix unused variable warning in release build
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2015-10-01 Matt ArsenaultAMDGPU: Move SIFixSGPRLiveRanges to be a regalloc pass
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2015-10-01 Matt ArsenaultAMDGPU: Merge if and switch
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2015-10-01 Matt ArsenaultAMDGPU: Remove dead code
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2015-10-01 Matt ArsenaultAMDGPU: Make SIInsertWaits about a factor of 4 faster
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2015-09-28 Matt ArsenaultAMDGPU: Factor switch into separate function
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2015-09-28 Matt ArsenaultAMDGPU: Fix splitting x16 SMRD loads
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2015-09-28 Matt ArsenaultAMDGPU: Fix moving SMRD loads with literal offsets...
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2015-09-28 Matt ArsenaultAMDGPU: Fix splitting SMRD with large offset
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2015-09-28 Matt ArsenaultAMDGPU: Add testcases
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2015-09-28 Matt ArsenaultAMDGPU: Cleanup test
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2015-09-26 Matt ArsenaultAMDGPU: Remove hasPostISelHook from most instructions
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2015-09-26 Matt ArsenaultAMDGPU: Switch over reg class size instead of checking...
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2015-09-26 Matt ArsenaultAMDGPU: Don't handle invalid reg classes in helper...
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2015-09-26 Matt ArsenaultAMDGPU: Set CopyCost of register classes
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2015-09-26 Matt ArsenaultAMDGPU: VOP3b definition cleanups
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2015-09-26 Matt ArsenaultAMDGPU: Fix sched model for VOP2b instructions
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2015-09-25 Matt ArsenaultAMDGPU: Construct new buffer instruction when moving...
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2015-09-25 Matt ArsenaultDAGCombiner: Check if store is volatile first
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2015-09-25 Matt ArsenaultPeepholeOptimizer: Remove redundant copies
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2015-09-25 Matt ArsenaultAMDGPU: Add some more tests for literal operands
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2015-09-25 Matt ArsenaultAMDGPU: Make getNamedOperandIdx declaration readonly
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2015-09-25 Matt ArsenaultAMDGPU: Disable some passes that are not meaningful
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2015-09-25 Matt ArsenaultAMDGPU: Handle i64->v2i32 loads/stores in PreprocessISelDAG
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2015-09-25 Matt ArsenaultAMDGPU: Fix recomputing dominator tree unnecessarily
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2015-09-25 Matt ArsenaultAMDGPU: Re-justify workaround and fix worked around...
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2015-09-25 Matt ArsenaultAMDGPU: Don't create REG_SEQUENCE with SGPR dest and...
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2015-09-25 Matt ArsenaultAMDGPU: Fix not adding exec to defs of cmpx instruction...
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2015-09-25 Matt ArsenaultAMDGPU: Improve accuracy of instruction rates for VOPC
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2015-09-25 Matt ArsenaultAMDGPU: Remove unused includes
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2015-09-24 Matt ArsenaultFix typo
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2015-09-24 Matt ArsenaultAMDGPU: Add s_dcache_* instructions
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2015-09-24 Matt ArsenaultAMDGPU: Add cache invalidation instructions.
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2015-09-24 Matt ArsenaultAMDGPU: Run mubuf assembler test for CI
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2015-09-24 Matt ArsenaultIntroduce target hook for optimizing register copies
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2015-09-24 Matt ArsenaultAMDGPU: Return after instruction is processed.
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2015-09-24 Matt ArsenaultAMDGPU: Remove another unnecessary check from commuteInstruction
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2015-09-24 Matt ArsenaultAMDGPU: Add readonly to InstrMapping functions
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2015-09-24 Matt ArsenaultTableGen: Add LLVM_READONLY to generated InstrMapping...
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2015-09-24 Matt ArsenaultAMDGPU: Fix printing trailing whitespace for mubuf...
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2015-09-24 Matt ArsenaultRemove dead declaration
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2015-09-24 Matt ArsenaultUse new TokenFactor chain when merging stores
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2015-09-24 Matt ArsenaultAMDGPU: Reduce number of copies emitted
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2015-09-22 Matt ArsenaultAMDGPU: Remove unnecessary check
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2015-09-21 Matt ArsenaultFix accidentally committed debug printing
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2015-09-21 Matt ArsenaultAMDGPU: Move copy handling under switch like other...
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2015-09-21 Matt ArsenaultDAGCombiner: Replace store of FP constant after attemping...
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2015-09-21 Matt ArsenaultFactor replacement of stores of FP constants into new...
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2015-09-21 Matt ArsenaultFix missing C++ mode comment
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2015-09-19 Matt ArsenaultAMDGPU: Remove dead code
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2015-09-19 Matt ArsenaultAMDGPU: Add failing testcase for live interval construction
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2015-09-10 Matt ArsenaultAMDGPU: Simplify debug printing
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2015-09-10 Matt ArsenaultAMDGPU: Use StringRef value
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2015-09-10 Matt ArsenaultAMDGPU/SI: Fix more cases of losing exec operands
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2015-09-10 Matt ArsenaultAMDGPU/SI: Fix creating v_mov_b32s without exec uses
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2015-09-09 Matt ArsenaultAMDGPU: Extract full 64-bit subregister and use subregs
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2015-09-09 Matt ArsenaultAMDGPU: Remove unused multiclass argument
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2015-09-09 Matt ArsenaultAMDGPU: Fix not encoding src2 of VOP3b instructions
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2015-09-09 Matt ArsenaultSelectionDAG: Support Expand of f16 extloads
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2015-09-09 Matt ArsenaultFix typos / grammar
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2015-09-08 Matt ArsenaultAMDGPU/SI: Fix input vcc operand for VOP2b instructions
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2015-09-08 Matt ArsenaultAdd const overload of findRegisterUseOperand
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2015-09-08 Matt ArsenaultAMDGPU: Mark s_barrier as a high latency instruction
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2015-09-08 Matt ArsenaultAMDGPU: Fix s_barrier flags
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2015-09-08 Matt ArsenaultAMDGPU: Handle sub of constant for DS offset folding
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2015-09-01 Matt ArsenaultAMDGPU: Fix adding redundant implicit operands
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2015-08-29 Matt ArsenaultAMDGPU: Add sdst operand to VOP2b instructions
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2015-08-29 Matt ArsenaultAMDGPU: Set mem operands for spill instructions
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2015-08-29 Matt ArsenaultAMDGPU: Fix dropping mem operands when moving to VALU
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2015-08-28 Matt ArsenaultMake MergeConsecutiveStores look at other stores on...
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2015-08-27 Matt ArsenaultAMDGPU/SI: Add test for folding constants into operands
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2015-08-26 Matt ArsenaultAMDGPU: Delete dead code
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2015-08-26 Matt ArsenaultAMDGPU: Don't reprocess instructions when splitting...
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2015-08-26 Matt ArsenaultAMDGPU: Fix not moving users of s_bfe_i64 to VALU
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2015-08-26 Matt ArsenaultAMDGPU: Don't create intermediate SALU instructions
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2015-08-26 Matt ArsenaultAMDGPU/SI: Report SIFixSGPRLiveRanges changed function
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2015-08-26 Matt ArsenaultAMDGPU: Make sure to reserve super registers
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2015-08-26 Matt ArsenaultAMDGPU: Produce error on dynamic_stackalloc
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2015-08-22 Matt ArsenaultAMDGPU: Allow specifying different opcode on VI for...
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2015-08-22 Matt ArsenaultAMDGPU: Improve accuracy of instruction rates for some...
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2015-08-22 Matt ArsenaultAMDGPU: Use DFS to avoid second loop over function
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2015-08-22 Matt ArsenaultAMDGPU: Make sure to run verifier after SIFixSGPRLiveRanges
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2015-08-22 Matt ArsenaultAMDGPU: Improve debug printing in SIFixSGPRLiveRanges
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2015-08-22 Matt ArsenaultAMDGPU: Move CI instructions into CIInstructions.td
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2015-08-21 Matt ArsenaultAMDGPU: Minor cleanups to help with f16 support
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2015-08-15 Matt ArsenaultAMDGPU/SI: Only look at live out SGPR defs
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2015-08-15 Matt ArsenaultLoopStrengthReduce: Try to pass address space to isLegalAddr...
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2015-08-15 Matt ArsenaultAMDGPU/SI: Fix printing useless info with amdhsa
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C/C++ LLVM-based compilers that forbids OOTA behaviors