Introduce target hook for optimizing register copies
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Thu, 24 Sep 2015 08:36:14 +0000 (08:36 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Thu, 24 Sep 2015 08:36:14 +0000 (08:36 +0000)
commitb10121bd9d277ab2483d14e00f49a4fa23b6ba82
tree421eb595e8f3c2244fcb9369f245e9ec21751005
parenta5e772ea93d2f14b6854ef58bdf6de077c1bd7d5
Introduce target hook for optimizing register copies

Allow a target to do something other than search for copies
that will avoid cross register bank copies.

Implement for SI by only rewriting the most basic copies,
so it should look through anything like a subregister extract.

I'm not entirely satisified with this because it seems like
eliminating a reg_sequence that isn't fully used should work
generically for all targets without them having to override
something. However, it seems to be tricky to have a simple
implementation of this without rewriting to invalid  kinds
of subregister copies on some targets.

I'm not sure if there is currently a generic way to easily check
if a subregister index would be valid for the current use.
The current set of TargetRegisterInfo::get*Class functions don't
quite behave like I would expect (e.g. getSubClassWithSubReg
returns the maximal register class rather than the minimal), so
I'm not sure how to make the generic test keep searching if
SrcRC:SrcSubReg is a valid replacement for DefRC:DefSubReg. Making
the default implementation to check for simple copies breaks
a variety of ARM and x86 tests by producing illegal subregister uses.

The ARM tests are not actually changed since it should still be using
the same sharesSameRegisterFile implementation, this just relaxes
them to not check for specific registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248478 91177308-0d34-0410-b5e6-96231b3b80d8
14 files changed:
include/llvm/Target/TargetRegisterInfo.h
lib/CodeGen/PeepholeOptimizer.cpp
lib/CodeGen/TargetRegisterInfo.cpp
lib/Target/AMDGPU/SIRegisterInfo.cpp
lib/Target/AMDGPU/SIRegisterInfo.h
test/CodeGen/AMDGPU/and.ll
test/CodeGen/AMDGPU/ds_read2_superreg.ll
test/CodeGen/AMDGPU/half.ll
test/CodeGen/AMDGPU/llvm.round.f64.ll
test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll [new file with mode: 0644]
test/CodeGen/ARM/vcombine.ll
test/CodeGen/ARM/vtrn.ll
test/CodeGen/ARM/vuzp.ll
test/CodeGen/ARM/vzip.ll