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AMDGPU: Fix ctlz combine for sub 32-bit types
2016-01-11 Matt ArsenaultAMDGPU: Fix ctlz combine for sub 32-bit types
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2016-01-11 Matt ArsenaultAMDGPU: Pattern match ffbh pattern to instruction.
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2016-01-11 Matt ArsenaultAMDGPU: Custom lower i64 ctlz
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2016-01-11 Matt ArsenaultMips: Remove lowerSELECT_CC
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2016-01-11 Matt ArsenaultLegalizeDAG: Expand ctlz with ctlz_zero_undef if legal
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2016-01-11 Matt ArsenaultAMDGPU: Remove dead target dag combine
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2016-01-05 Matt ArsenaultAMDGPU: Remove redundant let mayLoad = 1
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2015-12-24 Matt ArsenaultAMDGPU: Fix getRegisterBitWidth for vectors
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2015-12-19 Matt ArsenaultSelectionDAG: Cleanup integer bin op promotion functions.
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2015-12-19 Matt ArsenaultAMDGPU: Switch barrier intrinsics to using convergent
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2015-12-19 Matt ArsenaultFix broken type legalization of min/max
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2015-12-16 Matt ArsenaultAMDGPU: Override getCFInstrCost
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2015-12-14 Matt ArsenaultAMDGPU: Use generic bitreverse intrinsic
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2015-12-14 Matt ArsenaultAMDGPU: Fix splitting vector loads with existing offsets
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2015-12-11 Matt ArsenaultSelectionDAG: Match min/max if the scalar operation...
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2015-12-11 Matt ArsenaultStart replacing vector_extract/vector_insert with extractelt...
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2015-12-01 Matt ArsenaultAMDGPU: Error on addrspacecasts that aren't actually...
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2015-12-01 Matt ArsenaultAMDGPU: Implement isNoopAddrSpaceCast
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2015-12-01 Matt ArsenaultAMDGPU: Disallow flat_scr in SI assembler
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2015-12-01 Matt ArsenaultAMDGPU: Optimize VOP2 operand legalization
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2015-12-01 Matt ArsenaultAMDGPU: Report extractelement as free in cost model
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2015-12-01 Matt ArsenaultSquelch unused variable warning in SIRegisterInfo.cpp.
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2015-11-30 Matt ArsenaultAMDGPU: Fix unused function
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2015-11-30 Matt ArsenaultAMDGPU: Error if too many user SGPRs used
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2015-11-30 Matt ArsenaultAMDGPU: Rework how private buffer passed for HSA
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2015-11-30 Matt ArsenaultAMDGPU: Rename enums to be consistent with HSA code...
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2015-11-30 Matt ArsenaultAMDGPU: Remove SIPrepareScratchRegs
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2015-11-30 Matt ArsenaultAMDGPU: Use assert zext for workgroup sizes
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2015-11-30 Matt ArsenaultAMDGPU: Don't reserve SCRATCH_PTR input register
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2015-11-25 Matt ArsenaultAMDGPU: Check feature attributes in SIMachineFunctionInfo
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2015-11-25 Matt ArsenaultAMDGPU: Add some tests for promotion of v2i64 scalar_to_vector
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2015-11-25 Matt ArsenaultAMDGPU: Make v2i64/v2f64 legal types.
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2015-11-24 Matt ArsenaultAMDGPU: Split LDS vector loads
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2015-11-24 Matt ArsenaultAMDGPU: Split x8 and x16 vector loads instead of scalarize
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2015-11-11 Matt ArsenaultAdd target preference for GatherAllAliases max depth
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2015-11-11 Matt ArsenaultAMDGPU: Print more fields in comments
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2015-11-11 Matt ArsenaultAMDGPU: Remove dead code
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2015-11-11 Matt ArsenaultAMDGPU: Set isAllocatable = 0 on VS_32/VS_64
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2015-11-10 Matt ArsenaultLegalizeDAG: Implement promote for scalar_to_vector
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2015-11-10 Matt ArsenaultLegalizeDAG: Implement promote for insert_vector_elt
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2015-11-10 Matt ArsenaultLegalizeDAG: Implement promote for extract_vector_elt
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2015-11-10 Matt ArsenaultRemove unnecessary call to getAllocatableRegClass
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2015-11-06 Matt ArsenaultAMDGPU: Cleanup includes
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2015-11-06 Matt ArsenaultAMDGPU: Create emergency stack slots during frame lowering
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2015-11-06 Matt ArsenaultAMDGPU: Remove unused scratch resource operands
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2015-11-06 Matt ArsenaultAMDGPU: Add pass to detect used kernel features
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2015-11-06 Matt ArsenaultAMDGPU: Fix hardcoded alignment of spill.
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2015-11-06 Matt ArsenaultAMDGPU: Hack for VS_32 register pressure
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2015-11-05 Matt ArsenaultAMDGPU: Also track whether SGPRs were spilled
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2015-11-05 Matt ArsenaultAMDGPU: Print number user SGPRs
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2015-11-05 Matt ArsenaultAMDGPU: Disallow s[102:103] on VI in assembler
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2015-11-05 Matt ArsenaultAMDGPU: Fix assert when legalizing atomic operands
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2015-11-05 Matt ArsenaultAMDGPU: Make addr64 atomic operand order consistent
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2015-11-05 Matt ArsenaultAMDGPU: Add missing v2f64 fadd tests
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2015-11-05 Matt ArsenaultAMDGPU: Fix typo
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2015-11-03 Matt ArsenaultAMDGPU: Make flat_scratch name consistent
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2015-11-03 Matt ArsenaultAMDGPU: Fix asserts on invalid register ranges
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2015-11-03 Matt ArsenaultAMDGPU: Fix off by one error in register parsing
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2015-11-03 Matt ArsenaultAMDGPU: s[102:103] is unavailable on VI
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2015-11-03 Matt ArsenaultAMDGPU: Define correct number of SGPRs
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2015-11-03 Matt ArsenaultAMDGPU: Make findUsedSGPR more readable
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2015-11-03 Matt ArsenaultAMDGPU: Initialize SIFixSGPRCopies so -print-after...
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2015-11-03 Matt ArsenaultAMDGPU: Alphabetize includes
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2015-11-02 Matt ArsenaultAMDGPU: Stop assuming vreg for build_vector
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2015-11-02 Matt ArsenaultAMDGPU: Error on graphics shaders with HSA
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2015-11-02 Matt ArsenaultAMDGPU: Un XFAIL a test
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2015-11-02 Matt ArsenaultAMDGPU: Distribute SGPR->VGPR copies of REG_SEQUENCE
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2015-10-24 Matt ArsenaultAMDGPU: Print modifiers when dumping AMDGPUOperand
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2015-10-23 Matt ArsenaultAMDGPU: Fix parsing of 32-bit literals with sign bit set
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2015-10-21 Matt ArsenaultAMDGPU: Fix adding redundant m0 uses
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2015-10-21 Matt ArsenaultAMDGPU: Fix verifier error in SIFoldOperands
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2015-10-21 Matt ArsenaultAMDGPU: Split DiagnosticInfoUnsupported into its own...
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2015-10-21 Matt ArsenaultAMDGPU: Simplify VOP3 operand legalization.
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2015-10-21 Matt ArsenaultAMDGPU: Fix not checking implicit operands in verifyInstruction
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2015-10-21 Matt ArsenaultUse numeric_limits instead of LLONG_MAX
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2015-10-21 Matt ArsenaultLegalizeDAG: Implement promote for build_vector
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2015-10-20 Matt ArsenaultAMDGPU: Add MachineInstr overloads for instruction...
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2015-10-20 Matt ArsenaultAMDGPU: Stop reserving v[254:255]
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2015-10-13 Matt ArsenaultDAGCombiner: Don't stop finding better chain on 2 aliases
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2015-10-13 Matt ArsenaultAMDGPU: Refactor isVGPRToSGPRCopy
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2015-10-12 Matt ArsenaultDAGCombiner: Combine extract_vector_elt from build_vector
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2015-10-12 Matt ArsenaultAMDGPU: Register some more passes so -print-before...
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2015-10-12 Matt ArsenaultEnable verifier after PeepholeOptimizer
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2015-10-07 Matt ArsenaultAMDGPU: Fix missing implicit m0 uses on movrel instructions
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2015-10-07 Matt ArsenaultAMDGPU: Add comment for VOP2b operand class
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2015-10-07 Matt ArsenaultAMDGPU: Properly register passes
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2015-10-07 Matt ArsenaultAMDGPU: Use explicit register size indirect pseudos
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2015-10-07 Matt ArsenaultAMDGPU: Remove inferRegClassFromUses / inferRegClassFromDefs
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2015-10-02 Matt ArsenaultAMDGPU/SI: Add verifier check for exec reads
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2015-10-02 Matt ArsenaultAdd way to test for generic TargetOpcodes
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2015-10-01 Matt ArsenaultAMDGPU: Fix unused variable warning in release build
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2015-10-01 Matt ArsenaultAMDGPU: Move SIFixSGPRLiveRanges to be a regalloc pass
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2015-10-01 Matt ArsenaultAMDGPU: Merge if and switch
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2015-10-01 Matt ArsenaultAMDGPU: Remove dead code
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2015-10-01 Matt ArsenaultAMDGPU: Make SIInsertWaits about a factor of 4 faster
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2015-09-28 Matt ArsenaultAMDGPU: Factor switch into separate function
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2015-09-28 Matt ArsenaultAMDGPU: Fix splitting x16 SMRD loads
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2015-09-28 Matt ArsenaultAMDGPU: Fix moving SMRD loads with literal offsets...
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2015-09-28 Matt ArsenaultAMDGPU: Fix splitting SMRD with large offset
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2015-09-28 Matt ArsenaultAMDGPU: Add testcases
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C/C++ LLVM-based compilers that forbids OOTA behaviors