HexagonMCInst.h: Qualify constants explicitly to appease msc17.
[oota-llvm.git] / test / CodeGen /
2014-12-03 Hal Finkel[PowerPC] Fix inline asm memory operands not to use r0
2014-12-03 Quentin Colombet[RegAllocFast] Handle implicit definitions conservatively.
2014-12-03 Rafael EspindolaThis reverts commit r223306 and r223277.
2014-12-03 Kevin EnderbyAdd support to llvm-objdump for Mach-O universal files...
2014-12-03 Tim NorthoverAArch64: fix wrong-endian parameter passing.
2014-12-03 Hal Finkel[PowerPC] Print all inline-asm consts as signed numbers
2014-12-03 Charlie TurnerEmit ABI_FP_rounding attribute.
2014-12-03 Charlie TurnerAdd tests for default value of Tag_ABI_FP_rounding.
2014-12-03 Matt ArsenaultR600/SI: Remove i1 pseudo VALU ops
2014-12-03 Tom StellardR600/SI: Enable inline assembly
2014-12-03 Matt ArsenaultR600/SI: Change mubuf offsets to print as decimal
2014-12-03 Peter CollingbournePrologue support
2014-12-03 Hal Finkel[PowerPC] Fix readcyclecounter to be custom expanded...
2014-12-02 Tim NorthoverAArch64: strengthen Darwin ABI alignment assumptions
2014-12-02 Tim NorthoverAArch64: don't be too greedy when folding :lo12: access...
2014-12-02 Simon Pilgrim[X86][SSE] Keep 4i32 vector insertions in integer domai...
2014-12-02 Hal Finkel[PowerPC] Implement readcyclecounter for PPC32
2014-12-02 Lang Hames[AArch64][Stackmaps] Optimize stackmap shadows on AArch64.
2014-12-02 Tom StellardR600/SI: Move more information into SIProgramInfo struct
2014-12-02 Matt ArsenaultR600: Cleanup some tests and add missing testcases
2014-12-02 Daniel Sanders[mips] Fix passing of small structures for big-endian...
2014-12-02 Philip Reames[Statepoints 3/4] Statepoint infrastructure for garbage...
2014-12-02 Ahmed Bougacha[MachineCSE] Clear kill-flag on registers imp-def'd...
2014-12-02 Tim NorthoverAArch64: make register block rules apply to vector...
2014-12-02 Tom StellardR600/SI: Set the ATC bit on all resource descriptors...
2014-12-02 Charlie TurnerEmit Tag_ABI_FP_denormal correctly in fast-math mode.
2014-12-01 Jingyue Wu[NVPTX] Do not emit .weak symbols for NVPTX
2014-12-01 Reid KlecknerParse 'ghccc' in .ll files as the GHC convention (cc 10)
2014-12-01 Ahmed Bougacha[AArch64] Don't combine "select (setcc i1 LHS, RHS...
2014-12-01 Ahmed Bougacha[AArch64] Fix v2i8->i16 bitcast legalization.
2014-12-01 Ahmed Bougacha[MachineVerifier] Accept a MBB with a single landing...
2014-12-01 Tim NorthoverARM: lower tail calls correctly when using GHC calling...
2014-12-01 Hans WennborgRevert r223049, r223050 and r223051 while investigating...
2014-12-01 Hans WennborgSelectionDAG switch lowering: Replace unreachable defau...
2014-12-01 Jay Foad[PowerPC] Fix unwind info with dynamic stack realignment
2014-12-01 Akira Hatanaka[stack protector] Set edge weights for newly created...
2014-11-29 Hans WennborgSwitch lowering: Fix broken 'Figure out which block...
2014-11-28 Matt ArsenaultR600/SI: Fix assertion on sign extend of 3 vectors
2014-11-28 Duncan P. N. Exon... Revert "Masked Vector Load and Store Intrinsics."
2014-11-28 Sanjay PatelEnable FeatureFastUAMem for btver2
2014-11-27 Tim NorthoverAArch64: treat [N x Ty] as a block during procedure...
2014-11-27 Charlie TurnerStop uppercasing build attribute data.
2014-11-26 Will NewtonUpdate AArch64 ELF relocations to ABI 1.0
2014-11-26 Elena DemikhovskyAVX-512: Scalar ERI intrinsics
2014-11-25 Simon Pilgrim[X86][SSE] Improvements to byte shift shuffle matching
2014-11-25 Cameron McInally[AVX512] Add 512b integer shift by variable intrinsics...
2014-11-25 Zoran Jovanovic[mips][micromips] Use call instructions with short...
2014-11-25 Juergen Ributzka[FastISel][AArch64] Fix and extend the tbz/tbnz pattern...
2014-11-24 Hal Finkel[PowerPC] Implement combineRepeatedFPDivisors
2014-11-24 Andrea Di Biagio[X86] Improved target specific combine on VSELECT dag...
2014-11-23 Michael Kuperstein[X86] Fixes bug in build_vector v4x32 lowering
2014-11-23 Elena DemikhovskyMasked Vector Load and Store Intrinsics.
2014-11-23 Matt ArsenaultR600: Fix extloads of i1 on R600/Evergreen
2014-11-23 Matt ArsenaultR600/SI: Add additional tests for i1 loads
2014-11-23 Matt ArsenaultR600/SI: Fix broken check lines and modernize prefixes
2014-11-23 Matt ArsenaultR600/SI: Fix missing -verify-machineinstrs on a test
2014-11-22 Chandler Carruth[x86] Add some tests for a common unpack pattern of...
2014-11-21 Tom StellardR600/SI: Add a failing test case for offset order in...
2014-11-21 Tom StellardR600/SI: Emit s_mov_b32 m0, -1 before every DS instruction
2014-11-21 Tom StellardR600/SI: Add SIFoldOperands pass
2014-11-21 Jozef Kolek[mips][microMIPS] This patch implements functionality...
2014-11-21 Tom StellardR600/SI: Use hex notation for constant in test
2014-11-21 Sanjay PatelAdd a feature flag for slow 32-byte unaligned memory...
2014-11-21 Chandler Carruth[x86] Restructure the checking patterns for v16 and...
2014-11-21 Chandler Carruth[x86] Make the previous logic significantly less conser...
2014-11-21 Andrea Di Biagio[DAG] Teach how to turn a build_vector into a shuffle...
2014-11-21 Chandler Carruth[x86] Teach the x86 vector shuffle lowering to detect...
2014-11-21 Chandler Carruth[x86] Remove more windows line endings that slipped...
2014-11-21 Chandler Carruth[x86] Add a bunch of test cases to 256-bit shuffles...
2014-11-21 Alexey Volkov[X86] For Silvermont CPU use 16-bit division instead...
2014-11-21 Hao LiuDAGCombiner: Allow the DAGCombiner to combine multiple...
2014-11-21 Hal Finkel[PPC] Use SeparateConstOffsetFromGEP
2014-11-21 Quentin Colombet[X86] Do not custom lower UINT_TO_FP when the target...
2014-11-20 Saleem AbdulrasoolX86: use the correct alloca symbol for Windows Itanium
2014-11-19 Andrea Di Biagio[X86] Improved lowering of v4x32 build_vector dag nodes.
2014-11-19 Tom StellardR600/SI: Make SIInstrInfo::isOperandLegal() more strict
2014-11-19 Jozef Kolek[mips][microMIPS] Implement CodeGen support for 16...
2014-11-19 Jozef Kolek[mips][microMIPS] Implement CodeGen support for ADDIUS5...
2014-11-19 Jozef Kolek[mips][microMIPS] Implement SDBBP and RDHWR instructions.
2014-11-19 Simon Pilgrim[X86][SSE] pslldq/psrldq byte shifts/rotation for SSE2
2014-11-19 Hao Liu[AArch64] Enable SeparateConstOffsetFromGEP, EarlyCSE...
2014-11-19 Weiming Zhao[Aarch64] Customer lowering of CTPOP to SIMD should...
2014-11-19 Matt ArsenaultR600/SI: Implement areMemAccessesTriviallyDisjoint
2014-11-18 Simon Pilgrim[X86][AVX] 256-bit vector stack unaligned load/stores...
2014-11-18 Chad Rosier[FastISel][AArch64] Also allow folding of sign-/zero...
2014-11-18 Chad Rosier[FastISel][AArch64] Also allow folding of sign-/zero...
2014-11-18 Juergen Ributzka[FastISel][AArch64] Follow-up fix for "Fix shift-immedi...
2014-11-18 Matt ArsenaultR600/SI: Move SIFixSGPRCopies to inst selector passes
2014-11-18 Tom StellardR600/SI: Make sure resource descriptors are always...
2014-11-18 Juergen Ributzka[FastISel][AArch64] Fix shift-immediate emission for...
2014-11-17 Alexey Volkov[X86] Use ADD/SUB instead of INC/DEC for Haswell and...
2014-11-17 Renato GolinFix ARM triple parsing
2014-11-17 Oliver Stannard[Thumb1] Re-write emitThumbRegPlusImmediate
2014-11-17 Oliver StannardFix optimisations of SELECT_CC which assumed result...
2014-11-17 Bob WilsonFix CR/LF line endings in test case.
2014-11-15 Andrea Di Biagio[DAG] Improved target independent vector shuffle foldin...
2014-11-15 Simon Pilgrim[X86][SSE] Improve legal SHUFP and PSHUFD shuffle matching
2014-11-15 Matt ArsenaultR600: Permute operands when selecting legacy min/max
2014-11-14 Tim NorthoverARM: refactor .cfi_def_cfa_offset emission.
2014-11-14 Tim NorthoverARM: correctly calculate the offset of FP in its push.
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