Enable (sext x) == C --> x == (trunc C) combine
[oota-llvm.git] / lib / Target / R600 / SIISelLowering.cpp
2014-12-21 Matt ArsenaultEnable (sext x) == C --> x == (trunc C) combine
2014-12-17 Matt ArsenaultR600/SI: Fix f64 inline immediates
2014-12-12 Matt ArsenaultR600/SI: Don't promote f32 select to i32
2014-12-11 Matt ArsenaultR600/SI: Use unordered equal instructions
2014-12-11 Matt ArsenaultR600/SI: Make more unordered comparisons legal
2014-12-11 Matt ArsenaultR600/SI: Use unordered not equal instructions
2014-12-10 Marek OlsakR600/SI: Use getTargetConstant in AdjustRegClass
2014-12-07 Marek OlsakR600/SI: Set 20-bit immediate byte offset for SMRD...
2014-12-02 Tom StellardR600/SI: Set correct number of user sgprs for HSA runtime
2014-12-02 Tom StellardR600/SI: Set the ATC bit on all resource descriptors...
2014-11-28 Matt ArsenaultR600/SI: Fix assertion on sign extend of 3 vectors
2014-11-21 Tom StellardR600/SI: Emit s_mov_b32 m0, -1 before every DS instruction
2014-11-18 Tom StellardR600/SI: Make sure resource descriptors are always...
2014-11-16 Craig TopperConvert some EVTs to MVTs where only a SimpleValueType...
2014-11-14 Matt ArsenaultR600/SI: Combine min3/max3 instructions
2014-11-14 Matt ArsenaultR600/SI: Use S_BFE_I64 for 64-bit sext_inreg
2014-11-13 Matt ArsenaultR600/SI: Get rid of FCLAMP_SI pseudo
2014-11-05 Matt ArsenaultR600/SI: Move all rsrc building functions to SIISelLowering
2014-11-05 Matt ArsenaultR600/SI: Remove SI_ADDR64_RSRC
2014-11-02 Matt ArsenaultR600/SI: Use REG_SEQUENCE instead of INSERT_SUBREGs
2014-10-21 Matt ArsenaultAdd minnum / maxnum codegen
2014-10-21 Matt ArsenaultR600/SI: Add pattern for bswap
2014-10-17 Matt ArsenaultR600/SI: Remove SI_BUFFER_RSRC pseudo
2014-10-14 Jan VeselyReapply "R600: Add new intrinsic to read work dimensions"
2014-10-14 Rafael EspindolaRevert "R600: Add new intrinsic to read work dimensions"
2014-10-14 Jan VeselyR600: Add new intrinsic to read work dimensions
2014-10-09 Tom StellardR600/SI: Legalize CopyToReg during instruction selection
2014-10-09 Tom StellardR600/SI: Legalize INSERT_SUBREG instructions during...
2014-10-03 Matt ArsenaultR600/SI: Custom lower f64 -> i64 conversions
2014-09-29 Matt ArsenaultR600/SI: Also fix fsub + fadd a, a to mad combines
2014-09-29 Matt ArsenaultR600/SI: Fix using mad with multiplies by 2
2014-09-26 Matt ArsenaultR600/SI: Partially move operand legalization to post...
2014-09-26 Matt ArsenaultR600/SI: Remove apparently dead code in legalizeOperands
2014-09-23 Tom StellardR600/SI: Clean up checks for legality of immediate...
2014-09-22 Tom StellardR600/SI: Add enums for some hard-coded values
2014-09-17 Matt ArsenaultR600/SI: Remove promotion of instructions to e64 forms.
2014-09-10 Matt ArsenaultR600/SI: Fix losing chain when fixing reg class of...
2014-09-08 Matt ArsenaultR600/SI: Fix assertion from copying a TargetGlobalAddress
2014-09-08 Matt ArsenaultR600/SI: Replace LDS atomics with no return versions
2014-08-29 Matt ArsenaultR600/SI: Use mad for fsub + fmul
2014-08-27 Alexey SamsonovUse BitVector instead of int in R600 SIISelLowering.
2014-08-22 Tom StellardR600/SI: Wrap local memory pointer in AssertZExt on SI
2014-08-21 Tom StellardR600/SI: Make sure SCRATCH_WAVE_OFFSET is added as...
2014-08-18 Aaron BallmanSilencing an MSVC warning about loop variable conflicti...
2014-08-15 Matt ArsenaultR600/SI: Move all fabs / fneg handling to patterns
2014-08-15 Matt ArsenaultR600/SI: Use source modifiers for f64 fneg
2014-08-15 Matt ArsenaultR600/SI: Use source modifier for f64 fabs
2014-08-15 Matt ArsenaultR600/SI: Fix offset folding in some cases with shifted...
2014-08-15 Matt ArsenaultR600/SI: Implement isLegalAddressingMode
2014-08-09 Tom StellardR600/SI: Custom lower CONCAT_VECTORS
2014-08-06 Eric ChristopherRemove the target machine from CCState. Previously...
2014-08-04 Eric ChristopherRemove the TargetMachine forwards for TargetSubtargetIn...
2014-08-02 Matt ArsenaultR600/SI: Fix formatting.
2014-08-01 Chandler Carruth[SDAG] MorphNodeTo recursively deletes dead operands...
2014-08-01 Tom StellardR600/SI: Do abs/neg folding with ComplexPatterns
2014-07-28 Matt ArsenaultR600/SI: Implement getOptimalMemOpType
2014-07-28 Matt ArsenaultR600/SI: Make argument loads invariant
2014-07-27 Matt ArsenaultAdd alignment value to allowsUnalignedMemoryAccess
2014-07-26 Matt ArsenaultR600: Move intrinsic lowering to separate functions
2014-07-24 Matt ArsenaultR600: Add new functions for splitting vector loads...
2014-07-21 Tom StellardR600/SI: Clean up some of the unused REGISTER_{LOAD...
2014-07-21 Tom StellardR600/SI: Use scratch memory for large private arrays
2014-07-21 Tom StellardR600/SI: Store constant initializer data in constant...
2014-07-20 NAKAMURA TakumiSIISelLowering.cpp: Define _USE_MATH_DEFINES to let...
2014-07-20 Matt ArsenaultR600/SI: Remove dead code and add missing tests.
2014-07-19 Matt ArsenaultR600/SI: implement range reduction for sin/cos
2014-07-15 Matt ArsenaultR600/SI: Allow using f32 rcp / rsq when denormals not...
2014-07-15 Matt ArsenaultR600/SI: Fix select on i1
2014-07-15 Matt ArsenaultR600/SI: Implement less wrong f32 fdiv
2014-07-13 Matt ArsenaultR600: Make ShaderType private
2014-07-10 Jan VeselyR600: Implement float to long/ulong
2014-07-07 Matt ArsenaultR600: Fix mishandling of load / store chains.
2014-07-03 Chandler Carruth[codegen,aarch64] Add a target hook to the code generat...
2014-07-02 Tom StellardR600: Promote i64 loads to v2i32
2014-06-24 Tom StellardR600: Promote i64 stores to v2i32
2014-06-23 Matt ArsenaultR600: Move more out of AMDILISelLowering
2014-06-23 Matt ArsenaultR600/SI: Handle i64 sub.
2014-06-23 Matt ArsenaultR600: Rename AMDIL file
2014-06-18 Matt ArsenaultR600/SI: Prettier operand printing for 64-bit ops.
2014-06-18 Matt ArsenaultR600/SI: Temporary fix for f64 fneg
2014-06-11 Matt ArsenaultR600/SI: Use v_cvt_f32_ubyte* instructions
2014-06-10 Matt ArsenaultR600: Use BCNT_INT for evergreen
2014-06-10 Matt ArsenaultR600/SI: Implement i64 ctpop
2014-06-10 Matt ArsenaultR600/SI: Use bcnt instruction for ctpop
2014-06-10 Matt ArsenaultR600/SI: Handle sign_extend and zero_extend to i64...
2014-06-10 Tom StellardSelectionDAG: Expand SELECT_CC to SELECT + SETCC
2014-06-05 Matt ArsenaultUse nullptr
2014-06-03 Matt ArsenaultFix typos
2014-05-22 Matt ArsenaultR600: Add dag combine for BFE
2014-05-16 Tom StellardR600/SI: Promote f32 SELECT to i32
2014-05-15 Matt ArsenaultUse range for
2014-05-15 Tom StellardR600/SI: Stop using VSrc_* as the default register...
2014-05-10 Vincent LejeuneR600/SI: Fold fabs/fneg into src input modifier
2014-05-10 Vincent LejeuneR600/SI: Prettier display of input modifiers
2014-05-10 Vincent LejeuneR600/SI: Use pseudo instruction for fabs/clamp/fneg
2014-05-09 Tom StellardR600: Move MIN/MAX matching from LowerOperation() to...
2014-04-30 Tom StellardR600/SI: Use VALU instructions for copying i1 values
2014-04-29 Tom StellardR600/SI: Custom lower SI_IF and SI_ELSE to avoid machin...
2014-04-29 Tom StellardR600: Change UDIV/UREM to UDIVREM when legalizing types
2014-04-28 Craig TopperConvert more SelectionDAG functions to use ArrayRef.
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