1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for SI
13 //===----------------------------------------------------------------------===//
15 #include "SIISelLowering.h"
17 #include "AMDGPUSubtarget.h"
18 #include "AMDILIntrinsicInfo.h"
19 #include "SIInstrInfo.h"
20 #include "SIMachineFunctionInfo.h"
21 #include "SIRegisterInfo.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/IR/Function.h"
30 SITargetLowering::SITargetLowering(TargetMachine &TM) :
31 AMDGPUTargetLowering(TM) {
32 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
33 addRegisterClass(MVT::i64, &AMDGPU::VSrc_64RegClass);
35 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
36 addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass);
38 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
39 addRegisterClass(MVT::f32, &AMDGPU::VSrc_32RegClass);
41 addRegisterClass(MVT::f64, &AMDGPU::VSrc_64RegClass);
42 addRegisterClass(MVT::v2i32, &AMDGPU::VSrc_64RegClass);
43 addRegisterClass(MVT::v2f32, &AMDGPU::VSrc_64RegClass);
45 addRegisterClass(MVT::v4i32, &AMDGPU::VSrc_128RegClass);
46 addRegisterClass(MVT::v4f32, &AMDGPU::VSrc_128RegClass);
48 addRegisterClass(MVT::v8i32, &AMDGPU::VReg_256RegClass);
49 addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
51 addRegisterClass(MVT::v16i32, &AMDGPU::VReg_512RegClass);
52 addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
54 computeRegisterProperties();
57 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
58 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
59 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
60 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
61 setCondCodeAction(ISD::SETULE, MVT::f32, Expand);
62 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
64 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
65 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
66 setCondCodeAction(ISD::SETUGE, MVT::f64, Expand);
67 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
68 setCondCodeAction(ISD::SETULE, MVT::f64, Expand);
69 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
71 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
72 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
73 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
74 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
76 setOperationAction(ISD::ADD, MVT::i32, Legal);
77 setOperationAction(ISD::ADDC, MVT::i32, Legal);
78 setOperationAction(ISD::ADDE, MVT::i32, Legal);
80 // We need to custom lower vector stores from local memory
81 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
82 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
83 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
84 setOperationAction(ISD::LOAD, MVT::v16i32, Custom);
86 setOperationAction(ISD::STORE, MVT::v8i32, Custom);
87 setOperationAction(ISD::STORE, MVT::v16i32, Custom);
89 // We need to custom lower loads/stores from private memory
90 setOperationAction(ISD::LOAD, MVT::i32, Custom);
91 setOperationAction(ISD::LOAD, MVT::i64, Custom);
92 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
93 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
94 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
96 setOperationAction(ISD::STORE, MVT::i1, Custom);
97 setOperationAction(ISD::STORE, MVT::i32, Custom);
98 setOperationAction(ISD::STORE, MVT::i64, Custom);
99 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
100 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
102 setOperationAction(ISD::SELECT, MVT::i64, Custom);
103 setOperationAction(ISD::SELECT, MVT::f64, Promote);
104 AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
106 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
107 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
109 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
111 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
112 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
114 setOperationAction(ISD::ANY_EXTEND, MVT::i64, Custom);
115 setOperationAction(ISD::SIGN_EXTEND, MVT::i64, Custom);
116 setOperationAction(ISD::ZERO_EXTEND, MVT::i64, Custom);
118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Legal);
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
120 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
122 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Legal);
123 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
124 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
126 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
127 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
128 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
130 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Custom);
132 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom);
134 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
135 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom);
136 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v16i8, Custom);
137 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
139 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
141 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
142 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Custom);
143 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Custom);
144 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Expand);
145 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, Expand);
146 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, Expand);
148 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
149 setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom);
150 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Custom);
151 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Expand);
153 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
154 setLoadExtAction(ISD::EXTLOAD, MVT::i8, Custom);
155 setLoadExtAction(ISD::EXTLOAD, MVT::i16, Custom);
156 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Expand);
157 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
159 setTruncStoreAction(MVT::i32, MVT::i8, Custom);
160 setTruncStoreAction(MVT::i32, MVT::i16, Custom);
161 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
162 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
163 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand);
164 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand);
166 setOperationAction(ISD::LOAD, MVT::i1, Custom);
168 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
169 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
170 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
172 // These should use UDIVREM, so set them to expand
173 setOperationAction(ISD::UDIV, MVT::i64, Expand);
174 setOperationAction(ISD::UREM, MVT::i64, Expand);
176 // We only support LOAD/STORE and vector manipulation ops for vectors
177 // with > 4 elements.
179 MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32
182 const size_t NumVecTypes = array_lengthof(VecTypes);
183 for (unsigned Type = 0; Type < NumVecTypes; ++Type) {
184 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
188 case ISD::BUILD_VECTOR:
190 case ISD::EXTRACT_VECTOR_ELT:
191 case ISD::INSERT_VECTOR_ELT:
192 case ISD::CONCAT_VECTORS:
193 case ISD::INSERT_SUBVECTOR:
194 case ISD::EXTRACT_SUBVECTOR:
197 setOperationAction(Op, VecTypes[Type], Expand);
203 for (int I = MVT::v1f64; I <= MVT::v8f64; ++I) {
204 MVT::SimpleValueType VT = static_cast<MVT::SimpleValueType>(I);
205 setOperationAction(ISD::FTRUNC, VT, Expand);
206 setOperationAction(ISD::FCEIL, VT, Expand);
207 setOperationAction(ISD::FFLOOR, VT, Expand);
210 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS) {
211 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
212 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
213 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
214 setOperationAction(ISD::FRINT, MVT::f64, Legal);
217 setTargetDAGCombine(ISD::SELECT_CC);
218 setTargetDAGCombine(ISD::SETCC);
220 setSchedulingPreference(Sched::RegPressure);
223 //===----------------------------------------------------------------------===//
224 // TargetLowering queries
225 //===----------------------------------------------------------------------===//
227 bool SITargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
229 bool *IsFast) const {
233 // XXX: This depends on the address space and also we may want to revist
234 // the alignment values we specify in the DataLayout.
236 // TODO: I think v3i32 should allow unaligned accesses on CI with DS_READ_B96,
237 // which isn't a simple VT.
238 if (!VT.isSimple() || VT == MVT::Other)
241 // XXX - CI changes say "Support for unaligned memory accesses" but I don't
242 // see what for specifically. The wording everywhere else seems to be the
245 // 3.6.4 - Operations using pairs of VGPRs (for example: double-floats) have
246 // no alignment restrictions.
247 if (AddrSpace == AMDGPUAS::PRIVATE_ADDRESS) {
248 // Using any pair of GPRs should be the same as any other pair.
251 return VT.bitsGE(MVT::i64);
254 // XXX - The only mention I see of this in the ISA manual is for LDS direct
255 // reads the "byte address and must be dword aligned". Is it also true for the
256 // normal loads and stores?
257 if (AddrSpace == AMDGPUAS::LOCAL_ADDRESS)
260 // 8.1.6 - For Dword or larger reads or writes, the two LSBs of the
261 // byte-address are ignored, thus forcing Dword alignment.
264 return VT.bitsGT(MVT::i32);
267 bool SITargetLowering::shouldSplitVectorType(EVT VT) const {
268 return VT.getScalarType().bitsLE(MVT::i16);
271 bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
273 const SIInstrInfo *TII =
274 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
275 return TII->isInlineConstant(Imm);
278 SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
279 SDLoc DL, SDValue Chain,
280 unsigned Offset, bool Signed) const {
281 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
282 PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
283 AMDGPUAS::CONSTANT_ADDRESS);
284 SDValue BasePtr = DAG.getCopyFromReg(Chain, DL,
285 MRI.getLiveInVirtReg(AMDGPU::SGPR0_SGPR1), MVT::i64);
286 SDValue Ptr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
287 DAG.getConstant(Offset, MVT::i64));
288 return DAG.getExtLoad(Signed ? ISD::SEXTLOAD : ISD::ZEXTLOAD, DL, VT, Chain, Ptr,
289 MachinePointerInfo(UndefValue::get(PtrTy)), MemVT,
290 false, false, MemVT.getSizeInBits() >> 3);
294 SDValue SITargetLowering::LowerFormalArguments(
296 CallingConv::ID CallConv,
298 const SmallVectorImpl<ISD::InputArg> &Ins,
299 SDLoc DL, SelectionDAG &DAG,
300 SmallVectorImpl<SDValue> &InVals) const {
302 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
304 MachineFunction &MF = DAG.getMachineFunction();
305 FunctionType *FType = MF.getFunction()->getFunctionType();
306 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
308 assert(CallConv == CallingConv::C);
310 SmallVector<ISD::InputArg, 16> Splits;
311 uint32_t Skipped = 0;
313 for (unsigned i = 0, e = Ins.size(), PSInputNum = 0; i != e; ++i) {
314 const ISD::InputArg &Arg = Ins[i];
316 // First check if it's a PS input addr
317 if (Info->ShaderType == ShaderType::PIXEL && !Arg.Flags.isInReg() &&
318 !Arg.Flags.isByVal()) {
320 assert((PSInputNum <= 15) && "Too many PS inputs!");
323 // We can savely skip PS inputs
329 Info->PSInputAddr |= 1 << PSInputNum++;
332 // Second split vertices into their elements
333 if (Info->ShaderType != ShaderType::COMPUTE && Arg.VT.isVector()) {
334 ISD::InputArg NewArg = Arg;
335 NewArg.Flags.setSplit();
336 NewArg.VT = Arg.VT.getVectorElementType();
338 // We REALLY want the ORIGINAL number of vertex elements here, e.g. a
339 // three or five element vertex only needs three or five registers,
340 // NOT four or eigth.
341 Type *ParamType = FType->getParamType(Arg.OrigArgIndex);
342 unsigned NumElements = ParamType->getVectorNumElements();
344 for (unsigned j = 0; j != NumElements; ++j) {
345 Splits.push_back(NewArg);
346 NewArg.PartOffset += NewArg.VT.getStoreSize();
349 } else if (Info->ShaderType != ShaderType::COMPUTE) {
350 Splits.push_back(Arg);
354 SmallVector<CCValAssign, 16> ArgLocs;
355 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
356 getTargetMachine(), ArgLocs, *DAG.getContext());
358 // At least one interpolation mode must be enabled or else the GPU will hang.
359 if (Info->ShaderType == ShaderType::PIXEL && (Info->PSInputAddr & 0x7F) == 0) {
360 Info->PSInputAddr |= 1;
361 CCInfo.AllocateReg(AMDGPU::VGPR0);
362 CCInfo.AllocateReg(AMDGPU::VGPR1);
365 // The pointer to the list of arguments is stored in SGPR0, SGPR1
366 if (Info->ShaderType == ShaderType::COMPUTE) {
367 CCInfo.AllocateReg(AMDGPU::SGPR0);
368 CCInfo.AllocateReg(AMDGPU::SGPR1);
369 MF.addLiveIn(AMDGPU::SGPR0_SGPR1, &AMDGPU::SReg_64RegClass);
372 if (Info->ShaderType == ShaderType::COMPUTE) {
373 getOriginalFunctionArgs(DAG, DAG.getMachineFunction().getFunction(), Ins,
377 AnalyzeFormalArguments(CCInfo, Splits);
379 for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
381 const ISD::InputArg &Arg = Ins[i];
382 if (Skipped & (1 << i)) {
383 InVals.push_back(DAG.getUNDEF(Arg.VT));
387 CCValAssign &VA = ArgLocs[ArgIdx++];
388 EVT VT = VA.getLocVT();
392 EVT MemVT = Splits[i].VT;
393 // The first 36 bytes of the input buffer contains information about
394 // thread group and global sizes.
395 SDValue Arg = LowerParameter(DAG, VT, MemVT, DL, DAG.getRoot(),
396 36 + VA.getLocMemOffset(),
397 Ins[i].Flags.isSExt());
398 InVals.push_back(Arg);
401 assert(VA.isRegLoc() && "Parameter must be in a register!");
403 unsigned Reg = VA.getLocReg();
405 if (VT == MVT::i64) {
406 // For now assume it is a pointer
407 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
408 &AMDGPU::SReg_64RegClass);
409 Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass);
410 InVals.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
414 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
416 Reg = MF.addLiveIn(Reg, RC);
417 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
419 if (Arg.VT.isVector()) {
421 // Build a vector from the registers
422 Type *ParamType = FType->getParamType(Arg.OrigArgIndex);
423 unsigned NumElements = ParamType->getVectorNumElements();
425 SmallVector<SDValue, 4> Regs;
427 for (unsigned j = 1; j != NumElements; ++j) {
428 Reg = ArgLocs[ArgIdx++].getLocReg();
429 Reg = MF.addLiveIn(Reg, RC);
430 Regs.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
433 // Fill up the missing vector elements
434 NumElements = Arg.VT.getVectorNumElements() - NumElements;
435 for (unsigned j = 0; j != NumElements; ++j)
436 Regs.push_back(DAG.getUNDEF(VT));
438 InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT, Regs));
442 InVals.push_back(Val);
447 /// Usually ISel will insert a copy between terminator insturction that output
448 /// a value and the S_BRANCH* at the end of the block. This causes
449 /// MachineBasicBlock::getFirstTerminator() to return the incorrect value,
450 /// so we want to make sure there are no copies between terminators at the
452 static void LowerTerminatorWithOutput(unsigned Opcode, MachineBasicBlock *BB,
454 const TargetInstrInfo *TII,
455 MachineRegisterInfo &MRI) {
456 unsigned DstReg = MI->getOperand(0).getReg();
457 // Usually ISel will insert a copy between the SI_IF_NON_TERM instruction
458 // and the S_BRANCH* terminator. We want to replace SI_IF_NO_TERM with
459 // SI_IF and we can't have any instructions between S_BRANCH* and SI_IF,
460 // since they are both terminators
461 assert(MRI.hasOneUse(DstReg));
462 MachineOperand &Use = *MRI.use_begin(DstReg);
463 MachineInstr *UseMI = Use.getParent();
464 assert(UseMI->getOpcode() == AMDGPU::COPY);
466 MRI.replaceRegWith(UseMI->getOperand(0).getReg(), DstReg);
467 UseMI->eraseFromParent();
468 BuildMI(*BB, BB->getFirstTerminator(), MI->getDebugLoc(),
470 .addOperand(MI->getOperand(0))
471 .addOperand(MI->getOperand(1))
472 .addOperand(MI->getOperand(2));
473 MI->eraseFromParent();
476 MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
477 MachineInstr * MI, MachineBasicBlock * BB) const {
479 MachineBasicBlock::iterator I = *MI;
480 const SIInstrInfo *TII =
481 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
482 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
484 switch (MI->getOpcode()) {
486 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
487 case AMDGPU::BRANCH: return BB;
488 case AMDGPU::SI_ADDR64_RSRC: {
489 unsigned SuperReg = MI->getOperand(0).getReg();
490 unsigned SubRegLo = MRI.createVirtualRegister(&AMDGPU::SGPR_64RegClass);
491 unsigned SubRegHi = MRI.createVirtualRegister(&AMDGPU::SGPR_64RegClass);
492 unsigned SubRegHiHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
493 unsigned SubRegHiLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
494 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B64), SubRegLo)
495 .addOperand(MI->getOperand(1));
496 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiLo)
498 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiHi)
499 .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
500 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SubRegHi)
502 .addImm(AMDGPU::sub0)
504 .addImm(AMDGPU::sub1);
505 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SuperReg)
507 .addImm(AMDGPU::sub0_sub1)
509 .addImm(AMDGPU::sub2_sub3);
510 MI->eraseFromParent();
513 case AMDGPU::SI_IF_NON_TERM:
514 LowerTerminatorWithOutput(AMDGPU::SI_IF, BB, MI, TII, MRI);
516 case AMDGPU::SI_ELSE_NON_TERM:
517 LowerTerminatorWithOutput(AMDGPU::SI_ELSE, BB, MI, TII, MRI);
519 case AMDGPU::V_SUB_F64:
520 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F64),
521 MI->getOperand(0).getReg())
522 .addReg(MI->getOperand(1).getReg())
523 .addReg(MI->getOperand(2).getReg())
524 .addImm(0) /* src2 */
526 .addImm(0) /* CLAMP */
527 .addImm(0) /* OMOD */
528 .addImm(2); /* NEG */
529 MI->eraseFromParent();
532 case AMDGPU::SI_RegisterStorePseudo: {
533 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
534 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
535 MachineInstrBuilder MIB =
536 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::SI_RegisterStore),
538 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
539 MIB.addOperand(MI->getOperand(i));
541 MI->eraseFromParent();
547 EVT SITargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
548 if (!VT.isVector()) {
551 return MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
554 MVT SITargetLowering::getScalarShiftAmountTy(EVT VT) const {
558 bool SITargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
559 VT = VT.getScalarType();
564 switch (VT.getSimpleVT().SimpleTy) {
566 return false; /* There is V_MAD_F32 for f32 */
576 //===----------------------------------------------------------------------===//
577 // Custom DAG Lowering Operations
578 //===----------------------------------------------------------------------===//
580 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
581 MachineFunction &MF = DAG.getMachineFunction();
582 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
583 switch (Op.getOpcode()) {
584 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
585 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
587 LoadSDNode *Load = dyn_cast<LoadSDNode>(Op);
588 if (Op.getValueType().isVector() &&
589 (Load->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
590 Load->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS ||
591 (Load->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS &&
592 Op.getValueType().getVectorNumElements() > 4))) {
593 SDValue MergedValues[2] = {
594 SplitVectorLoad(Op, DAG),
597 return DAG.getMergeValues(MergedValues, SDLoc(Op));
599 return LowerLOAD(Op, DAG);
603 case ISD::SELECT: return LowerSELECT(Op, DAG);
604 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
605 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
606 case ISD::STORE: return LowerSTORE(Op, DAG);
607 case ISD::ANY_EXTEND: // Fall-through
608 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, DAG);
609 case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG);
610 case ISD::INTRINSIC_WO_CHAIN: {
611 unsigned IntrinsicID =
612 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
613 EVT VT = Op.getValueType();
615 //XXX: Hardcoded we only use two to store the pointer to the parameters.
616 unsigned NumUserSGPRs = 2;
617 switch (IntrinsicID) {
618 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
619 case Intrinsic::r600_read_ngroups_x:
620 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 0, false);
621 case Intrinsic::r600_read_ngroups_y:
622 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 4, false);
623 case Intrinsic::r600_read_ngroups_z:
624 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 8, false);
625 case Intrinsic::r600_read_global_size_x:
626 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 12, false);
627 case Intrinsic::r600_read_global_size_y:
628 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 16, false);
629 case Intrinsic::r600_read_global_size_z:
630 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 20, false);
631 case Intrinsic::r600_read_local_size_x:
632 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 24, false);
633 case Intrinsic::r600_read_local_size_y:
634 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 28, false);
635 case Intrinsic::r600_read_local_size_z:
636 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 32, false);
637 case Intrinsic::r600_read_tgid_x:
638 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
639 AMDGPU::SReg_32RegClass.getRegister(NumUserSGPRs + 0), VT);
640 case Intrinsic::r600_read_tgid_y:
641 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
642 AMDGPU::SReg_32RegClass.getRegister(NumUserSGPRs + 1), VT);
643 case Intrinsic::r600_read_tgid_z:
644 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
645 AMDGPU::SReg_32RegClass.getRegister(NumUserSGPRs + 2), VT);
646 case Intrinsic::r600_read_tidig_x:
647 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
649 case Intrinsic::r600_read_tidig_y:
650 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
652 case Intrinsic::r600_read_tidig_z:
653 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
655 case AMDGPUIntrinsic::SI_load_const: {
661 MachineMemOperand *MMO = MF.getMachineMemOperand(
662 MachinePointerInfo(),
663 MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant,
664 VT.getSizeInBits() / 8, 4);
665 return DAG.getMemIntrinsicNode(AMDGPUISD::LOAD_CONSTANT, DL,
666 Op->getVTList(), Ops, VT, MMO);
668 case AMDGPUIntrinsic::SI_sample:
669 return LowerSampleIntrinsic(AMDGPUISD::SAMPLE, Op, DAG);
670 case AMDGPUIntrinsic::SI_sampleb:
671 return LowerSampleIntrinsic(AMDGPUISD::SAMPLEB, Op, DAG);
672 case AMDGPUIntrinsic::SI_sampled:
673 return LowerSampleIntrinsic(AMDGPUISD::SAMPLED, Op, DAG);
674 case AMDGPUIntrinsic::SI_samplel:
675 return LowerSampleIntrinsic(AMDGPUISD::SAMPLEL, Op, DAG);
676 case AMDGPUIntrinsic::SI_vs_load_input:
677 return DAG.getNode(AMDGPUISD::LOAD_INPUT, DL, VT,
684 case ISD::INTRINSIC_VOID:
685 SDValue Chain = Op.getOperand(0);
686 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
688 switch (IntrinsicID) {
689 case AMDGPUIntrinsic::SI_tbuffer_store: {
707 EVT VT = Op.getOperand(3).getValueType();
709 MachineMemOperand *MMO = MF.getMachineMemOperand(
710 MachinePointerInfo(),
711 MachineMemOperand::MOStore,
712 VT.getSizeInBits() / 8, 4);
713 return DAG.getMemIntrinsicNode(AMDGPUISD::TBUFFER_STORE_FORMAT, DL,
714 Op->getVTList(), Ops, VT, MMO);
723 /// \brief Helper function for LowerBRCOND
724 static SDNode *findUser(SDValue Value, unsigned Opcode) {
726 SDNode *Parent = Value.getNode();
727 for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
730 if (I.getUse().get() != Value)
733 if (I->getOpcode() == Opcode)
739 /// This transforms the control flow intrinsics to get the branch destination as
740 /// last parameter, also switches branch target with BR if the need arise
741 SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
742 SelectionDAG &DAG) const {
746 SDNode *Intr = BRCOND.getOperand(1).getNode();
747 SDValue Target = BRCOND.getOperand(2);
748 SDNode *BR = nullptr;
750 if (Intr->getOpcode() == ISD::SETCC) {
751 // As long as we negate the condition everything is fine
752 SDNode *SetCC = Intr;
753 assert(SetCC->getConstantOperandVal(1) == 1);
754 assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
756 Intr = SetCC->getOperand(0).getNode();
759 // Get the target from BR if we don't negate the condition
760 BR = findUser(BRCOND, ISD::BR);
761 Target = BR->getOperand(1);
764 assert(Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN);
766 // Build the result and
767 SmallVector<EVT, 4> Res;
768 for (unsigned i = 1, e = Intr->getNumValues(); i != e; ++i)
769 Res.push_back(Intr->getValueType(i));
771 // operands of the new intrinsic call
772 SmallVector<SDValue, 4> Ops;
773 Ops.push_back(BRCOND.getOperand(0));
774 for (unsigned i = 1, e = Intr->getNumOperands(); i != e; ++i)
775 Ops.push_back(Intr->getOperand(i));
776 Ops.push_back(Target);
778 // build the new intrinsic call
779 SDNode *Result = DAG.getNode(
780 Res.size() > 1 ? ISD::INTRINSIC_W_CHAIN : ISD::INTRINSIC_VOID, DL,
781 DAG.getVTList(Res), Ops).getNode();
784 // Give the branch instruction our target
789 DAG.MorphNodeTo(BR, ISD::BR, BR->getVTList(), Ops);
792 SDValue Chain = SDValue(Result, Result->getNumValues() - 1);
794 // Copy the intrinsic results to registers
795 for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
796 SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
800 Chain = DAG.getCopyToReg(
802 CopyToReg->getOperand(1),
803 SDValue(Result, i - 1),
806 DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0));
809 // Remove the old intrinsic from the chain
810 DAG.ReplaceAllUsesOfValueWith(
811 SDValue(Intr, Intr->getNumValues() - 1),
812 Intr->getOperand(0));
817 SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
819 LoadSDNode *Load = cast<LoadSDNode>(Op);
820 SDValue Ret = AMDGPUTargetLowering::LowerLOAD(Op, DAG);
821 SDValue MergedValues[2];
822 MergedValues[1] = Load->getChain();
824 MergedValues[0] = Ret;
825 return DAG.getMergeValues(MergedValues, DL);
828 if (Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
832 EVT MemVT = Load->getMemoryVT();
834 assert(!MemVT.isVector() && "Private loads should be scalarized");
835 assert(!MemVT.isFloatingPoint() && "FP loads should be promoted to int");
837 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
838 DAG.getConstant(2, MVT::i32));
839 Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
840 Load->getChain(), Ptr,
841 DAG.getTargetConstant(0, MVT::i32),
843 if (MemVT.getSizeInBits() == 64) {
844 SDValue IncPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
845 DAG.getConstant(1, MVT::i32));
847 SDValue LoadUpper = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
848 Load->getChain(), IncPtr,
849 DAG.getTargetConstant(0, MVT::i32),
852 Ret = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ret, LoadUpper);
855 MergedValues[0] = Ret;
856 return DAG.getMergeValues(MergedValues, DL);
860 SDValue SITargetLowering::LowerSampleIntrinsic(unsigned Opcode,
862 SelectionDAG &DAG) const {
863 return DAG.getNode(Opcode, SDLoc(Op), Op.getValueType(), Op.getOperand(1),
869 SDValue SITargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
870 if (Op.getValueType() != MVT::i64)
874 SDValue Cond = Op.getOperand(0);
876 SDValue Zero = DAG.getConstant(0, MVT::i32);
877 SDValue One = DAG.getConstant(1, MVT::i32);
879 SDValue LHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(1));
880 SDValue RHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(2));
882 SDValue Lo0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, Zero);
883 SDValue Lo1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, Zero);
885 SDValue Lo = DAG.getSelect(DL, MVT::i32, Cond, Lo0, Lo1);
887 SDValue Hi0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, One);
888 SDValue Hi1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, One);
890 SDValue Hi = DAG.getSelect(DL, MVT::i32, Cond, Hi0, Hi1);
892 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2i32, Lo, Hi);
893 return DAG.getNode(ISD::BITCAST, DL, MVT::i64, Res);
896 SDValue SITargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
897 SDValue LHS = Op.getOperand(0);
898 SDValue RHS = Op.getOperand(1);
899 SDValue True = Op.getOperand(2);
900 SDValue False = Op.getOperand(3);
901 SDValue CC = Op.getOperand(4);
902 EVT VT = Op.getValueType();
905 SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC);
906 return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False);
909 SDValue SITargetLowering::LowerSIGN_EXTEND(SDValue Op,
910 SelectionDAG &DAG) const {
911 EVT VT = Op.getValueType();
914 if (VT != MVT::i64) {
918 SDValue Hi = DAG.getNode(ISD::SRA, DL, MVT::i32, Op.getOperand(0),
919 DAG.getConstant(31, MVT::i32));
921 return DAG.getNode(ISD::BUILD_PAIR, DL, VT, Op.getOperand(0), Hi);
924 SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
926 StoreSDNode *Store = cast<StoreSDNode>(Op);
927 EVT VT = Store->getMemoryVT();
929 SDValue Ret = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
933 if (VT.isVector() && VT.getVectorNumElements() >= 8)
934 return SplitVectorStore(Op, DAG);
937 return DAG.getTruncStore(Store->getChain(), DL,
938 DAG.getSExtOrTrunc(Store->getValue(), DL, MVT::i32),
939 Store->getBasePtr(), MVT::i1, Store->getMemOperand());
941 if (Store->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS)
944 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Store->getBasePtr(),
945 DAG.getConstant(2, MVT::i32));
946 SDValue Chain = Store->getChain();
947 SmallVector<SDValue, 8> Values;
949 if (Store->isTruncatingStore()) {
951 if (Store->getMemoryVT() == MVT::i8) {
953 } else if (Store->getMemoryVT() == MVT::i16) {
956 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
957 Chain, Store->getBasePtr(),
958 DAG.getConstant(0, MVT::i32));
959 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, Store->getBasePtr(),
960 DAG.getConstant(0x3, MVT::i32));
961 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
962 DAG.getConstant(3, MVT::i32));
963 SDValue MaskedValue = DAG.getNode(ISD::AND, DL, MVT::i32, Store->getValue(),
964 DAG.getConstant(Mask, MVT::i32));
965 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
966 MaskedValue, ShiftAmt);
967 SDValue RotrAmt = DAG.getNode(ISD::SUB, DL, MVT::i32,
968 DAG.getConstant(32, MVT::i32), ShiftAmt);
969 SDValue DstMask = DAG.getNode(ISD::ROTR, DL, MVT::i32,
970 DAG.getConstant(Mask, MVT::i32),
972 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
973 Dst = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
975 Values.push_back(Dst);
976 } else if (VT == MVT::i64) {
977 for (unsigned i = 0; i < 2; ++i) {
978 Values.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
979 Store->getValue(), DAG.getConstant(i, MVT::i32)));
981 } else if (VT == MVT::i128) {
982 for (unsigned i = 0; i < 2; ++i) {
983 for (unsigned j = 0; j < 2; ++j) {
984 Values.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
985 DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i64,
986 Store->getValue(), DAG.getConstant(i, MVT::i32)),
987 DAG.getConstant(j, MVT::i32)));
991 Values.push_back(Store->getValue());
994 for (unsigned i = 0; i < Values.size(); ++i) {
995 SDValue PartPtr = DAG.getNode(ISD::ADD, DL, MVT::i32,
996 Ptr, DAG.getConstant(i, MVT::i32));
997 Chain = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
998 Chain, Values[i], PartPtr,
999 DAG.getTargetConstant(0, MVT::i32));
1005 SDValue SITargetLowering::LowerZERO_EXTEND(SDValue Op,
1006 SelectionDAG &DAG) const {
1007 EVT VT = Op.getValueType();
1010 if (VT != MVT::i64) {
1014 SDValue Src = Op.getOperand(0);
1015 if (Src.getValueType() != MVT::i32)
1016 Src = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Src);
1018 SDValue Zero = DAG.getConstant(0, MVT::i32);
1019 return DAG.getNode(ISD::BUILD_PAIR, DL, VT, Src, Zero);
1022 //===----------------------------------------------------------------------===//
1023 // Custom DAG optimizations
1024 //===----------------------------------------------------------------------===//
1026 SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
1027 DAGCombinerInfo &DCI) const {
1028 SelectionDAG &DAG = DCI.DAG;
1030 EVT VT = N->getValueType(0);
1032 switch (N->getOpcode()) {
1033 default: return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1034 case ISD::SELECT_CC: {
1035 ConstantSDNode *True, *False;
1036 // i1 selectcc(l, r, -1, 0, cc) -> i1 setcc(l, r, cc)
1037 if ((True = dyn_cast<ConstantSDNode>(N->getOperand(2)))
1038 && (False = dyn_cast<ConstantSDNode>(N->getOperand(3)))
1039 && True->isAllOnesValue()
1040 && False->isNullValue()
1042 return DAG.getNode(ISD::SETCC, DL, VT, N->getOperand(0),
1043 N->getOperand(1), N->getOperand(4));
1049 SDValue Arg0 = N->getOperand(0);
1050 SDValue Arg1 = N->getOperand(1);
1051 SDValue CC = N->getOperand(2);
1052 ConstantSDNode * C = nullptr;
1053 ISD::CondCode CCOp = dyn_cast<CondCodeSDNode>(CC)->get();
1055 // i1 setcc (sext(i1), 0, setne) -> i1 setcc(i1, 0, setne)
1057 && Arg0.getOpcode() == ISD::SIGN_EXTEND
1058 && Arg0.getOperand(0).getValueType() == MVT::i1
1059 && (C = dyn_cast<ConstantSDNode>(Arg1))
1061 && CCOp == ISD::SETNE) {
1062 return SimplifySetCC(VT, Arg0.getOperand(0),
1063 DAG.getConstant(0, MVT::i1), CCOp, true, DCI, DL);
1071 /// \brief Test if RegClass is one of the VSrc classes
1072 static bool isVSrc(unsigned RegClass) {
1073 return AMDGPU::VSrc_32RegClassID == RegClass ||
1074 AMDGPU::VSrc_64RegClassID == RegClass;
1077 /// \brief Test if RegClass is one of the SSrc classes
1078 static bool isSSrc(unsigned RegClass) {
1079 return AMDGPU::SSrc_32RegClassID == RegClass ||
1080 AMDGPU::SSrc_64RegClassID == RegClass;
1083 /// \brief Analyze the possible immediate value Op
1085 /// Returns -1 if it isn't an immediate, 0 if it's and inline immediate
1086 /// and the immediate value if it's a literal immediate
1087 int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
1094 if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N)) {
1095 if (Node->getZExtValue() >> 32) {
1098 Imm.I = Node->getSExtValue();
1099 } else if (const ConstantFPSDNode *Node = dyn_cast<ConstantFPSDNode>(N)) {
1100 if (N->getValueType(0) != MVT::f32)
1102 Imm.F = Node->getValueAPF().convertToFloat();
1104 return -1; // It isn't an immediate
1106 if ((Imm.I >= -16 && Imm.I <= 64) ||
1107 Imm.F == 0.5f || Imm.F == -0.5f ||
1108 Imm.F == 1.0f || Imm.F == -1.0f ||
1109 Imm.F == 2.0f || Imm.F == -2.0f ||
1110 Imm.F == 4.0f || Imm.F == -4.0f)
1111 return 0; // It's an inline immediate
1113 return Imm.I; // It's a literal immediate
1116 /// \brief Try to fold an immediate directly into an instruction
1117 bool SITargetLowering::foldImm(SDValue &Operand, int32_t &Immediate,
1118 bool &ScalarSlotUsed) const {
1120 MachineSDNode *Mov = dyn_cast<MachineSDNode>(Operand);
1121 const SIInstrInfo *TII =
1122 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1123 if (!Mov || !TII->isMov(Mov->getMachineOpcode()))
1126 const SDValue &Op = Mov->getOperand(0);
1127 int32_t Value = analyzeImmediate(Op.getNode());
1129 // Not an immediate at all
1132 } else if (Value == 0) {
1133 // Inline immediates can always be fold
1137 } else if (Value == Immediate) {
1138 // Already fold literal immediate
1142 } else if (!ScalarSlotUsed && !Immediate) {
1143 // Fold this literal immediate
1144 ScalarSlotUsed = true;
1154 const TargetRegisterClass *SITargetLowering::getRegClassForNode(
1155 SelectionDAG &DAG, const SDValue &Op) const {
1156 const SIInstrInfo *TII =
1157 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1158 const SIRegisterInfo &TRI = TII->getRegisterInfo();
1160 if (!Op->isMachineOpcode()) {
1161 switch(Op->getOpcode()) {
1162 case ISD::CopyFromReg: {
1163 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1164 unsigned Reg = cast<RegisterSDNode>(Op->getOperand(1))->getReg();
1165 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1166 return MRI.getRegClass(Reg);
1168 return TRI.getPhysRegClass(Reg);
1170 default: return nullptr;
1173 const MCInstrDesc &Desc = TII->get(Op->getMachineOpcode());
1174 int OpClassID = Desc.OpInfo[Op.getResNo()].RegClass;
1175 if (OpClassID != -1) {
1176 return TRI.getRegClass(OpClassID);
1178 switch(Op.getMachineOpcode()) {
1179 case AMDGPU::COPY_TO_REGCLASS:
1180 // Operand 1 is the register class id for COPY_TO_REGCLASS instructions.
1181 OpClassID = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1183 // If the COPY_TO_REGCLASS instruction is copying to a VSrc register
1184 // class, then the register class for the value could be either a
1185 // VReg or and SReg. In order to get a more accurate
1186 if (OpClassID == AMDGPU::VSrc_32RegClassID ||
1187 OpClassID == AMDGPU::VSrc_64RegClassID) {
1188 return getRegClassForNode(DAG, Op.getOperand(0));
1190 return TRI.getRegClass(OpClassID);
1191 case AMDGPU::EXTRACT_SUBREG: {
1192 int SubIdx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1193 const TargetRegisterClass *SuperClass =
1194 getRegClassForNode(DAG, Op.getOperand(0));
1195 return TRI.getSubClassWithSubReg(SuperClass, SubIdx);
1197 case AMDGPU::REG_SEQUENCE:
1198 // Operand 0 is the register class id for REG_SEQUENCE instructions.
1199 return TRI.getRegClass(
1200 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue());
1202 return getRegClassFor(Op.getSimpleValueType());
1206 /// \brief Does "Op" fit into register class "RegClass" ?
1207 bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
1208 unsigned RegClass) const {
1209 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
1210 const TargetRegisterClass *RC = getRegClassForNode(DAG, Op);
1214 return TRI->getRegClass(RegClass)->hasSubClassEq(RC);
1217 /// \brief Make sure that we don't exeed the number of allowed scalars
1218 void SITargetLowering::ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
1220 bool &ScalarSlotUsed) const {
1222 // First map the operands register class to a destination class
1223 if (RegClass == AMDGPU::VSrc_32RegClassID)
1224 RegClass = AMDGPU::VReg_32RegClassID;
1225 else if (RegClass == AMDGPU::VSrc_64RegClassID)
1226 RegClass = AMDGPU::VReg_64RegClassID;
1230 // Nothing to do if they fit naturally
1231 if (fitsRegClass(DAG, Operand, RegClass))
1234 // If the scalar slot isn't used yet use it now
1235 if (!ScalarSlotUsed) {
1236 ScalarSlotUsed = true;
1240 // This is a conservative aproach. It is possible that we can't determine the
1241 // correct register class and copy too often, but better safe than sorry.
1242 SDValue RC = DAG.getTargetConstant(RegClass, MVT::i32);
1243 SDNode *Node = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS, SDLoc(),
1244 Operand.getValueType(), Operand, RC);
1245 Operand = SDValue(Node, 0);
1248 /// \returns true if \p Node's operands are different from the SDValue list
1250 static bool isNodeChanged(const SDNode *Node, const std::vector<SDValue> &Ops) {
1251 for (unsigned i = 0, e = Node->getNumOperands(); i < e; ++i) {
1252 if (Ops[i].getNode() != Node->getOperand(i).getNode()) {
1259 /// \brief Try to fold the Nodes operands into the Node
1260 SDNode *SITargetLowering::foldOperands(MachineSDNode *Node,
1261 SelectionDAG &DAG) const {
1263 // Original encoding (either e32 or e64)
1264 int Opcode = Node->getMachineOpcode();
1265 const SIInstrInfo *TII =
1266 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1267 const MCInstrDesc *Desc = &TII->get(Opcode);
1269 unsigned NumDefs = Desc->getNumDefs();
1270 unsigned NumOps = Desc->getNumOperands();
1272 // Commuted opcode if available
1273 int OpcodeRev = Desc->isCommutable() ? TII->commuteOpcode(Opcode) : -1;
1274 const MCInstrDesc *DescRev = OpcodeRev == -1 ? nullptr : &TII->get(OpcodeRev);
1276 assert(!DescRev || DescRev->getNumDefs() == NumDefs);
1277 assert(!DescRev || DescRev->getNumOperands() == NumOps);
1279 // e64 version if available, -1 otherwise
1280 int OpcodeE64 = AMDGPU::getVOPe64(Opcode);
1281 const MCInstrDesc *DescE64 = OpcodeE64 == -1 ? nullptr : &TII->get(OpcodeE64);
1283 assert(!DescE64 || DescE64->getNumDefs() == NumDefs);
1284 assert(!DescE64 || DescE64->getNumOperands() == (NumOps + 4));
1286 int32_t Immediate = Desc->getSize() == 4 ? 0 : -1;
1287 bool HaveVSrc = false, HaveSSrc = false;
1289 // First figure out what we alread have in this instruction
1290 for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs;
1291 i != e && Op < NumOps; ++i, ++Op) {
1293 unsigned RegClass = Desc->OpInfo[Op].RegClass;
1294 if (isVSrc(RegClass))
1296 else if (isSSrc(RegClass))
1301 int32_t Imm = analyzeImmediate(Node->getOperand(i).getNode());
1302 if (Imm != -1 && Imm != 0) {
1303 // Literal immediate
1308 // If we neither have VSrc nor SSrc it makes no sense to continue
1309 if (!HaveVSrc && !HaveSSrc)
1312 // No scalar allowed when we have both VSrc and SSrc
1313 bool ScalarSlotUsed = HaveVSrc && HaveSSrc;
1315 // Second go over the operands and try to fold them
1316 std::vector<SDValue> Ops;
1317 bool Promote2e64 = false;
1318 for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs;
1319 i != e && Op < NumOps; ++i, ++Op) {
1321 const SDValue &Operand = Node->getOperand(i);
1322 Ops.push_back(Operand);
1324 // Already folded immediate ?
1325 if (isa<ConstantSDNode>(Operand.getNode()) ||
1326 isa<ConstantFPSDNode>(Operand.getNode()))
1329 // Is this a VSrc or SSrc operand ?
1330 unsigned RegClass = Desc->OpInfo[Op].RegClass;
1331 if (isVSrc(RegClass) || isSSrc(RegClass)) {
1332 // Try to fold the immediates
1333 if (!foldImm(Ops[i], Immediate, ScalarSlotUsed)) {
1334 // Folding didn't worked, make sure we don't hit the SReg limit
1335 ensureSRegLimit(DAG, Ops[i], RegClass, ScalarSlotUsed);
1340 if (i == 1 && DescRev && fitsRegClass(DAG, Ops[0], RegClass)) {
1342 unsigned OtherRegClass = Desc->OpInfo[NumDefs].RegClass;
1343 assert(isVSrc(OtherRegClass) || isSSrc(OtherRegClass));
1345 // Test if it makes sense to swap operands
1346 if (foldImm(Ops[1], Immediate, ScalarSlotUsed) ||
1347 (!fitsRegClass(DAG, Ops[1], RegClass) &&
1348 fitsRegClass(DAG, Ops[1], OtherRegClass))) {
1350 // Swap commutable operands
1351 std::swap(Ops[0], Ops[1]);
1359 if (DescE64 && !Immediate) {
1361 // Test if it makes sense to switch to e64 encoding
1362 unsigned OtherRegClass = DescE64->OpInfo[Op].RegClass;
1363 if (!isVSrc(OtherRegClass) && !isSSrc(OtherRegClass))
1366 int32_t TmpImm = -1;
1367 if (foldImm(Ops[i], TmpImm, ScalarSlotUsed) ||
1368 (!fitsRegClass(DAG, Ops[i], RegClass) &&
1369 fitsRegClass(DAG, Ops[1], OtherRegClass))) {
1371 // Switch to e64 encoding
1381 // Add the modifier flags while promoting
1382 for (unsigned i = 0; i < 4; ++i)
1383 Ops.push_back(DAG.getTargetConstant(0, MVT::i32));
1386 // Add optional chain and glue
1387 for (unsigned i = NumOps - NumDefs, e = Node->getNumOperands(); i < e; ++i)
1388 Ops.push_back(Node->getOperand(i));
1390 // Nodes that have a glue result are not CSE'd by getMachineNode(), so in
1391 // this case a brand new node is always be created, even if the operands
1392 // are the same as before. So, manually check if anything has been changed.
1393 if (Desc->Opcode == Opcode && !isNodeChanged(Node, Ops)) {
1397 // Create a complete new instruction
1398 return DAG.getMachineNode(Desc->Opcode, SDLoc(Node), Node->getVTList(), Ops);
1401 /// \brief Helper function for adjustWritemask
1402 static unsigned SubIdx2Lane(unsigned Idx) {
1405 case AMDGPU::sub0: return 0;
1406 case AMDGPU::sub1: return 1;
1407 case AMDGPU::sub2: return 2;
1408 case AMDGPU::sub3: return 3;
1412 /// \brief Adjust the writemask of MIMG instructions
1413 void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
1414 SelectionDAG &DAG) const {
1415 SDNode *Users[4] = { };
1417 unsigned OldDmask = Node->getConstantOperandVal(0);
1418 unsigned NewDmask = 0;
1420 // Try to figure out the used register components
1421 for (SDNode::use_iterator I = Node->use_begin(), E = Node->use_end();
1424 // Abort if we can't understand the usage
1425 if (!I->isMachineOpcode() ||
1426 I->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG)
1429 // Lane means which subreg of %VGPRa_VGPRb_VGPRc_VGPRd is used.
1430 // Note that subregs are packed, i.e. Lane==0 is the first bit set
1431 // in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit
1433 Lane = SubIdx2Lane(I->getConstantOperandVal(1));
1435 // Set which texture component corresponds to the lane.
1437 for (unsigned i = 0, Dmask = OldDmask; i <= Lane; i++) {
1439 Comp = countTrailingZeros(Dmask);
1440 Dmask &= ~(1 << Comp);
1443 // Abort if we have more than one user per component
1448 NewDmask |= 1 << Comp;
1451 // Abort if there's no change
1452 if (NewDmask == OldDmask)
1455 // Adjust the writemask in the node
1456 std::vector<SDValue> Ops;
1457 Ops.push_back(DAG.getTargetConstant(NewDmask, MVT::i32));
1458 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
1459 Ops.push_back(Node->getOperand(i));
1460 Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops);
1462 // If we only got one lane, replace it with a copy
1463 // (if NewDmask has only one bit set...)
1464 if (NewDmask && (NewDmask & (NewDmask-1)) == 0) {
1465 SDValue RC = DAG.getTargetConstant(AMDGPU::VReg_32RegClassID, MVT::i32);
1466 SDNode *Copy = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
1467 SDLoc(), Users[Lane]->getValueType(0),
1468 SDValue(Node, 0), RC);
1469 DAG.ReplaceAllUsesWith(Users[Lane], Copy);
1473 // Update the users of the node with the new indices
1474 for (unsigned i = 0, Idx = AMDGPU::sub0; i < 4; ++i) {
1476 SDNode *User = Users[i];
1480 SDValue Op = DAG.getTargetConstant(Idx, MVT::i32);
1481 DAG.UpdateNodeOperands(User, User->getOperand(0), Op);
1485 case AMDGPU::sub0: Idx = AMDGPU::sub1; break;
1486 case AMDGPU::sub1: Idx = AMDGPU::sub2; break;
1487 case AMDGPU::sub2: Idx = AMDGPU::sub3; break;
1492 /// \brief Fold the instructions after slecting them
1493 SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
1494 SelectionDAG &DAG) const {
1495 const SIInstrInfo *TII =
1496 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1497 Node = AdjustRegClass(Node, DAG);
1499 if (TII->isMIMG(Node->getMachineOpcode()))
1500 adjustWritemask(Node, DAG);
1502 return foldOperands(Node, DAG);
1505 /// \brief Assign the register class depending on the number of
1506 /// bits set in the writemask
1507 void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
1508 SDNode *Node) const {
1509 const SIInstrInfo *TII =
1510 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1511 if (!TII->isMIMG(MI->getOpcode()))
1514 unsigned VReg = MI->getOperand(0).getReg();
1515 unsigned Writemask = MI->getOperand(1).getImm();
1516 unsigned BitsSet = 0;
1517 for (unsigned i = 0; i < 4; ++i)
1518 BitsSet += Writemask & (1 << i) ? 1 : 0;
1520 const TargetRegisterClass *RC;
1523 case 1: RC = &AMDGPU::VReg_32RegClass; break;
1524 case 2: RC = &AMDGPU::VReg_64RegClass; break;
1525 case 3: RC = &AMDGPU::VReg_96RegClass; break;
1528 unsigned NewOpcode = TII->getMaskedMIMGOp(MI->getOpcode(), BitsSet);
1529 MI->setDesc(TII->get(NewOpcode));
1530 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1531 MRI.setRegClass(VReg, RC);
1534 MachineSDNode *SITargetLowering::AdjustRegClass(MachineSDNode *N,
1535 SelectionDAG &DAG) const {
1538 unsigned NewOpcode = N->getMachineOpcode();
1540 switch (N->getMachineOpcode()) {
1542 case AMDGPU::S_LOAD_DWORD_IMM:
1543 NewOpcode = AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
1545 case AMDGPU::S_LOAD_DWORDX2_SGPR:
1546 if (NewOpcode == N->getMachineOpcode()) {
1547 NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
1550 case AMDGPU::S_LOAD_DWORDX4_IMM:
1551 case AMDGPU::S_LOAD_DWORDX4_SGPR: {
1552 if (NewOpcode == N->getMachineOpcode()) {
1553 NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
1555 if (fitsRegClass(DAG, N->getOperand(0), AMDGPU::SReg_64RegClassID)) {
1558 ConstantSDNode *Offset = cast<ConstantSDNode>(N->getOperand(1));
1560 SDValue(DAG.getMachineNode(AMDGPU::SI_ADDR64_RSRC, DL, MVT::i128,
1561 DAG.getConstant(0, MVT::i64)), 0),
1563 DAG.getConstant(Offset->getSExtValue() << 2, MVT::i32)
1565 return DAG.getMachineNode(NewOpcode, DL, N->getVTList(), Ops);
1570 SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
1571 const TargetRegisterClass *RC,
1572 unsigned Reg, EVT VT) const {
1573 SDValue VReg = AMDGPUTargetLowering::CreateLiveInRegister(DAG, RC, Reg, VT);
1575 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(DAG.getEntryNode()),
1576 cast<RegisterSDNode>(VReg)->getReg(), VT);