drm/rockchip: vop: rk3328: fix overlay abnormal
authorMark Yao <mark.yao@rock-chips.com>
Sat, 1 Apr 2017 09:14:16 +0000 (17:14 +0800)
committerHuang, Tao <huangtao@rock-chips.com>
Sat, 1 Apr 2017 10:14:13 +0000 (18:14 +0800)
It's a hardware bug, all window's overlay channel reset
value is same, hardware overlay would be die.

so we must initial difference id for each overlay channel.

Change-Id: Ic0b744b2789a5aff2f6605199e7670cac1ea7214
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
drivers/gpu/drm/rockchip/rockchip_vop_reg.c
drivers/gpu/drm/rockchip/rockchip_vop_reg.h

index 8cb4558..e10d272 100644 (file)
@@ -825,7 +825,9 @@ static void vop_initial(struct drm_crtc *crtc)
         */
        for (i = 0; i < vop->num_wins; i++) {
                struct vop_win *win = &vop->win[i];
+               int channel = i * 2 + 1;
 
+               VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
                if (win->phy->scl && win->phy->scl->ext) {
                        VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
                        VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
index 0710cda..7e45492 100644 (file)
@@ -235,6 +235,7 @@ struct vop_win_phy {
        struct vop_reg yrgb_vir;
        struct vop_reg uv_vir;
 
+       struct vop_reg channel;
        struct vop_reg dst_alpha_ctl;
        struct vop_reg src_alpha_ctl;
        struct vop_reg alpha_mode;
index 9b35835..34a778f 100644 (file)
@@ -120,6 +120,7 @@ static const struct vop_win_phy rk3288_win01_data = {
        .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
        .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xffffffff, 0),
        .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xffffffff, 0),
+       .channel = VOP_REG_VER(RK3288_WIN0_CTRL2, 0xff, 0, 3, 8, 8),
 };
 
 static const struct vop_win_phy rk3288_win23_data = {
index ad0bbd9..56a723a 100644 (file)
@@ -41,6 +41,7 @@
 #define RK3288_WIN0_SRC_ALPHA_CTRL             0x0060
 #define RK3288_WIN0_DST_ALPHA_CTRL             0x0064
 #define RK3288_WIN0_FADING_CTRL                        0x0068
+#define RK3288_WIN0_CTRL2                      0x006c
 
 /* win1 register */
 #define RK3288_WIN1_CTRL0                      0x0070