drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21
  22 #include <linux/iopoll.h>
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/clk.h>
  27 #include <linux/of.h>
  28 #include <linux/of_device.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/component.h>
  31
  32 #include <linux/reset.h>
  33 #include <linux/delay.h>
  34 #include <linux/sort.h>
  35 #include <uapi/drm/rockchip_drm.h>
  36
  37 #include "rockchip_drm_drv.h"
  38 #include "rockchip_drm_gem.h"
  39 #include "rockchip_drm_fb.h"
  40 #include "rockchip_drm_vop.h"
  41
  42 #define VOP_REG_SUPPORT(vop, reg) \
  43                 (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
  44                 reg.begin_minor <= VOP_MINOR(vop->data->version) && \
  45                 reg.end_minor >= VOP_MINOR(vop->data->version) && \
  46                 reg.mask))
  47
  48 #define VOP_WIN_SUPPORT(vop, win, name) \
  49                 VOP_REG_SUPPORT(vop, win->phy->name)
  50
  51 #define VOP_CTRL_SUPPORT(vop, name) \
  52                 VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
  53
  54 #define VOP_INTR_SUPPORT(vop, name) \
  55                 VOP_REG_SUPPORT(vop, vop->data->intr->name)
  56
  57 #define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
  58                 vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
  59
  60 #define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
  61         do { \
  62                 if (VOP_REG_SUPPORT(vop, reg)) \
  63                         __REG_SET(vop, off + reg.offset, mask, reg.shift, \
  64                                   v, reg.write_mask, relaxed); \
  65                 else \
  66                         dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
  67         } while(0)
  68
  69 #define REG_SET(x, name, off, reg, v, relaxed) \
  70                 _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
  71 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
  72                 _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
  73
  74 #define VOP_WIN_SET(x, win, name, v) \
  75                 REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
  76 #define VOP_WIN_SET_EXT(x, win, ext, name, v) \
  77                 REG_SET(x, name, 0, win->ext->name, v, true)
  78 #define VOP_SCL_SET(x, win, name, v) \
  79                 REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
  80 #define VOP_SCL_SET_EXT(x, win, name, v) \
  81                 REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
  82
  83 #define VOP_CTRL_SET(x, name, v) \
  84                 REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
  85
  86 #define VOP_INTR_GET(vop, name) \
  87                 vop_read_reg(vop, 0, &vop->data->ctrl->name)
  88
  89 #define VOP_INTR_SET(vop, name, v) \
  90                 REG_SET(vop, name, 0, vop->data->intr->name, \
  91                         v, false)
  92 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
  93                 REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
  94                              mask, v, false)
  95
  96 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
  97         do { \
  98                 int i, reg = 0, mask = 0; \
  99                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
 100                         if (vop->data->intr->intrs[i] & type) { \
 101                                 reg |= (v) << i; \
 102                                 mask |= 1 << i; \
 103                         } \
 104                 } \
 105                 VOP_INTR_SET_MASK(vop, name, mask, reg); \
 106         } while (0)
 107 #define VOP_INTR_GET_TYPE(vop, name, type) \
 108                 vop_get_intr_type(vop, &vop->data->intr->name, type)
 109
 110 #define VOP_CTRL_GET(x, name) \
 111                 vop_read_reg(x, 0, &vop->data->ctrl->name)
 112
 113 #define VOP_WIN_GET(x, win, name) \
 114                 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
 115
 116 #define VOP_WIN_NAME(win, name) \
 117                 (vop_get_win_phy(win, &win->phy->name)->name)
 118
 119 #define VOP_WIN_GET_YRGBADDR(vop, win) \
 120                 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
 121
 122 #define to_vop(x) container_of(x, struct vop, crtc)
 123 #define to_vop_win(x) container_of(x, struct vop_win, base)
 124 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
 125
 126 struct vop_zpos {
 127         int win_id;
 128         int zpos;
 129 };
 130
 131 struct vop_plane_state {
 132         struct drm_plane_state base;
 133         int format;
 134         int zpos;
 135         struct drm_rect src;
 136         struct drm_rect dest;
 137         dma_addr_t yrgb_mst;
 138         dma_addr_t uv_mst;
 139         const uint32_t *y2r_table;
 140         const uint32_t *r2r_table;
 141         const uint32_t *r2y_table;
 142         bool enable;
 143 };
 144
 145 struct vop_win {
 146         struct vop_win *parent;
 147         struct drm_plane base;
 148
 149         int win_id;
 150         int area_id;
 151         uint32_t offset;
 152         enum drm_plane_type type;
 153         const struct vop_win_phy *phy;
 154         const struct vop_csc *csc;
 155         const uint32_t *data_formats;
 156         uint32_t nformats;
 157         struct vop *vop;
 158
 159         struct drm_property *rotation_prop;
 160         struct vop_plane_state state;
 161 };
 162
 163 struct vop {
 164         struct drm_crtc crtc;
 165         struct device *dev;
 166         struct drm_device *drm_dev;
 167         struct drm_property *plane_zpos_prop;
 168         struct drm_property *plane_feature_prop;
 169         struct drm_property *feature_prop;
 170         bool is_iommu_enabled;
 171         bool is_iommu_needed;
 172         bool is_enabled;
 173
 174         /* mutex vsync_ work */
 175         struct mutex vsync_mutex;
 176         bool vsync_work_pending;
 177         bool loader_protect;
 178         struct completion dsp_hold_completion;
 179         struct completion wait_update_complete;
 180         struct drm_pending_vblank_event *event;
 181
 182         struct completion line_flag_completion;
 183
 184         const struct vop_data *data;
 185         int num_wins;
 186
 187         uint32_t *regsbak;
 188         void __iomem *regs;
 189
 190         /* physical map length of vop register */
 191         uint32_t len;
 192
 193         /* one time only one process allowed to config the register */
 194         spinlock_t reg_lock;
 195         /* lock vop irq reg */
 196         spinlock_t irq_lock;
 197
 198         unsigned int irq;
 199
 200         /* vop AHP clk */
 201         struct clk *hclk;
 202         /* vop dclk */
 203         struct clk *dclk;
 204         /* vop share memory frequency */
 205         struct clk *aclk;
 206
 207         /* vop dclk reset */
 208         struct reset_control *dclk_rst;
 209
 210         struct vop_win win[];
 211 };
 212
 213 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 214 {
 215         writel(v, vop->regs + offset);
 216         vop->regsbak[offset >> 2] = v;
 217 }
 218
 219 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 220 {
 221         return readl(vop->regs + offset);
 222 }
 223
 224 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 225                                     const struct vop_reg *reg)
 226 {
 227         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 228 }
 229
 230 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 231                                   uint32_t mask, uint32_t shift, uint32_t v,
 232                                   bool write_mask, bool relaxed)
 233 {
 234         if (!mask)
 235                 return;
 236
 237         if (write_mask) {
 238                 v = ((v & mask) << shift) | (mask << (shift + 16));
 239         } else {
 240                 uint32_t cached_val = vop->regsbak[offset >> 2];
 241
 242                 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
 243                 vop->regsbak[offset >> 2] = v;
 244         }
 245
 246         if (relaxed)
 247                 writel_relaxed(v, vop->regs + offset);
 248         else
 249                 writel(v, vop->regs + offset);
 250 }
 251
 252 static inline const struct vop_win_phy *
 253 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
 254 {
 255         if (!reg->mask && win->parent)
 256                 return win->parent->phy;
 257
 258         return win->phy;
 259 }
 260
 261 static inline uint32_t vop_get_intr_type(struct vop *vop,
 262                                          const struct vop_reg *reg, int type)
 263 {
 264         uint32_t i, ret = 0;
 265         uint32_t regs = vop_read_reg(vop, 0, reg);
 266
 267         for (i = 0; i < vop->data->intr->nintrs; i++) {
 268                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 269                         ret |= vop->data->intr->intrs[i];
 270         }
 271
 272         return ret;
 273 }
 274
 275 static void vop_load_csc_table(struct vop *vop, u32 offset, const u32 *table)
 276 {
 277         int i;
 278
 279         if (!table)
 280                 return;
 281
 282         for (i = 0; i < 8; i++)
 283                 vop_writel(vop, offset + i * 4, table[i]);
 284 }
 285
 286 static inline void vop_cfg_done(struct vop *vop)
 287 {
 288         VOP_CTRL_SET(vop, cfg_done, 1);
 289 }
 290
 291 static bool vop_is_allwin_disabled(struct vop *vop)
 292 {
 293         int i;
 294
 295         for (i = 0; i < vop->num_wins; i++) {
 296                 struct vop_win *win = &vop->win[i];
 297
 298                 if (VOP_WIN_GET(vop, win, enable) != 0)
 299                         return false;
 300         }
 301
 302         return true;
 303 }
 304
 305 static bool vop_is_cfg_done_complete(struct vop *vop)
 306 {
 307         return VOP_CTRL_GET(vop, cfg_done) ? false : true;
 308 }
 309
 310 static bool vop_fs_irq_is_active(struct vop *vop)
 311 {
 312         return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
 313 }
 314
 315 static bool vop_line_flag_is_active(struct vop *vop)
 316 {
 317         return VOP_INTR_GET_TYPE(vop, status, LINE_FLAG_INTR);
 318 }
 319
 320 static bool has_rb_swapped(uint32_t format)
 321 {
 322         switch (format) {
 323         case DRM_FORMAT_XBGR8888:
 324         case DRM_FORMAT_ABGR8888:
 325         case DRM_FORMAT_BGR888:
 326         case DRM_FORMAT_BGR565:
 327                 return true;
 328         default:
 329                 return false;
 330         }
 331 }
 332
 333 static enum vop_data_format vop_convert_format(uint32_t format)
 334 {
 335         switch (format) {
 336         case DRM_FORMAT_XRGB8888:
 337         case DRM_FORMAT_ARGB8888:
 338         case DRM_FORMAT_XBGR8888:
 339         case DRM_FORMAT_ABGR8888:
 340                 return VOP_FMT_ARGB8888;
 341         case DRM_FORMAT_RGB888:
 342         case DRM_FORMAT_BGR888:
 343                 return VOP_FMT_RGB888;
 344         case DRM_FORMAT_RGB565:
 345         case DRM_FORMAT_BGR565:
 346                 return VOP_FMT_RGB565;
 347         case DRM_FORMAT_NV12:
 348         case DRM_FORMAT_NV12_10:
 349                 return VOP_FMT_YUV420SP;
 350         case DRM_FORMAT_NV16:
 351         case DRM_FORMAT_NV16_10:
 352                 return VOP_FMT_YUV422SP;
 353         case DRM_FORMAT_NV24:
 354         case DRM_FORMAT_NV24_10:
 355                 return VOP_FMT_YUV444SP;
 356         default:
 357                 DRM_ERROR("unsupport format[%08x]\n", format);
 358                 return -EINVAL;
 359         }
 360 }
 361
 362 static bool is_yuv_output(uint32_t bus_format)
 363 {
 364         switch (bus_format) {
 365         case MEDIA_BUS_FMT_YUV8_1X24:
 366         case MEDIA_BUS_FMT_YUV10_1X30:
 367                 return true;
 368         default:
 369                 return false;
 370         }
 371 }
 372
 373 static bool is_yuv_support(uint32_t format)
 374 {
 375         switch (format) {
 376         case DRM_FORMAT_NV12:
 377         case DRM_FORMAT_NV12_10:
 378         case DRM_FORMAT_NV16:
 379         case DRM_FORMAT_NV16_10:
 380         case DRM_FORMAT_NV24:
 381         case DRM_FORMAT_NV24_10:
 382                 return true;
 383         default:
 384                 return false;
 385         }
 386 }
 387
 388 static bool is_yuv_10bit(uint32_t format)
 389 {
 390         switch (format) {
 391         case DRM_FORMAT_NV12_10:
 392         case DRM_FORMAT_NV16_10:
 393         case DRM_FORMAT_NV24_10:
 394                 return true;
 395         default:
 396                 return false;
 397         }
 398 }
 399
 400 static bool is_alpha_support(uint32_t format)
 401 {
 402         switch (format) {
 403         case DRM_FORMAT_ARGB8888:
 404         case DRM_FORMAT_ABGR8888:
 405                 return true;
 406         default:
 407                 return false;
 408         }
 409 }
 410
 411 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 412                                   uint32_t dst, bool is_horizontal,
 413                                   int vsu_mode, int *vskiplines)
 414 {
 415         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 416
 417         if (is_horizontal) {
 418                 if (mode == SCALE_UP)
 419                         val = GET_SCL_FT_BIC(src, dst);
 420                 else if (mode == SCALE_DOWN)
 421                         val = GET_SCL_FT_BILI_DN(src, dst);
 422         } else {
 423                 if (mode == SCALE_UP) {
 424                         if (vsu_mode == SCALE_UP_BIL)
 425                                 val = GET_SCL_FT_BILI_UP(src, dst);
 426                         else
 427                                 val = GET_SCL_FT_BIC(src, dst);
 428                 } else if (mode == SCALE_DOWN) {
 429                         if (vskiplines) {
 430                                 *vskiplines = scl_get_vskiplines(src, dst);
 431                                 val = scl_get_bili_dn_vskip(src, dst,
 432                                                             *vskiplines);
 433                         } else {
 434                                 val = GET_SCL_FT_BILI_DN(src, dst);
 435                         }
 436                 }
 437         }
 438
 439         return val;
 440 }
 441
 442 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
 443                                 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 444                                 uint32_t dst_h, uint32_t pixel_format)
 445 {
 446         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 447         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 448         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 449         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 450         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 451         bool is_yuv = is_yuv_support(pixel_format);
 452         uint16_t cbcr_src_w = src_w / hsub;
 453         uint16_t cbcr_src_h = src_h / vsub;
 454         uint16_t vsu_mode;
 455         uint16_t lb_mode;
 456         uint32_t val;
 457         int vskiplines = 0;
 458
 459         if (!win->phy->scl)
 460                 return;
 461
 462         if (!win->phy->scl->ext) {
 463                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 464                             scl_cal_scale2(src_w, dst_w));
 465                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 466                             scl_cal_scale2(src_h, dst_h));
 467                 if (is_yuv) {
 468                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 469                                     scl_cal_scale2(cbcr_src_w, dst_w));
 470                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 471                                     scl_cal_scale2(cbcr_src_h, dst_h));
 472                 }
 473                 return;
 474         }
 475
 476         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 477         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 478
 479         if (is_yuv) {
 480                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 481                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 482                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 483                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 484                 else
 485                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 486         } else {
 487                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 488                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 489                 else
 490                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 491         }
 492
 493         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 494         if (lb_mode == LB_RGB_3840X2) {
 495                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 496                         DRM_ERROR("ERROR : not allow yrgb ver scale\n");
 497                         return;
 498                 }
 499                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 500                         DRM_ERROR("ERROR : not allow cbcr ver scale\n");
 501                         return;
 502                 }
 503                 vsu_mode = SCALE_UP_BIL;
 504         } else if (lb_mode == LB_RGB_2560X4) {
 505                 vsu_mode = SCALE_UP_BIL;
 506         } else {
 507                 vsu_mode = SCALE_UP_BIC;
 508         }
 509
 510         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 511                                 true, 0, NULL);
 512         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 513         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 514                                 false, vsu_mode, &vskiplines);
 515         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 516
 517         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 518         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 519
 520         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 521         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 522         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 523         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 524         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 525         if (is_yuv) {
 526                 vskiplines = 0;
 527
 528                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 529                                         dst_w, true, 0, NULL);
 530                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 531                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 532                                         dst_h, false, vsu_mode, &vskiplines);
 533                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 534
 535                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 536                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 537                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 538                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 539                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 540                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 541                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 542         }
 543 }
 544
 545 /*
 546  * rk3399 colorspace path:
 547  *      Input        Win csc                     Output
 548  * 1. YUV(2020)  --> Y2R->2020To709->R2Y   --> YUV_OUTPUT(601/709)
 549  *    RGB        --> R2Y                  __/
 550  *
 551  * 2. YUV(2020)  --> bypasss               --> YUV_OUTPUT(2020)
 552  *    RGB        --> 709To2020->R2Y       __/
 553  *
 554  * 3. YUV(2020)  --> Y2R->2020To709        --> RGB_OUTPUT(709)
 555  *    RGB        --> R2Y                  __/
 556  *
 557  * 4. YUV(601/709)-> Y2R->709To2020->R2Y   --> YUV_OUTPUT(2020)
 558  *    RGB        --> 709To2020->R2Y       __/
 559  *
 560  * 5. YUV(601/709)-> bypass                --> YUV_OUTPUT(709)
 561  *    RGB        --> R2Y                  __/
 562  *
 563  * 6. YUV(601/709)-> bypass                --> YUV_OUTPUT(601)
 564  *    RGB        --> R2Y(601)             __/
 565  *
 566  * 7. YUV        --> Y2R(709)              --> RGB_OUTPUT(709)
 567  *    RGB        --> bypass               __/
 568  *
 569  * 8. RGB        --> 709To2020->R2Y        --> YUV_OUTPUT(2020)
 570  *
 571  * 9. RGB        --> R2Y(709)              --> YUV_OUTPUT(709)
 572  *
 573  * 10. RGB       --> R2Y(601)              --> YUV_OUTPUT(601)
 574  *
 575  * 11. RGB       --> bypass                --> RGB_OUTPUT(709)
 576  */
 577 static int vop_csc_setup(const struct vop_csc_table *csc_table,
 578                          bool is_input_yuv, bool is_output_yuv,
 579                          int input_csc, int output_csc,
 580                          const uint32_t **y2r_table,
 581                          const uint32_t **r2r_table,
 582                          const uint32_t **r2y_table)
 583 {
 584         *y2r_table = NULL;
 585         *r2r_table = NULL;
 586         *r2y_table = NULL;
 587
 588         if (is_output_yuv) {
 589                 if (output_csc == CSC_BT2020) {
 590                         if (is_input_yuv) {
 591                                 if (input_csc == CSC_BT2020)
 592                                         return 0;
 593                                 *y2r_table = csc_table->y2r_bt709;
 594                         }
 595                         if (input_csc != CSC_BT2020)
 596                                 *r2r_table = csc_table->r2r_bt709_to_bt2020;
 597                         *r2y_table = csc_table->r2y_bt2020;
 598                 } else {
 599                         if (is_input_yuv && input_csc == CSC_BT2020)
 600                                 *y2r_table = csc_table->y2r_bt2020;
 601                         if (input_csc == CSC_BT2020)
 602                                 *r2r_table = csc_table->r2r_bt2020_to_bt709;
 603                         if (!is_input_yuv || *y2r_table) {
 604                                 if (output_csc == CSC_BT709)
 605                                         *r2y_table = csc_table->r2y_bt709;
 606                                 else
 607                                         *r2y_table = csc_table->r2y_bt601;
 608                         }
 609                 }
 610         } else {
 611                 if (!is_input_yuv)
 612                         return 0;
 613
 614                 /*
 615                  * is possible use bt2020 on rgb mode?
 616                  */
 617                 if (WARN_ON(output_csc == CSC_BT2020))
 618                         return -EINVAL;
 619
 620                 if (input_csc == CSC_BT2020)
 621                         *y2r_table = csc_table->y2r_bt2020;
 622                 else if (input_csc == CSC_BT709)
 623                         *y2r_table = csc_table->y2r_bt709;
 624                 else
 625                         *y2r_table = csc_table->y2r_bt601;
 626
 627                 if (input_csc == CSC_BT2020)
 628                         /*
 629                          * We don't have bt601 to bt709 table, force use bt709.
 630                          */
 631                         *r2r_table = csc_table->r2r_bt2020_to_bt709;
 632         }
 633
 634         return 0;
 635 }
 636
 637 static int vop_csc_atomic_check(struct drm_crtc *crtc,
 638                                 struct drm_crtc_state *crtc_state)
 639 {
 640         struct vop *vop = to_vop(crtc);
 641         struct drm_atomic_state *state = crtc_state->state;
 642         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
 643         const struct vop_csc_table *csc_table = vop->data->csc_table;
 644         struct drm_plane_state *pstate;
 645         struct drm_plane *plane;
 646         bool is_input_yuv, is_output_yuv;
 647         int ret;
 648
 649         if (!csc_table)
 650                 return 0;
 651
 652         is_output_yuv = is_yuv_output(s->bus_format);
 653
 654         drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
 655                 struct vop_plane_state *vop_plane_state;
 656
 657                 pstate = drm_atomic_get_plane_state(state, plane);
 658                 if (IS_ERR(pstate))
 659                         return PTR_ERR(pstate);
 660                 vop_plane_state = to_vop_plane_state(pstate);
 661
 662                 if (!pstate->fb)
 663                         continue;
 664                 is_input_yuv = is_yuv_support(pstate->fb->pixel_format);
 665
 666                 /*
 667                  * TODO: force set input and output csc mode.
 668                  */
 669                 ret = vop_csc_setup(csc_table, is_input_yuv, is_output_yuv,
 670                                     CSC_BT709, CSC_BT709,
 671                                     &vop_plane_state->y2r_table,
 672                                     &vop_plane_state->r2r_table,
 673                                     &vop_plane_state->r2y_table);
 674                 if (ret)
 675                         return ret;
 676         }
 677
 678         return 0;
 679 }
 680
 681 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 682 {
 683         unsigned long flags;
 684
 685         spin_lock_irqsave(&vop->irq_lock, flags);
 686
 687         VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
 688         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 689
 690         spin_unlock_irqrestore(&vop->irq_lock, flags);
 691 }
 692
 693 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 694 {
 695         unsigned long flags;
 696
 697         spin_lock_irqsave(&vop->irq_lock, flags);
 698
 699         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 700
 701         spin_unlock_irqrestore(&vop->irq_lock, flags);
 702 }
 703
 704 /*
 705  * (1) each frame starts at the start of the Vsync pulse which is signaled by
 706  *     the "FRAME_SYNC" interrupt.
 707  * (2) the active data region of each frame ends at dsp_vact_end
 708  * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
 709  *      to get "LINE_FLAG" interrupt at the end of the active on screen data.
 710  *
 711  * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
 712  * Interrupts
 713  * LINE_FLAG -------------------------------+
 714  * FRAME_SYNC ----+                         |
 715  *                |                         |
 716  *                v                         v
 717  *                | Vsync | Vbp |  Vactive  | Vfp |
 718  *                        ^     ^           ^     ^
 719  *                        |     |           |     |
 720  *                        |     |           |     |
 721  * dsp_vs_end ------------+     |           |     |   VOP_DSP_VTOTAL_VS_END
 722  * dsp_vact_start --------------+           |     |   VOP_DSP_VACT_ST_END
 723  * dsp_vact_end ----------------------------+     |   VOP_DSP_VACT_ST_END
 724  * dsp_total -------------------------------------+   VOP_DSP_VTOTAL_VS_END
 725  */
 726 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
 727 {
 728         uint32_t line_flag_irq;
 729         unsigned long flags;
 730
 731         spin_lock_irqsave(&vop->irq_lock, flags);
 732
 733         line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
 734
 735         spin_unlock_irqrestore(&vop->irq_lock, flags);
 736
 737         return !!line_flag_irq;
 738 }
 739
 740 static void vop_line_flag_irq_enable(struct vop *vop, int line_num)
 741 {
 742         unsigned long flags;
 743
 744         if (WARN_ON(!vop->is_enabled))
 745                 return;
 746
 747         spin_lock_irqsave(&vop->irq_lock, flags);
 748
 749         VOP_INTR_SET(vop, line_flag_num[0], line_num);
 750         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
 751         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
 752
 753         spin_unlock_irqrestore(&vop->irq_lock, flags);
 754 }
 755
 756 static void vop_line_flag_irq_disable(struct vop *vop)
 757 {
 758         unsigned long flags;
 759
 760         if (WARN_ON(!vop->is_enabled))
 761                 return;
 762
 763         spin_lock_irqsave(&vop->irq_lock, flags);
 764
 765         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
 766
 767         spin_unlock_irqrestore(&vop->irq_lock, flags);
 768 }
 769
 770 static void vop_power_enable(struct drm_crtc *crtc)
 771 {
 772         struct vop *vop = to_vop(crtc);
 773         int ret;
 774
 775         ret = clk_prepare_enable(vop->hclk);
 776         if (ret < 0) {
 777                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 778                 return;
 779         }
 780
 781         ret = clk_prepare_enable(vop->dclk);
 782         if (ret < 0) {
 783                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 784                 goto err_disable_hclk;
 785         }
 786
 787         ret = clk_prepare_enable(vop->aclk);
 788         if (ret < 0) {
 789                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 790                 goto err_disable_dclk;
 791         }
 792
 793         ret = pm_runtime_get_sync(vop->dev);
 794         if (ret < 0) {
 795                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 796                 return;
 797         }
 798
 799         memcpy(vop->regsbak, vop->regs, vop->len);
 800
 801         vop->is_enabled = true;
 802
 803         return;
 804
 805 err_disable_dclk:
 806         clk_disable_unprepare(vop->dclk);
 807 err_disable_hclk:
 808         clk_disable_unprepare(vop->hclk);
 809 }
 810
 811 static void vop_initial(struct drm_crtc *crtc)
 812 {
 813         struct vop *vop = to_vop(crtc);
 814         int i;
 815
 816         vop_power_enable(crtc);
 817
 818         VOP_CTRL_SET(vop, global_regdone_en, 1);
 819         VOP_CTRL_SET(vop, dsp_blank, 0);
 820
 821         /*
 822          * We need to make sure that all windows are disabled before resume
 823          * the crtc. Otherwise we might try to scan from a destroyed
 824          * buffer later.
 825          */
 826         for (i = 0; i < vop->num_wins; i++) {
 827                 struct vop_win *win = &vop->win[i];
 828
 829                 if (win->phy->scl && win->phy->scl->ext) {
 830                         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
 831                         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
 832                         VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
 833                         VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
 834                 }
 835                 VOP_WIN_SET(vop, win, enable, 0);
 836                 VOP_WIN_SET(vop, win, gate, 1);
 837         }
 838         VOP_CTRL_SET(vop, afbdc_en, 0);
 839 }
 840
 841 static void vop_crtc_disable(struct drm_crtc *crtc)
 842 {
 843         struct vop *vop = to_vop(crtc);
 844
 845         drm_crtc_vblank_off(crtc);
 846
 847         /*
 848          * Vop standby will take effect at end of current frame,
 849          * if dsp hold valid irq happen, it means standby complete.
 850          *
 851          * we must wait standby complete when we want to disable aclk,
 852          * if not, memory bus maybe dead.
 853          */
 854         reinit_completion(&vop->dsp_hold_completion);
 855         vop_dsp_hold_valid_irq_enable(vop);
 856
 857         spin_lock(&vop->reg_lock);
 858
 859         VOP_CTRL_SET(vop, standby, 1);
 860
 861         spin_unlock(&vop->reg_lock);
 862
 863         WARN_ON(!wait_for_completion_timeout(&vop->dsp_hold_completion,
 864                                              msecs_to_jiffies(50)));
 865
 866         vop_dsp_hold_valid_irq_disable(vop);
 867
 868         disable_irq(vop->irq);
 869
 870         vop->is_enabled = false;
 871         if (vop->is_iommu_enabled) {
 872                 /*
 873                  * vop standby complete, so iommu detach is safe.
 874                  */
 875                 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 876                 vop->is_iommu_enabled = false;
 877         }
 878
 879         pm_runtime_put(vop->dev);
 880         clk_disable_unprepare(vop->dclk);
 881         clk_disable_unprepare(vop->aclk);
 882         clk_disable_unprepare(vop->hclk);
 883 }
 884
 885 static void vop_plane_destroy(struct drm_plane *plane)
 886 {
 887         drm_plane_cleanup(plane);
 888 }
 889
 890 static int vop_plane_prepare_fb(struct drm_plane *plane,
 891                                 const struct drm_plane_state *new_state)
 892 {
 893         if (plane->state->fb)
 894                 drm_framebuffer_reference(plane->state->fb);
 895
 896         return 0;
 897 }
 898
 899 static void vop_plane_cleanup_fb(struct drm_plane *plane,
 900                                  const struct drm_plane_state *old_state)
 901 {
 902         if (old_state->fb)
 903                 drm_framebuffer_unreference(old_state->fb);
 904 }
 905
 906 static int vop_plane_atomic_check(struct drm_plane *plane,
 907                            struct drm_plane_state *state)
 908 {
 909         struct drm_crtc *crtc = state->crtc;
 910         struct drm_framebuffer *fb = state->fb;
 911         struct vop_win *win = to_vop_win(plane);
 912         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 913         struct drm_crtc_state *crtc_state;
 914         const struct vop_data *vop_data;
 915         struct vop *vop;
 916         bool visible;
 917         int ret;
 918         struct drm_rect *dest = &vop_plane_state->dest;
 919         struct drm_rect *src = &vop_plane_state->src;
 920         struct drm_rect clip;
 921         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
 922                                         DRM_PLANE_HELPER_NO_SCALING;
 923         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
 924                                         DRM_PLANE_HELPER_NO_SCALING;
 925         unsigned long offset;
 926         dma_addr_t dma_addr;
 927
 928         crtc = crtc ? crtc : plane->state->crtc;
 929         /*
 930          * Both crtc or plane->state->crtc can be null.
 931          */
 932         if (!crtc || !fb)
 933                 goto out_disable;
 934
 935         crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
 936         if (IS_ERR(crtc_state))
 937                 return PTR_ERR(crtc_state);
 938
 939         src->x1 = state->src_x;
 940         src->y1 = state->src_y;
 941         src->x2 = state->src_x + state->src_w;
 942         src->y2 = state->src_y + state->src_h;
 943         dest->x1 = state->crtc_x;
 944         dest->y1 = state->crtc_y;
 945         dest->x2 = state->crtc_x + state->crtc_w;
 946         dest->y2 = state->crtc_y + state->crtc_h;
 947
 948         clip.x1 = 0;
 949         clip.y1 = 0;
 950         clip.x2 = crtc_state->mode.hdisplay;
 951         clip.y2 = crtc_state->mode.vdisplay;
 952
 953         ret = drm_plane_helper_check_update(plane, crtc, state->fb,
 954                                             src, dest, &clip,
 955                                             min_scale,
 956                                             max_scale,
 957                                             true, true, &visible);
 958         if (ret)
 959                 return ret;
 960
 961         if (!visible)
 962                 goto out_disable;
 963
 964         vop_plane_state->format = vop_convert_format(fb->pixel_format);
 965         if (vop_plane_state->format < 0)
 966                 return vop_plane_state->format;
 967
 968         vop = to_vop(crtc);
 969         vop_data = vop->data;
 970
 971         if (drm_rect_width(src) >> 16 > vop_data->max_input.width ||
 972             drm_rect_height(src) >> 16 > vop_data->max_input.height) {
 973                 DRM_ERROR("Invalid source: %dx%d. max input: %dx%d\n",
 974                           drm_rect_width(src) >> 16,
 975                           drm_rect_height(src) >> 16,
 976                           vop_data->max_input.width,
 977                           vop_data->max_input.height);
 978                 return -EINVAL;
 979         }
 980
 981         /*
 982          * Src.x1 can be odd when do clip, but yuv plane start point
 983          * need align with 2 pixel.
 984          */
 985         if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2)) {
 986                 DRM_ERROR("Invalid Source: Yuv format Can't support odd xpos\n");
 987                 return -EINVAL;
 988         }
 989
 990         offset = (src->x1 >> 16) * drm_format_plane_bpp(fb->pixel_format, 0) / 8;
 991         if (state->rotation & BIT(DRM_REFLECT_Y))
 992                 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
 993         else
 994                 offset += (src->y1 >> 16) * fb->pitches[0];
 995
 996         dma_addr = rockchip_fb_get_dma_addr(fb, 0);
 997         vop_plane_state->yrgb_mst = dma_addr + offset + fb->offsets[0];
 998         if (is_yuv_support(fb->pixel_format)) {
 999                 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
1000                 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
1001                 int bpp = drm_format_plane_bpp(fb->pixel_format, 1);
1002
1003                 offset = (src->x1 >> 16) * bpp / hsub / 8;
1004                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
1005
1006                 dma_addr = rockchip_fb_get_dma_addr(fb, 1);
1007                 dma_addr += offset + fb->offsets[1];
1008                 vop_plane_state->uv_mst = dma_addr;
1009         }
1010
1011         vop_plane_state->enable = true;
1012
1013         return 0;
1014
1015 out_disable:
1016         vop_plane_state->enable = false;
1017         return 0;
1018 }
1019
1020 static void vop_plane_atomic_disable(struct drm_plane *plane,
1021                                      struct drm_plane_state *old_state)
1022 {
1023         struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
1024         struct vop_win *win = to_vop_win(plane);
1025         struct vop *vop = to_vop(old_state->crtc);
1026
1027         if (!old_state->crtc)
1028                 return;
1029
1030         spin_lock(&vop->reg_lock);
1031
1032         /*
1033          * FIXUP: some of the vop scale would be abnormal after windows power
1034          * on/off so deinit scale to scale_none mode.
1035          */
1036         if (win->phy->scl && win->phy->scl->ext) {
1037                 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
1038                 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
1039                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
1040                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
1041         }
1042         VOP_WIN_SET(vop, win, enable, 0);
1043
1044         spin_unlock(&vop->reg_lock);
1045
1046         vop_plane_state->enable = false;
1047 }
1048
1049 static void vop_plane_atomic_update(struct drm_plane *plane,
1050                 struct drm_plane_state *old_state)
1051 {
1052         struct drm_plane_state *state = plane->state;
1053         struct drm_crtc *crtc = state->crtc;
1054         struct vop_win *win = to_vop_win(plane);
1055         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
1056         struct rockchip_crtc_state *s;
1057         struct vop *vop;
1058         struct drm_framebuffer *fb = state->fb;
1059         unsigned int actual_w, actual_h;
1060         unsigned int dsp_stx, dsp_sty;
1061         uint32_t act_info, dsp_info, dsp_st;
1062         struct drm_rect *src = &vop_plane_state->src;
1063         struct drm_rect *dest = &vop_plane_state->dest;
1064         const uint32_t *y2r_table = vop_plane_state->y2r_table;
1065         const uint32_t *r2r_table = vop_plane_state->r2r_table;
1066         const uint32_t *r2y_table = vop_plane_state->r2y_table;
1067         int ymirror, xmirror;
1068         uint32_t val;
1069         bool rb_swap;
1070
1071         /*
1072          * can't update plane when vop is disabled.
1073          */
1074         if (!crtc)
1075                 return;
1076
1077         if (!vop_plane_state->enable) {
1078                 vop_plane_atomic_disable(plane, old_state);
1079                 return;
1080         }
1081
1082         actual_w = drm_rect_width(src) >> 16;
1083         actual_h = drm_rect_height(src) >> 16;
1084         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
1085
1086         dsp_info = (drm_rect_height(dest) - 1) << 16;
1087         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
1088
1089         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
1090         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
1091         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
1092
1093         ymirror = !!(state->rotation & BIT(DRM_REFLECT_Y));
1094         xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
1095
1096         vop = to_vop(state->crtc);
1097         s = to_rockchip_crtc_state(crtc->state);
1098
1099         spin_lock(&vop->reg_lock);
1100
1101         VOP_WIN_SET(vop, win, xmirror, xmirror);
1102         VOP_WIN_SET(vop, win, ymirror, ymirror);
1103         VOP_WIN_SET(vop, win, format, vop_plane_state->format);
1104         VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
1105         VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
1106         if (is_yuv_support(fb->pixel_format)) {
1107                 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
1108                 VOP_WIN_SET(vop, win, uv_mst, vop_plane_state->uv_mst);
1109         }
1110         VOP_WIN_SET(vop, win, fmt_10, is_yuv_10bit(fb->pixel_format));
1111
1112         scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
1113                             drm_rect_width(dest), drm_rect_height(dest),
1114                             fb->pixel_format);
1115
1116         VOP_WIN_SET(vop, win, act_info, act_info);
1117         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
1118         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
1119
1120         rb_swap = has_rb_swapped(fb->pixel_format);
1121         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
1122
1123         if (is_alpha_support(fb->pixel_format) &&
1124             (s->dsp_layer_sel & 0x3) != win->win_id) {
1125                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
1126                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
1127                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
1128                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
1129                         SRC_BLEND_M0(ALPHA_PER_PIX) |
1130                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
1131                         SRC_FACTOR_M0(ALPHA_ONE);
1132                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
1133                 VOP_WIN_SET(vop, win, alpha_mode, 1);
1134                 VOP_WIN_SET(vop, win, alpha_en, 1);
1135         } else {
1136                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
1137                 VOP_WIN_SET(vop, win, alpha_en, 0);
1138         }
1139
1140         if (win->csc) {
1141                 vop_load_csc_table(vop, win->csc->y2r_offset, y2r_table);
1142                 vop_load_csc_table(vop, win->csc->r2r_offset, r2r_table);
1143                 vop_load_csc_table(vop, win->csc->r2y_offset, r2y_table);
1144                 VOP_WIN_SET_EXT(vop, win, csc, y2r_en, !!y2r_table);
1145                 VOP_WIN_SET_EXT(vop, win, csc, r2r_en, !!r2r_table);
1146                 VOP_WIN_SET_EXT(vop, win, csc, r2y_en, !!r2y_table);
1147         }
1148         VOP_WIN_SET(vop, win, enable, 1);
1149         spin_unlock(&vop->reg_lock);
1150         vop->is_iommu_needed = true;
1151 }
1152
1153 static const struct drm_plane_helper_funcs plane_helper_funcs = {
1154         .prepare_fb = vop_plane_prepare_fb,
1155         .cleanup_fb = vop_plane_cleanup_fb,
1156         .atomic_check = vop_plane_atomic_check,
1157         .atomic_update = vop_plane_atomic_update,
1158         .atomic_disable = vop_plane_atomic_disable,
1159 };
1160
1161 void vop_atomic_plane_reset(struct drm_plane *plane)
1162 {
1163         struct vop_win *win = to_vop_win(plane);
1164         struct vop_plane_state *vop_plane_state =
1165                                         to_vop_plane_state(plane->state);
1166
1167         if (plane->state && plane->state->fb)
1168                 drm_framebuffer_unreference(plane->state->fb);
1169
1170         kfree(vop_plane_state);
1171         vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
1172         if (!vop_plane_state)
1173                 return;
1174
1175         vop_plane_state->zpos = win->win_id;
1176         plane->state = &vop_plane_state->base;
1177         plane->state->plane = plane;
1178 }
1179
1180 struct drm_plane_state *
1181 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
1182 {
1183         struct vop_plane_state *old_vop_plane_state;
1184         struct vop_plane_state *vop_plane_state;
1185
1186         if (WARN_ON(!plane->state))
1187                 return NULL;
1188
1189         old_vop_plane_state = to_vop_plane_state(plane->state);
1190         vop_plane_state = kmemdup(old_vop_plane_state,
1191                                   sizeof(*vop_plane_state), GFP_KERNEL);
1192         if (!vop_plane_state)
1193                 return NULL;
1194
1195         __drm_atomic_helper_plane_duplicate_state(plane,
1196                                                   &vop_plane_state->base);
1197
1198         return &vop_plane_state->base;
1199 }
1200
1201 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
1202                                            struct drm_plane_state *state)
1203 {
1204         struct vop_plane_state *vop_state = to_vop_plane_state(state);
1205
1206         __drm_atomic_helper_plane_destroy_state(plane, state);
1207
1208         kfree(vop_state);
1209 }
1210
1211 static int vop_atomic_plane_set_property(struct drm_plane *plane,
1212                                          struct drm_plane_state *state,
1213                                          struct drm_property *property,
1214                                          uint64_t val)
1215 {
1216         struct vop_win *win = to_vop_win(plane);
1217         struct vop_plane_state *plane_state = to_vop_plane_state(state);
1218
1219         if (property == win->vop->plane_zpos_prop) {
1220                 plane_state->zpos = val;
1221                 return 0;
1222         }
1223
1224         if (property == win->rotation_prop) {
1225                 state->rotation = val;
1226                 return 0;
1227         }
1228
1229         DRM_ERROR("failed to set vop plane property\n");
1230         return -EINVAL;
1231 }
1232
1233 static int vop_atomic_plane_get_property(struct drm_plane *plane,
1234                                          const struct drm_plane_state *state,
1235                                          struct drm_property *property,
1236                                          uint64_t *val)
1237 {
1238         struct vop_win *win = to_vop_win(plane);
1239         struct vop_plane_state *plane_state = to_vop_plane_state(state);
1240
1241         if (property == win->vop->plane_zpos_prop) {
1242                 *val = plane_state->zpos;
1243                 return 0;
1244         }
1245
1246         if (property == win->rotation_prop) {
1247                 *val = state->rotation;
1248                 return 0;
1249         }
1250
1251         DRM_ERROR("failed to get vop plane property\n");
1252         return -EINVAL;
1253 }
1254
1255 static const struct drm_plane_funcs vop_plane_funcs = {
1256         .update_plane   = drm_atomic_helper_update_plane,
1257         .disable_plane  = drm_atomic_helper_disable_plane,
1258         .destroy = vop_plane_destroy,
1259         .reset = vop_atomic_plane_reset,
1260         .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
1261         .atomic_destroy_state = vop_atomic_plane_destroy_state,
1262         .atomic_set_property = vop_atomic_plane_set_property,
1263         .atomic_get_property = vop_atomic_plane_get_property,
1264 };
1265
1266 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1267 {
1268         struct vop *vop = to_vop(crtc);
1269         unsigned long flags;
1270
1271         if (!vop->is_enabled)
1272                 return -EPERM;
1273
1274         spin_lock_irqsave(&vop->irq_lock, flags);
1275
1276         VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
1277         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
1278
1279         spin_unlock_irqrestore(&vop->irq_lock, flags);
1280
1281         return 0;
1282 }
1283
1284 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1285 {
1286         struct vop *vop = to_vop(crtc);
1287         unsigned long flags;
1288
1289         if (!vop->is_enabled)
1290                 return;
1291
1292         spin_lock_irqsave(&vop->irq_lock, flags);
1293
1294         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1295
1296         spin_unlock_irqrestore(&vop->irq_lock, flags);
1297 }
1298
1299 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
1300 {
1301         struct vop *vop = to_vop(crtc);
1302
1303         reinit_completion(&vop->wait_update_complete);
1304         WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
1305 }
1306
1307 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
1308                                            struct drm_file *file_priv)
1309 {
1310         struct drm_device *drm = crtc->dev;
1311         struct vop *vop = to_vop(crtc);
1312         struct drm_pending_vblank_event *e;
1313         unsigned long flags;
1314
1315         spin_lock_irqsave(&drm->event_lock, flags);
1316         e = vop->event;
1317         if (e && e->base.file_priv == file_priv) {
1318                 vop->event = NULL;
1319
1320                 e->base.destroy(&e->base);
1321                 file_priv->event_space += sizeof(e->event);
1322         }
1323         spin_unlock_irqrestore(&drm->event_lock, flags);
1324 }
1325
1326 static int vop_crtc_loader_protect(struct drm_crtc *crtc, bool on)
1327 {
1328         struct vop *vop = to_vop(crtc);
1329
1330         if (on == vop->loader_protect)
1331                 return 0;
1332
1333         if (on) {
1334                 vop_power_enable(crtc);
1335                 enable_irq(vop->irq);
1336                 drm_crtc_vblank_on(crtc);
1337                 vop->loader_protect = true;
1338         } else {
1339                 vop_crtc_disable(crtc);
1340
1341                 vop->loader_protect = false;
1342         }
1343
1344         return 0;
1345 }
1346
1347 static int vop_plane_info_dump(struct seq_file *s, struct drm_plane *plane)
1348 {
1349         struct vop_win *win = to_vop_win(plane);
1350         struct drm_plane_state *state = plane->state;
1351         struct vop_plane_state *pstate = to_vop_plane_state(state);
1352         struct drm_rect *src, *dest;
1353         struct drm_framebuffer *fb = state->fb;
1354         int i;
1355
1356         seq_printf(s, "    win%d-%d: %s\n", win->win_id, win->area_id,
1357                    pstate->enable ? "ACTIVE" : "DISABLED");
1358         if (!fb)
1359                 return 0;
1360
1361         src = &pstate->src;
1362         dest = &pstate->dest;
1363
1364         seq_printf(s, "\tformat: %s%s\n", drm_get_format_name(fb->pixel_format),
1365                    fb->modifier[0] == DRM_FORMAT_MOD_ARM_AFBC ? "[AFBC]" : "");
1366         seq_printf(s, "\tzpos: %d\n", pstate->zpos);
1367         seq_printf(s, "\tsrc: pos[%dx%d] rect[%dx%d]\n", src->x1 >> 16,
1368                    src->y1 >> 16, drm_rect_width(src) >> 16,
1369                    drm_rect_height(src) >> 16);
1370         seq_printf(s, "\tdst: pos[%dx%d] rect[%dx%d]\n", dest->x1, dest->y1,
1371                    drm_rect_width(dest), drm_rect_height(dest));
1372
1373         for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
1374                 dma_addr_t fb_addr = rockchip_fb_get_dma_addr(fb, i);
1375                 seq_printf(s, "\tbuf[%d]: addr: %pad pitch: %d offset: %d\n",
1376                            i, &fb_addr, fb->pitches[i], fb->offsets[i]);
1377         }
1378
1379         return 0;
1380 }
1381
1382 static int vop_crtc_debugfs_dump(struct drm_crtc *crtc, struct seq_file *s)
1383 {
1384         struct vop *vop = to_vop(crtc);
1385         struct drm_crtc_state *crtc_state = crtc->state;
1386         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1387         struct rockchip_crtc_state *state = to_rockchip_crtc_state(crtc->state);
1388         bool interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1389         struct drm_plane *plane;
1390         int i;
1391
1392         seq_printf(s, "VOP [%s]: %s\n", dev_name(vop->dev),
1393                    crtc_state->active ? "ACTIVE" : "DISABLED");
1394
1395         if (!crtc_state->active)
1396                 return 0;
1397
1398         seq_printf(s, "    Connector: %s\n",
1399                    drm_get_connector_name(state->output_type));
1400         seq_printf(s, "\tbus_format[%x] output_mode[%x]\n",
1401                    state->bus_format, state->output_mode);
1402         seq_printf(s, "    Display mode: %dx%d%s%d\n",
1403                    mode->hdisplay, mode->vdisplay, interlaced ? "i" : "p",
1404                    drm_mode_vrefresh(mode));
1405         seq_printf(s, "\tclk[%d] real_clk[%d] type[%x] flag[%x]\n",
1406                    mode->clock, mode->crtc_clock, mode->type, mode->flags);
1407         seq_printf(s, "\tH: %d %d %d %d\n", mode->hdisplay, mode->hsync_start,
1408                    mode->hsync_end, mode->htotal);
1409         seq_printf(s, "\tV: %d %d %d %d\n", mode->vdisplay, mode->vsync_start,
1410                    mode->vsync_end, mode->vtotal);
1411
1412         for (i = 0; i < vop->num_wins; i++) {
1413                 plane = &vop->win[i].base;
1414                 vop_plane_info_dump(s, plane);
1415         }
1416
1417         return 0;
1418 }
1419
1420 static enum drm_mode_status
1421 vop_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode,
1422                     int output_type)
1423 {
1424         struct vop *vop = to_vop(crtc);
1425         const struct vop_data *vop_data = vop->data;
1426         int request_clock = mode->clock;
1427         int clock;
1428
1429         if (mode->hdisplay > vop_data->max_output.width)
1430                 return MODE_BAD_HVALUE;
1431         if (mode->vdisplay > vop_data->max_output.height)
1432                 return MODE_BAD_VVALUE;
1433
1434         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1435                 request_clock *= 2;
1436         clock = clk_round_rate(vop->dclk, request_clock * 1000) / 1000;
1437
1438         /*
1439          * Hdmi or DisplayPort request a Accurate clock.
1440          */
1441         if (output_type == DRM_MODE_CONNECTOR_HDMIA ||
1442             output_type == DRM_MODE_CONNECTOR_DisplayPort)
1443                 if (clock != request_clock)
1444                         return MODE_CLOCK_RANGE;
1445
1446         return MODE_OK;
1447 }
1448
1449 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1450         .loader_protect = vop_crtc_loader_protect,
1451         .enable_vblank = vop_crtc_enable_vblank,
1452         .disable_vblank = vop_crtc_disable_vblank,
1453         .wait_for_update = vop_crtc_wait_for_update,
1454         .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
1455         .debugfs_dump = vop_crtc_debugfs_dump,
1456         .mode_valid = vop_crtc_mode_valid,
1457 };
1458
1459 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1460                                 const struct drm_display_mode *mode,
1461                                 struct drm_display_mode *adjusted_mode)
1462 {
1463         struct vop *vop = to_vop(crtc);
1464         const struct vop_data *vop_data = vop->data;
1465         int request_clock = mode->clock;
1466
1467         if (mode->hdisplay > vop_data->max_output.width ||
1468             mode->vdisplay > vop_data->max_output.height)
1469                 return false;
1470
1471         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1472                 request_clock *= 2;
1473         adjusted_mode->crtc_clock =
1474                 clk_round_rate(vop->dclk, request_clock * 1000) / 1000;
1475
1476         return true;
1477 }
1478
1479 static void vop_crtc_enable(struct drm_crtc *crtc)
1480 {
1481         struct vop *vop = to_vop(crtc);
1482         const struct vop_data *vop_data = vop->data;
1483         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1484         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1485         u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1486         u16 hdisplay = adjusted_mode->crtc_hdisplay;
1487         u16 htotal = adjusted_mode->crtc_htotal;
1488         u16 hact_st = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_start;
1489         u16 hact_end = hact_st + hdisplay;
1490         u16 vdisplay = adjusted_mode->crtc_vdisplay;
1491         u16 vtotal = adjusted_mode->crtc_vtotal;
1492         u16 vsync_len = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1493         u16 vact_st = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
1494         u16 vact_end = vact_st + vdisplay;
1495         uint32_t val;
1496
1497         vop_initial(crtc);
1498
1499         val = BIT(DCLK_INVERT);
1500         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ?
1501                    0 : BIT(HSYNC_POSITIVE);
1502         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ?
1503                    0 : BIT(VSYNC_POSITIVE);
1504         VOP_CTRL_SET(vop, pin_pol, val);
1505         switch (s->output_type) {
1506         case DRM_MODE_CONNECTOR_LVDS:
1507                 VOP_CTRL_SET(vop, rgb_en, 1);
1508                 VOP_CTRL_SET(vop, rgb_pin_pol, val);
1509                 break;
1510         case DRM_MODE_CONNECTOR_eDP:
1511                 VOP_CTRL_SET(vop, edp_en, 1);
1512                 VOP_CTRL_SET(vop, edp_pin_pol, val);
1513                 break;
1514         case DRM_MODE_CONNECTOR_HDMIA:
1515                 VOP_CTRL_SET(vop, hdmi_en, 1);
1516                 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1517                 break;
1518         case DRM_MODE_CONNECTOR_DSI:
1519                 VOP_CTRL_SET(vop, mipi_en, 1);
1520                 VOP_CTRL_SET(vop, mipi_pin_pol, val);
1521                 break;
1522         case DRM_MODE_CONNECTOR_DisplayPort:
1523                 val &= ~BIT(DCLK_INVERT);
1524                 VOP_CTRL_SET(vop, dp_pin_pol, val);
1525                 VOP_CTRL_SET(vop, dp_en, 1);
1526                 break;
1527         default:
1528                 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1529         }
1530
1531         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1532             !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1533                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1534
1535         VOP_CTRL_SET(vop, out_mode, s->output_mode);
1536         switch (s->bus_format) {
1537         case MEDIA_BUS_FMT_RGB565_1X16:
1538                 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565);
1539                 break;
1540         case MEDIA_BUS_FMT_RGB666_1X18:
1541         case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
1542                 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666);
1543                 break;
1544         case MEDIA_BUS_FMT_YUV8_1X24:
1545                 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(1);
1546                 break;
1547         case MEDIA_BUS_FMT_YUV10_1X30:
1548                 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
1549                 break;
1550         case MEDIA_BUS_FMT_RGB888_1X24:
1551         default:
1552                 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
1553                 break;
1554         }
1555
1556         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA)
1557                 val |= PRE_DITHER_DOWN_EN(0);
1558         else
1559                 val |= PRE_DITHER_DOWN_EN(1);
1560         val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO);
1561         VOP_CTRL_SET(vop, dither_down, val);
1562         VOP_CTRL_SET(vop, dclk_ddr,
1563                      s->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0);
1564         VOP_CTRL_SET(vop, overlay_mode, is_yuv_output(s->bus_format));
1565         VOP_CTRL_SET(vop, dsp_out_yuv, is_yuv_output(s->bus_format));
1566         VOP_CTRL_SET(vop, dsp_background,
1567                      is_yuv_output(s->bus_format) ? 0x20010200 : 0);
1568
1569         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1570         val = hact_st << 16;
1571         val |= hact_end;
1572         VOP_CTRL_SET(vop, hact_st_end, val);
1573         VOP_CTRL_SET(vop, hpost_st_end, val);
1574
1575         VOP_CTRL_SET(vop, vtotal_pw, (adjusted_mode->vtotal << 16) | vsync_len);
1576         val = vact_st << 16;
1577         val |= vact_end;
1578         VOP_CTRL_SET(vop, vact_st_end, val);
1579         VOP_CTRL_SET(vop, vpost_st_end, val);
1580         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
1581                 u16 vact_st_f1 = vtotal + vact_st + 1;
1582                 u16 vact_end_f1 = vact_st_f1 + vdisplay;
1583
1584                 val = vact_st_f1 << 16 | vact_end_f1;
1585                 VOP_CTRL_SET(vop, vact_st_end_f1, val);
1586                 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
1587
1588                 val = vtotal << 16 | (vtotal + vsync_len);
1589                 VOP_CTRL_SET(vop, vs_st_end_f1, val);
1590                 VOP_CTRL_SET(vop, dsp_interlace, 1);
1591                 VOP_CTRL_SET(vop, p2i_en, 1);
1592         } else {
1593                 VOP_CTRL_SET(vop, dsp_interlace, 0);
1594                 VOP_CTRL_SET(vop, p2i_en, 0);
1595         }
1596
1597         VOP_CTRL_SET(vop, core_dclk_div,
1598                      !!(adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK));
1599
1600         clk_set_rate(vop->dclk, adjusted_mode->crtc_clock * 1000);
1601
1602         vop_cfg_done(vop);
1603         /*
1604          * enable vop, all the register would take effect when vop exit standby
1605          */
1606         VOP_CTRL_SET(vop, standby, 0);
1607
1608         enable_irq(vop->irq);
1609         drm_crtc_vblank_on(crtc);
1610 }
1611
1612 static int vop_zpos_cmp(const void *a, const void *b)
1613 {
1614         struct vop_zpos *pa = (struct vop_zpos *)a;
1615         struct vop_zpos *pb = (struct vop_zpos *)b;
1616
1617         return pa->zpos - pb->zpos;
1618 }
1619
1620 static int vop_afbdc_atomic_check(struct drm_crtc *crtc,
1621                                   struct drm_crtc_state *crtc_state)
1622 {
1623         struct vop *vop = to_vop(crtc);
1624         const struct vop_data *vop_data = vop->data;
1625         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1626         struct drm_atomic_state *state = crtc_state->state;
1627         struct drm_plane *plane;
1628         struct drm_plane_state *pstate;
1629         struct vop_plane_state *plane_state;
1630         struct vop_win *win;
1631         int afbdc_format;
1632         int i;
1633
1634         s->afbdc_en = 0;
1635
1636         for_each_plane_in_state(state, plane, pstate, i) {
1637                 struct drm_framebuffer *fb = pstate->fb;
1638                 struct drm_rect *src;
1639
1640                 win = to_vop_win(plane);
1641                 plane_state = to_vop_plane_state(pstate);
1642
1643                 if (pstate->crtc != crtc || !fb)
1644                         continue;
1645
1646                 if (fb->modifier[0] != DRM_FORMAT_MOD_ARM_AFBC)
1647                         continue;
1648
1649                 if (!(vop_data->feature & VOP_FEATURE_AFBDC)) {
1650                         DRM_ERROR("not support afbdc\n");
1651                         return -EINVAL;
1652                 }
1653
1654                 switch (plane_state->format) {
1655                 case VOP_FMT_ARGB8888:
1656                         afbdc_format = AFBDC_FMT_U8U8U8U8;
1657                         break;
1658                 case VOP_FMT_RGB888:
1659                         afbdc_format = AFBDC_FMT_U8U8U8;
1660                         break;
1661                 case VOP_FMT_RGB565:
1662                         afbdc_format = AFBDC_FMT_RGB565;
1663                         break;
1664                 default:
1665                         return -EINVAL;
1666                 }
1667
1668                 if (s->afbdc_en) {
1669                         DRM_ERROR("vop only support one afbc layer\n");
1670                         return -EINVAL;
1671                 }
1672
1673                 src = &plane_state->src;
1674                 if (src->x1 || src->y1 || fb->offsets[0]) {
1675                         DRM_ERROR("win[%d] afbdc not support offset display\n",
1676                                   win->win_id);
1677                         DRM_ERROR("xpos=%d, ypos=%d, offset=%d\n",
1678                                   src->x1, src->y1, fb->offsets[0]);
1679                         return -EINVAL;
1680                 }
1681                 s->afbdc_win_format = afbdc_format;
1682                 s->afbdc_win_width = pstate->fb->width - 1;
1683                 s->afbdc_win_height = (drm_rect_height(src) >> 16) - 1;
1684                 s->afbdc_win_id = win->win_id;
1685                 s->afbdc_win_ptr = plane_state->yrgb_mst;
1686                 s->afbdc_en = 1;
1687         }
1688
1689         return 0;
1690 }
1691
1692 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1693                                  struct drm_crtc_state *crtc_state)
1694 {
1695         struct drm_atomic_state *state = crtc_state->state;
1696         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1697         struct vop *vop = to_vop(crtc);
1698         const struct vop_data *vop_data = vop->data;
1699         struct drm_plane *plane;
1700         struct drm_plane_state *pstate;
1701         struct vop_plane_state *plane_state;
1702         struct vop_zpos *pzpos;
1703         int dsp_layer_sel = 0;
1704         int i, j, cnt = 0, ret = 0;
1705
1706         ret = vop_afbdc_atomic_check(crtc, crtc_state);
1707         if (ret)
1708                 return ret;
1709
1710         ret = vop_csc_atomic_check(crtc, crtc_state);
1711         if (ret)
1712                 return ret;
1713
1714         pzpos = kmalloc_array(vop_data->win_size, sizeof(*pzpos), GFP_KERNEL);
1715         if (!pzpos)
1716                 return -ENOMEM;
1717
1718         for (i = 0; i < vop_data->win_size; i++) {
1719                 const struct vop_win_data *win_data = &vop_data->win[i];
1720                 struct vop_win *win;
1721
1722                 if (!win_data->phy)
1723                         continue;
1724
1725                 for (j = 0; j < vop->num_wins; j++) {
1726                         win = &vop->win[j];
1727
1728                         if (win->win_id == i && !win->area_id)
1729                                 break;
1730                 }
1731                 if (WARN_ON(j >= vop->num_wins)) {
1732                         ret = -EINVAL;
1733                         goto err_free_pzpos;
1734                 }
1735
1736                 plane = &win->base;
1737                 pstate = state->plane_states[drm_plane_index(plane)];
1738                 /*
1739                  * plane might not have changed, in which case take
1740                  * current state:
1741                  */
1742                 if (!pstate)
1743                         pstate = plane->state;
1744                 plane_state = to_vop_plane_state(pstate);
1745                 pzpos[cnt].zpos = plane_state->zpos;
1746                 pzpos[cnt++].win_id = win->win_id;
1747         }
1748
1749         sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
1750
1751         for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
1752                 const struct vop_win_data *win_data = &vop_data->win[i];
1753                 int shift = i * 2;
1754
1755                 if (win_data->phy) {
1756                         struct vop_zpos *zpos = &pzpos[cnt++];
1757
1758                         dsp_layer_sel |= zpos->win_id << shift;
1759                 } else {
1760                         dsp_layer_sel |= i << shift;
1761                 }
1762         }
1763
1764         s->dsp_layer_sel = dsp_layer_sel;
1765
1766 err_free_pzpos:
1767         kfree(pzpos);
1768         return ret;
1769 }
1770
1771 static void vop_post_config(struct drm_crtc *crtc)
1772 {
1773         struct vop *vop = to_vop(crtc);
1774         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1775         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1776         u16 vtotal = mode->crtc_vtotal;
1777         u16 hdisplay = mode->crtc_hdisplay;
1778         u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
1779         u16 vdisplay = mode->crtc_vdisplay;
1780         u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
1781         u16 hsize = hdisplay * (s->left_margin + s->right_margin) / 200;
1782         u16 vsize = vdisplay * (s->top_margin + s->bottom_margin) / 200;
1783         u16 hact_end, vact_end;
1784         u32 val;
1785
1786         hact_st += hdisplay * (100 - s->left_margin) / 200;
1787         hact_end = hact_st + hsize;
1788         val = hact_st << 16;
1789         val |= hact_end;
1790         VOP_CTRL_SET(vop, hpost_st_end, val);
1791         vact_st += vdisplay * (100 - s->top_margin) / 200;
1792         vact_end = vact_st + vsize;
1793         val = vact_st << 16;
1794         val |= vact_end;
1795         VOP_CTRL_SET(vop, vpost_st_end, val);
1796         val = scl_cal_scale2(vdisplay, vsize) << 16;
1797         val |= scl_cal_scale2(hdisplay, hsize);
1798         VOP_CTRL_SET(vop, post_scl_factor, val);
1799         VOP_CTRL_SET(vop, post_scl_ctrl, 0x3);
1800         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1801                 u16 vact_st_f1 = vtotal + vact_st + 1;
1802                 u16 vact_end_f1 = vact_st_f1 + vsize;
1803
1804                 val = vact_st_f1 << 16 | vact_end_f1;
1805                 VOP_CTRL_SET(vop, vpost_st_end_f1, val);
1806         }
1807 }
1808
1809 static void vop_cfg_update(struct drm_crtc *crtc,
1810                            struct drm_crtc_state *old_crtc_state)
1811 {
1812         struct rockchip_crtc_state *s =
1813                         to_rockchip_crtc_state(crtc->state);
1814         struct vop *vop = to_vop(crtc);
1815
1816         spin_lock(&vop->reg_lock);
1817
1818         if (s->afbdc_en) {
1819                 uint32_t pic_size;
1820
1821                 VOP_CTRL_SET(vop, afbdc_format, s->afbdc_win_format | 1 << 4);
1822                 VOP_CTRL_SET(vop, afbdc_hreg_block_split, 0);
1823                 VOP_CTRL_SET(vop, afbdc_sel, s->afbdc_win_id);
1824                 VOP_CTRL_SET(vop, afbdc_hdr_ptr, s->afbdc_win_ptr);
1825                 pic_size = (s->afbdc_win_width & 0xffff);
1826                 pic_size |= s->afbdc_win_height << 16;
1827                 VOP_CTRL_SET(vop, afbdc_pic_size, pic_size);
1828         }
1829
1830         VOP_CTRL_SET(vop, afbdc_en, s->afbdc_en);
1831         VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
1832         vop_post_config(crtc);
1833
1834         spin_unlock(&vop->reg_lock);
1835 }
1836
1837 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1838                                   struct drm_crtc_state *old_crtc_state)
1839 {
1840         struct vop *vop = to_vop(crtc);
1841
1842         vop_cfg_update(crtc, old_crtc_state);
1843
1844         if (!vop->is_iommu_enabled && vop->is_iommu_needed) {
1845                 bool need_wait_vblank = !vop_is_allwin_disabled(vop);
1846                 int ret;
1847
1848                 if (need_wait_vblank) {
1849                         bool active;
1850
1851                         disable_irq(vop->irq);
1852                         drm_crtc_vblank_get(crtc);
1853                         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
1854
1855                         ret = readx_poll_timeout_atomic(vop_fs_irq_is_active,
1856                                                         vop, active, active,
1857                                                         0, 50 * 1000);
1858                         if (ret)
1859                                 dev_err(vop->dev, "wait fs irq timeout\n");
1860
1861                         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
1862                         vop_cfg_done(vop);
1863
1864                         ret = readx_poll_timeout_atomic(vop_line_flag_is_active,
1865                                                         vop, active, active,
1866                                                         0, 50 * 1000);
1867                         if (ret)
1868                                 dev_err(vop->dev, "wait line flag timeout\n");
1869
1870                         enable_irq(vop->irq);
1871                 }
1872                 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
1873                 if (ret)
1874                         dev_err(vop->dev, "failed to attach dma mapping, %d\n",
1875                                 ret);
1876
1877                 if (need_wait_vblank) {
1878                         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
1879                         drm_crtc_vblank_put(crtc);
1880                 }
1881
1882                 vop->is_iommu_enabled = true;
1883         }
1884
1885         vop_cfg_done(vop);
1886 }
1887
1888 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1889                                   struct drm_crtc_state *old_crtc_state)
1890 {
1891         struct vop *vop = to_vop(crtc);
1892
1893         if (crtc->state->event) {
1894                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1895
1896                 vop->event = crtc->state->event;
1897                 crtc->state->event = NULL;
1898         }
1899 }
1900
1901 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1902         .enable = vop_crtc_enable,
1903         .disable = vop_crtc_disable,
1904         .mode_fixup = vop_crtc_mode_fixup,
1905         .atomic_check = vop_crtc_atomic_check,
1906         .atomic_flush = vop_crtc_atomic_flush,
1907         .atomic_begin = vop_crtc_atomic_begin,
1908 };
1909
1910 static void vop_crtc_destroy(struct drm_crtc *crtc)
1911 {
1912         drm_crtc_cleanup(crtc);
1913 }
1914
1915 static void vop_crtc_reset(struct drm_crtc *crtc)
1916 {
1917         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1918
1919         if (crtc->state) {
1920                 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
1921                 kfree(s);
1922         }
1923
1924         s = kzalloc(sizeof(*s), GFP_KERNEL);
1925         if (!s)
1926                 return;
1927         crtc->state = &s->base;
1928         crtc->state->crtc = crtc;
1929         s->left_margin = 100;
1930         s->right_margin = 100;
1931         s->top_margin = 100;
1932         s->bottom_margin = 100;
1933 }
1934
1935 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1936 {
1937         struct rockchip_crtc_state *rockchip_state, *old_state;
1938
1939         old_state = to_rockchip_crtc_state(crtc->state);
1940         rockchip_state = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL);
1941         if (!rockchip_state)
1942                 return NULL;
1943
1944         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1945         return &rockchip_state->base;
1946 }
1947
1948 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1949                                    struct drm_crtc_state *state)
1950 {
1951         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1952
1953         __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
1954         kfree(s);
1955 }
1956
1957 static int vop_crtc_atomic_get_property(struct drm_crtc *crtc,
1958                                         const struct drm_crtc_state *state,
1959                                         struct drm_property *property,
1960                                         uint64_t *val)
1961 {
1962         struct drm_device *drm_dev = crtc->dev;
1963         struct drm_mode_config *mode_config = &drm_dev->mode_config;
1964         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1965
1966         if (property == mode_config->tv_left_margin_property) {
1967                 *val = s->left_margin;
1968                 return 0;
1969         }
1970
1971         if (property == mode_config->tv_right_margin_property) {
1972                 *val = s->right_margin;
1973                 return 0;
1974         }
1975
1976         if (property == mode_config->tv_top_margin_property) {
1977                 *val = s->top_margin;
1978                 return 0;
1979         }
1980
1981         if (property == mode_config->tv_bottom_margin_property) {
1982                 *val = s->bottom_margin;
1983                 return 0;
1984         }
1985
1986         DRM_ERROR("failed to get vop crtc property\n");
1987         return -EINVAL;
1988 }
1989
1990 static int vop_crtc_atomic_set_property(struct drm_crtc *crtc,
1991                                         struct drm_crtc_state *state,
1992                                         struct drm_property *property,
1993                                         uint64_t val)
1994 {
1995         struct drm_device *drm_dev = crtc->dev;
1996         struct drm_mode_config *mode_config = &drm_dev->mode_config;
1997         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1998
1999         if (property == mode_config->tv_left_margin_property) {
2000                 s->left_margin = val;
2001                 return 0;
2002         }
2003
2004         if (property == mode_config->tv_right_margin_property) {
2005                 s->right_margin = val;
2006                 return 0;
2007         }
2008
2009         if (property == mode_config->tv_top_margin_property) {
2010                 s->top_margin = val;
2011                 return 0;
2012         }
2013
2014         if (property == mode_config->tv_bottom_margin_property) {
2015                 s->bottom_margin = val;
2016                 return 0;
2017         }
2018
2019         DRM_ERROR("failed to set vop crtc property\n");
2020         return -EINVAL;
2021 }
2022
2023 static const struct drm_crtc_funcs vop_crtc_funcs = {
2024         .set_config = drm_atomic_helper_set_config,
2025         .page_flip = drm_atomic_helper_page_flip,
2026         .destroy = vop_crtc_destroy,
2027         .reset = vop_crtc_reset,
2028         .atomic_get_property = vop_crtc_atomic_get_property,
2029         .atomic_set_property = vop_crtc_atomic_set_property,
2030         .atomic_duplicate_state = vop_crtc_duplicate_state,
2031         .atomic_destroy_state = vop_crtc_destroy_state,
2032 };
2033
2034 static void vop_handle_vblank(struct vop *vop)
2035 {
2036         struct drm_device *drm = vop->drm_dev;
2037         struct drm_crtc *crtc = &vop->crtc;
2038         unsigned long flags;
2039
2040         if (!vop_is_cfg_done_complete(vop))
2041                 return;
2042
2043         if (vop->event) {
2044                 spin_lock_irqsave(&drm->event_lock, flags);
2045
2046                 drm_crtc_send_vblank_event(crtc, vop->event);
2047                 drm_crtc_vblank_put(crtc);
2048                 vop->event = NULL;
2049
2050                 spin_unlock_irqrestore(&drm->event_lock, flags);
2051         }
2052         if (!completion_done(&vop->wait_update_complete))
2053                 complete(&vop->wait_update_complete);
2054 }
2055
2056 static irqreturn_t vop_isr(int irq, void *data)
2057 {
2058         struct vop *vop = data;
2059         struct drm_crtc *crtc = &vop->crtc;
2060         uint32_t active_irqs;
2061         unsigned long flags;
2062         int ret = IRQ_NONE;
2063
2064         /*
2065          * interrupt register has interrupt status, enable and clear bits, we
2066          * must hold irq_lock to avoid a race with enable/disable_vblank().
2067         */
2068         spin_lock_irqsave(&vop->irq_lock, flags);
2069
2070         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
2071         /* Clear all active interrupt sources */
2072         if (active_irqs)
2073                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
2074
2075         spin_unlock_irqrestore(&vop->irq_lock, flags);
2076
2077         /* This is expected for vop iommu irqs, since the irq is shared */
2078         if (!active_irqs)
2079                 return IRQ_NONE;
2080
2081         if (active_irqs & DSP_HOLD_VALID_INTR) {
2082                 complete(&vop->dsp_hold_completion);
2083                 active_irqs &= ~DSP_HOLD_VALID_INTR;
2084                 ret = IRQ_HANDLED;
2085         }
2086
2087         if (active_irqs & LINE_FLAG_INTR) {
2088                 complete(&vop->line_flag_completion);
2089                 active_irqs &= ~LINE_FLAG_INTR;
2090                 ret = IRQ_HANDLED;
2091         }
2092
2093         if (active_irqs & FS_INTR) {
2094                 drm_crtc_handle_vblank(crtc);
2095                 vop_handle_vblank(vop);
2096                 active_irqs &= ~FS_INTR;
2097                 ret = IRQ_HANDLED;
2098         }
2099
2100         /* Unhandled irqs are spurious. */
2101         if (active_irqs)
2102                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
2103
2104         return ret;
2105 }
2106
2107 static int vop_plane_init(struct vop *vop, struct vop_win *win,
2108                           unsigned long possible_crtcs)
2109 {
2110         struct drm_plane *share = NULL;
2111         unsigned int rotations = 0;
2112         struct drm_property *prop;
2113         uint64_t feature = 0;
2114         int ret;
2115
2116         if (win->parent)
2117                 share = &win->parent->base;
2118
2119         ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
2120                                    possible_crtcs, &vop_plane_funcs,
2121                                    win->data_formats, win->nformats, win->type);
2122         if (ret) {
2123                 DRM_ERROR("failed to initialize plane\n");
2124                 return ret;
2125         }
2126         drm_plane_helper_add(&win->base, &plane_helper_funcs);
2127         drm_object_attach_property(&win->base.base,
2128                                    vop->plane_zpos_prop, win->win_id);
2129
2130         if (VOP_WIN_SUPPORT(vop, win, xmirror))
2131                 rotations |= BIT(DRM_REFLECT_X);
2132
2133         if (VOP_WIN_SUPPORT(vop, win, ymirror))
2134                 rotations |= BIT(DRM_REFLECT_Y);
2135
2136         if (rotations) {
2137                 rotations |= BIT(DRM_ROTATE_0);
2138                 prop = drm_mode_create_rotation_property(vop->drm_dev,
2139                                                          rotations);
2140                 if (!prop) {
2141                         DRM_ERROR("failed to create zpos property\n");
2142                         return -EINVAL;
2143                 }
2144                 drm_object_attach_property(&win->base.base, prop,
2145                                            BIT(DRM_ROTATE_0));
2146                 win->rotation_prop = prop;
2147         }
2148         if (win->phy->scl)
2149                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE);
2150         if (VOP_WIN_SUPPORT(vop, win, src_alpha_ctl) ||
2151             VOP_WIN_SUPPORT(vop, win, alpha_en))
2152                 feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA);
2153
2154         drm_object_attach_property(&win->base.base, vop->plane_feature_prop,
2155                                    feature);
2156
2157         return 0;
2158 }
2159
2160 static int vop_create_crtc(struct vop *vop)
2161 {
2162         struct device *dev = vop->dev;
2163         const struct vop_data *vop_data = vop->data;
2164         struct drm_device *drm_dev = vop->drm_dev;
2165         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
2166         struct drm_crtc *crtc = &vop->crtc;
2167         struct device_node *port;
2168         uint64_t feature = 0;
2169         int ret;
2170         int i;
2171
2172         /*
2173          * Create drm_plane for primary and cursor planes first, since we need
2174          * to pass them to drm_crtc_init_with_planes, which sets the
2175          * "possible_crtcs" to the newly initialized crtc.
2176          */
2177         for (i = 0; i < vop->num_wins; i++) {
2178                 struct vop_win *win = &vop->win[i];
2179
2180                 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
2181                     win->type != DRM_PLANE_TYPE_CURSOR)
2182                         continue;
2183
2184                 ret = vop_plane_init(vop, win, 0);
2185                 if (ret)
2186                         goto err_cleanup_planes;
2187
2188                 plane = &win->base;
2189                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
2190                         primary = plane;
2191                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
2192                         cursor = plane;
2193
2194         }
2195
2196         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
2197                                         &vop_crtc_funcs, NULL);
2198         if (ret)
2199                 goto err_cleanup_planes;
2200
2201         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
2202
2203         /*
2204          * Create drm_planes for overlay windows with possible_crtcs restricted
2205          * to the newly created crtc.
2206          */
2207         for (i = 0; i < vop->num_wins; i++) {
2208                 struct vop_win *win = &vop->win[i];
2209                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
2210
2211                 if (win->type != DRM_PLANE_TYPE_OVERLAY)
2212                         continue;
2213
2214                 ret = vop_plane_init(vop, win, possible_crtcs);
2215                 if (ret)
2216                         goto err_cleanup_crtc;
2217         }
2218
2219         port = of_get_child_by_name(dev->of_node, "port");
2220         if (!port) {
2221                 DRM_ERROR("no port node found in %s\n",
2222                           dev->of_node->full_name);
2223                 ret = -ENOENT;
2224                 goto err_cleanup_crtc;
2225         }
2226
2227         init_completion(&vop->dsp_hold_completion);
2228         init_completion(&vop->wait_update_complete);
2229         init_completion(&vop->line_flag_completion);
2230         crtc->port = port;
2231         rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
2232
2233         ret = drm_mode_create_tv_properties(drm_dev, 0, NULL);
2234         if (ret)
2235                 goto err_unregister_crtc_funcs;
2236 #define VOP_ATTACH_MODE_CONFIG_PROP(prop, v) \
2237         drm_object_attach_property(&crtc->base, drm_dev->mode_config.prop, v)
2238
2239         VOP_ATTACH_MODE_CONFIG_PROP(tv_left_margin_property, 100);
2240         VOP_ATTACH_MODE_CONFIG_PROP(tv_right_margin_property, 100);
2241         VOP_ATTACH_MODE_CONFIG_PROP(tv_top_margin_property, 100);
2242         VOP_ATTACH_MODE_CONFIG_PROP(tv_bottom_margin_property, 100);
2243 #undef VOP_ATTACH_MODE_CONFIG_PROP
2244
2245         if (vop_data->feature & VOP_FEATURE_AFBDC)
2246                 feature |= BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC);
2247         drm_object_attach_property(&crtc->base, vop->feature_prop,
2248                                    feature);
2249
2250         return 0;
2251
2252 err_unregister_crtc_funcs:
2253         rockchip_unregister_crtc_funcs(crtc);
2254 err_cleanup_crtc:
2255         drm_crtc_cleanup(crtc);
2256 err_cleanup_planes:
2257         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
2258                                  head)
2259                 drm_plane_cleanup(plane);
2260         return ret;
2261 }
2262
2263 static void vop_destroy_crtc(struct vop *vop)
2264 {
2265         struct drm_crtc *crtc = &vop->crtc;
2266         struct drm_device *drm_dev = vop->drm_dev;
2267         struct drm_plane *plane, *tmp;
2268
2269         rockchip_unregister_crtc_funcs(crtc);
2270         of_node_put(crtc->port);
2271
2272         /*
2273          * We need to cleanup the planes now.  Why?
2274          *
2275          * The planes are "&vop->win[i].base".  That means the memory is
2276          * all part of the big "struct vop" chunk of memory.  That memory
2277          * was devm allocated and associated with this component.  We need to
2278          * free it ourselves before vop_unbind() finishes.
2279          */
2280         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
2281                                  head)
2282                 vop_plane_destroy(plane);
2283
2284         /*
2285          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
2286          * references the CRTC.
2287          */
2288         drm_crtc_cleanup(crtc);
2289 }
2290
2291 /*
2292  * Initialize the vop->win array elements.
2293  */
2294 static int vop_win_init(struct vop *vop)
2295 {
2296         const struct vop_data *vop_data = vop->data;
2297         unsigned int i, j;
2298         unsigned int num_wins = 0;
2299         struct drm_property *prop;
2300         static const struct drm_prop_enum_list props[] = {
2301                 { ROCKCHIP_DRM_PLANE_FEATURE_SCALE, "scale" },
2302                 { ROCKCHIP_DRM_PLANE_FEATURE_ALPHA, "alpha" },
2303         };
2304         static const struct drm_prop_enum_list crtc_props[] = {
2305                 { ROCKCHIP_DRM_CRTC_FEATURE_AFBDC, "afbdc" },
2306         };
2307
2308         for (i = 0; i < vop_data->win_size; i++) {
2309                 struct vop_win *vop_win = &vop->win[num_wins];
2310                 const struct vop_win_data *win_data = &vop_data->win[i];
2311
2312                 if (!win_data->phy)
2313                         continue;
2314
2315                 vop_win->phy = win_data->phy;
2316                 vop_win->csc = win_data->csc;
2317                 vop_win->offset = win_data->base;
2318                 vop_win->type = win_data->type;
2319                 vop_win->data_formats = win_data->phy->data_formats;
2320                 vop_win->nformats = win_data->phy->nformats;
2321                 vop_win->vop = vop;
2322                 vop_win->win_id = i;
2323                 vop_win->area_id = 0;
2324                 num_wins++;
2325
2326                 for (j = 0; j < win_data->area_size; j++) {
2327                         struct vop_win *vop_area = &vop->win[num_wins];
2328                         const struct vop_win_phy *area = win_data->area[j];
2329
2330                         vop_area->parent = vop_win;
2331                         vop_area->offset = vop_win->offset;
2332                         vop_area->phy = area;
2333                         vop_area->type = DRM_PLANE_TYPE_OVERLAY;
2334                         vop_area->data_formats = vop_win->data_formats;
2335                         vop_area->nformats = vop_win->nformats;
2336                         vop_area->vop = vop;
2337                         vop_area->win_id = i;
2338                         vop_area->area_id = j;
2339                         num_wins++;
2340                 }
2341         }
2342
2343         vop->num_wins = num_wins;
2344
2345         prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
2346                                          "ZPOS", 0, vop->data->win_size);
2347         if (!prop) {
2348                 DRM_ERROR("failed to create zpos property\n");
2349                 return -EINVAL;
2350         }
2351         vop->plane_zpos_prop = prop;
2352
2353         vop->plane_feature_prop = drm_property_create_bitmask(vop->drm_dev,
2354                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2355                                 props, ARRAY_SIZE(props),
2356                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE) |
2357                                 BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA));
2358         if (!vop->plane_feature_prop) {
2359                 DRM_ERROR("failed to create feature property\n");
2360                 return -EINVAL;
2361         }
2362
2363         vop->feature_prop = drm_property_create_bitmask(vop->drm_dev,
2364                                 DRM_MODE_PROP_IMMUTABLE, "FEATURE",
2365                                 crtc_props, ARRAY_SIZE(crtc_props),
2366                                 BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC));
2367         if (!vop->feature_prop) {
2368                 DRM_ERROR("failed to create vop feature property\n");
2369                 return -EINVAL;
2370         }
2371
2372         return 0;
2373 }
2374
2375 /**
2376  * rockchip_drm_wait_line_flag - acqiure the give line flag event
2377  * @crtc: CRTC to enable line flag
2378  * @line_num: interested line number
2379  * @mstimeout: millisecond for timeout
2380  *
2381  * Driver would hold here until the interested line flag interrupt have
2382  * happened or timeout to wait.
2383  *
2384  * Returns:
2385  * Zero on success, negative errno on failure.
2386  */
2387 int rockchip_drm_wait_line_flag(struct drm_crtc *crtc, unsigned int line_num,
2388                                 unsigned int mstimeout)
2389 {
2390         struct vop *vop = to_vop(crtc);
2391         unsigned long jiffies_left;
2392
2393         if (!crtc || !vop->is_enabled)
2394                 return -ENODEV;
2395
2396         if (line_num > crtc->mode.vtotal || mstimeout <= 0)
2397                 return -EINVAL;
2398
2399         if (vop_line_flag_irq_is_enabled(vop))
2400                 return -EBUSY;
2401
2402         reinit_completion(&vop->line_flag_completion);
2403         vop_line_flag_irq_enable(vop, line_num);
2404
2405         jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
2406                                                    msecs_to_jiffies(mstimeout));
2407         vop_line_flag_irq_disable(vop);
2408
2409         if (jiffies_left == 0) {
2410                 dev_err(vop->dev, "Timeout waiting for IRQ\n");
2411                 return -ETIMEDOUT;
2412         }
2413
2414         return 0;
2415 }
2416 EXPORT_SYMBOL(rockchip_drm_wait_line_flag);
2417
2418 static int vop_bind(struct device *dev, struct device *master, void *data)
2419 {
2420         struct platform_device *pdev = to_platform_device(dev);
2421         const struct vop_data *vop_data;
2422         struct drm_device *drm_dev = data;
2423         struct vop *vop;
2424         struct resource *res;
2425         size_t alloc_size;
2426         int ret, irq, i;
2427         int num_wins = 0;
2428
2429         vop_data = of_device_get_match_data(dev);
2430         if (!vop_data)
2431                 return -ENODEV;
2432
2433         for (i = 0; i < vop_data->win_size; i++) {
2434                 const struct vop_win_data *win_data = &vop_data->win[i];
2435
2436                 num_wins += win_data->area_size + 1;
2437         }
2438
2439         /* Allocate vop struct and its vop_win array */
2440         alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
2441         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
2442         if (!vop)
2443                 return -ENOMEM;
2444
2445         vop->dev = dev;
2446         vop->data = vop_data;
2447         vop->drm_dev = drm_dev;
2448         vop->num_wins = num_wins;
2449         dev_set_drvdata(dev, vop);
2450
2451         ret = vop_win_init(vop);
2452         if (ret)
2453                 return ret;
2454
2455         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2456         vop->len = resource_size(res);
2457         vop->regs = devm_ioremap_resource(dev, res);
2458         if (IS_ERR(vop->regs))
2459                 return PTR_ERR(vop->regs);
2460
2461         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
2462         if (!vop->regsbak)
2463                 return -ENOMEM;
2464
2465         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
2466         if (IS_ERR(vop->hclk)) {
2467                 dev_err(vop->dev, "failed to get hclk source\n");
2468                 return PTR_ERR(vop->hclk);
2469         }
2470         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
2471         if (IS_ERR(vop->aclk)) {
2472                 dev_err(vop->dev, "failed to get aclk source\n");
2473                 return PTR_ERR(vop->aclk);
2474         }
2475         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
2476         if (IS_ERR(vop->dclk)) {
2477                 dev_err(vop->dev, "failed to get dclk source\n");
2478                 return PTR_ERR(vop->dclk);
2479         }
2480
2481         irq = platform_get_irq(pdev, 0);
2482         if (irq < 0) {
2483                 dev_err(dev, "cannot find irq for vop\n");
2484                 return irq;
2485         }
2486         vop->irq = (unsigned int)irq;
2487
2488         spin_lock_init(&vop->reg_lock);
2489         spin_lock_init(&vop->irq_lock);
2490
2491         mutex_init(&vop->vsync_mutex);
2492
2493         ret = devm_request_irq(dev, vop->irq, vop_isr,
2494                                IRQF_SHARED, dev_name(dev), vop);
2495         if (ret)
2496                 return ret;
2497
2498         /* IRQ is initially disabled; it gets enabled in power_on */
2499         disable_irq(vop->irq);
2500
2501         ret = vop_create_crtc(vop);
2502         if (ret)
2503                 return ret;
2504
2505         pm_runtime_enable(&pdev->dev);
2506         return 0;
2507 }
2508
2509 static void vop_unbind(struct device *dev, struct device *master, void *data)
2510 {
2511         struct vop *vop = dev_get_drvdata(dev);
2512
2513         pm_runtime_disable(dev);
2514         vop_destroy_crtc(vop);
2515 }
2516
2517 const struct component_ops vop_component_ops = {
2518         .bind = vop_bind,
2519         .unbind = vop_unbind,
2520 };
2521 EXPORT_SYMBOL_GPL(vop_component_ops);