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R600: Remove AMDIL instruction and register definitions
2014-06-13 Tom StellardR600: Remove AMDIL instruction and register definitions
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2014-06-13 Tom StellardR600: Move AMDGPUInstrInfo from AMDGPUTargetMachine...
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2014-06-13 Tom StellardR600: Drop use of cached TargetMachine in R600InstrInfo.cpp
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2014-06-13 Tom StellardR600: Drop use of cached TargetMachine in AMDGPUInstrInfo.cpp
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2014-06-12 Tom StellardRevert "SelectionDAG: Enable (and (setcc x), (setcc...
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2014-06-11 Tom StellardR600: Set correct InstrItinClass for instructions using...
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2014-06-11 Tom StellardR600: BCNT_INT is a vector only instruction
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2014-06-10 Tom StellardR600/SI: Emit an error when attempting to spill VGPRs v4
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2014-06-10 Tom StellardR600/SI: Fix a crash when spilling SGPRs
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2014-06-10 Tom StellardHexagon: Expand i1 SELECT_CC
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2014-06-10 Tom StellardSelectionDAG: Don't use MVT::Other to determine legality...
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2014-06-10 Tom StellardSelectionDAG: Enable (and (setcc x), (setcc y)) ->...
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2014-06-10 Tom StellardSelectionDAG: Expand SELECT_CC to SELECT + SETCC
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2014-05-16 Tom StellardR600/SI: Refactor the VOP3_32 tablegen class
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2014-05-16 Tom StellardR600/SI: Add a PredicateControl class for managing...
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2014-05-16 Tom StellardR600/SI: Move tablegen patterns away from instruction...
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2014-05-16 Tom StellardR600/SI: Remove unused instruction
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2014-05-16 Tom StellardR600/SI: Promote f32 SELECT to i32
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2014-05-16 Tom StellardR600/SI: Remove duplicate pattern
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2014-05-15 Tom Stellardautoconf: Fix libLLVM-Major-Minor-Patch.so symlink
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2014-05-15 Tom StellardR600/SI: Stop using VSrc_* as the default register...
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2014-05-15 Tom StellardR600/SI: Fix a bug with handling of INSERT_SUBREG in...
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2014-05-15 Tom StellardR600/SI: Only use SALU instructions for 64-bit add...
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2014-05-15 Tom StellardR600/SI: Use VALU instructions for i1 ops
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2014-05-13 Tom Stellardautoconf: Fix soname for libLLVM-Major.Minor.so (2nd...
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2014-05-13 Tom StellardRevert "autoconf: Fix soname for libLLVM-Major.Minor.so"
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2014-05-13 Tom Stellardautoconf: Fix soname for libLLVM-Major.Minor.so
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2014-05-09 Tom StellardR600/SI: Teach SIInstrInfo::moveToVALU() how to move...
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2014-05-09 Tom StellardR600/SI: Fix SMRD pattern for offsets > 32 bits
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2014-05-09 Tom StellardR600: Expand i64 SELECT_CC
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2014-05-09 Tom StellardR600: Move MIN/MAX matching from LowerOperation() to...
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2014-05-05 Tom StellardR600: Expand i64 ISD:SUB
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2014-05-02 Tom StellardR600/SI: Add processor type for Mullins.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2014-05-02 Tom StellardR600: Expand vector sin and cos.
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2014-05-02 Tom StellardR600: Expand TruncStore i64 -> {i16,i8}
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2014-05-02 Tom StellardR600/SI: Only create one instruction when spilling...
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2014-04-30 Tom StellardR600/SI: Use VALU instructions for copying i1 values
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2014-04-30 Tom StellardR600/SI: Teach moveToVALU how to handle some SMRD instructions
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2014-04-30 Tom StellardR600: Remove unused function AMDGPUSubtarget::getDefaultSize()
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2014-04-29 Tom StellardR600: Remove duplicate setting of SELECT expansion.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2014-04-29 Tom StellardR600/SI: Custom lower SI_IF and SI_ELSE to avoid machine...
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2014-04-29 Tom StellardR600/SI: Only select SALU instructions in the entry...
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2014-04-29 Tom StellardR600: optimize the UDIVREM 64 algorithm
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2014-04-29 Tom StellardR600: Implement iterative algorithm for udivrem
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2014-04-29 Tom StellardR600: Change UDIV/UREM to UDIVREM when legalizing types
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2014-04-29 Tom StellardR600: remove unused variable
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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2014-04-22 Tom StellardR600/SI: Reorganize SIInstructions.td
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2014-04-18 Tom StellardR600/SI: Use SReg_64 instead of VSrc_64 when selecting...
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2014-04-17 Tom StellardR600: Add comment clariying use of sext for result...
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2014-04-17 Tom StellardR600/SI: Stop using i128 as the resource descriptor...
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2014-04-17 Tom StellardR600/SI: Change default register class for i32 to SReg_32
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2014-04-17 Tom StellardR600/SI: Teach SIInstrInfo::moveToVALU() how to handle...
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2014-04-17 Tom StellardR600/SI: Legalize operands after changing dst reg in...
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2014-04-16 Tom StellardAdded new functionality to LLVM C API to use DiagnosticInfo...
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2014-04-11 Tom StellardSelectionDAG: Use helper function to improve legalization...
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2014-04-11 Tom StellardSelectionDAG: Factor ISD::MUL lowering code out of...
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2014-04-07 Tom StellardR600/SI: Handle INSERT_SUBREG in SIFixSGPRCopies
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2014-04-07 Tom StellardR600: Match 24-bit arithmetic patterns in a Target...
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2014-04-07 Tom StellardR600: Replace dyn_cast + assert with cast
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2014-04-03 Tom StellardR600: Correct opcode for BFE_INT
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2014-04-03 Tom StellardR600/SI: Lower 64-bit immediates using REG_SEQUENCE
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2014-04-02 Tom StellardTargetLibraryInfo: Disable memcpy and memset on R600
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2014-03-31 Tom StellardR600/SI: Implement SIInstrInfo::isTriviallyRematerializable()
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2014-03-31 Tom StellardR600/SI: Lower i64 SELECT by bitcasting to a vector...
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2014-03-31 Tom StellardR600/SI: Return the correct index for VGPRs in getHWRegIndex()
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2014-03-24 Tom StellardR600/SI: Fix warning with gcc 4.8.2
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2014-03-24 Tom StellardR600/SI: Promote fp64 SELECT to i64
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2014-03-24 Tom StellardSelectionDAG: Allow promotion of SELECT nodes from...
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2014-03-24 Tom StellardR600: Reorganize tablegen instruction definitions
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2014-03-21 Tom StellardR600/SI: Handle MUBUF instructions in SIInstrInfo:...
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2014-03-21 Tom StellardR600/SI: Handle S_MOV_B64 in SIInstrInfo::moveToVALU()
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2014-03-21 Tom StellardR600/SI: Use SGPR_(32|64) reg clases when lowering...
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2014-03-21 Tom StellardSink: Don't sink static allocas from the entry block
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2014-03-17 Tom StellardR600/SI: Fix implementation of isInlineConstant() used...
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2014-03-17 Tom StellardR600/SI: Use correct dest register class for V_READFIRSTLANE_B32
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2014-03-17 Tom StellardR600/SI: Add generic checks to SIInstrInfo::verifyInstruction()
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2014-03-13 Tom StellardR600: LDS instructions shouldn't implicitly define...
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2014-03-07 Tom StellardR600/SI: Using SGPRs is illegal for instructions that...
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2014-03-07 Tom StellardR600/SI: Custom lower i1 stores
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2014-03-03 Tom StellardAdd patch level to llvm version in CMake and Autoconf
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2014-02-28 Tom StellardR600: Verify all instructions in the AsmPrinter on...
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2014-02-28 Tom StellardR600/SI: Expand all v16[if]32 operations
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2014-02-25 Tom StellardR600: Don't unconditionally unroll loops with private...
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2014-02-25 Tom StellardR600/SI: Custom select 64-bit ADD
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2014-02-14 Tom StellardTargetLowering: n * r where n > 2 should be an illegal...
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2014-02-13 Tom StellardR600/SI: Expand all v8[if]32 operations
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2014-02-13 Tom StellardR600/SI: Add a pattern for i32 anyext
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2014-02-13 Tom StellardR600/SI: Completely Disable TypeRewriter on compute
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2014-02-13 Tom StellardR600/SI: Split global vector loads with more than 4...
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2014-02-13 Tom StellardR600/SI: Add ShaderType attribute to some tests
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2014-02-10 Tom StellardR600/SI: Initialize M0 and emit S_WQM_B64 whenever...
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2014-02-10 Tom StellardR600/SI: Only use S_WQM_B64 in pixel shaders
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2014-02-06 Tom StellardR600/SI: Add a MUBUF store pattern for Reg+Imm offsets
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2014-02-06 Tom StellardR600/SI: Add a MUBUF store pattern for Imm offsets
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2014-02-06 Tom StellardR600/SI: Add a MUBUF load pattern for Reg+Imm offsets
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2014-02-06 Tom StellardR600/SI: Use immediates offsets for SMRD instructions...
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2014-02-04 Tom StellardR600/SI: Expand i1 BR_CC
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2014-02-04 Tom StellardR600/SI: Don't assume copies will be coalesced in SIFixSGPRC...
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2014-02-04 Tom StellardR600/SI: Custom lower i64 ISD::SELECT
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2014-02-04 Tom StellardR600: Enable vector fpow.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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C/C++ LLVM-based compilers that forbids OOTA behaviors