ARM sched model: Add divsion, loads, branches, vfp cvt
[oota-llvm.git] / lib /
2013-06-05 Arnold SchwaighoferARM sched model: Add divsion, loads, branches, vfp cvt
2013-06-05 Arnold SchwaighoferARMInstrInfo: Improve isSwiftFastImmShift
2013-06-05 Mihai PopaThis is a simple patch that changes RRX and RRXS to...
2013-06-05 David BlaikiePR15662: Optimized debug info produces out of order...
2013-06-05 Tom StellardR600: Make sure to schedule AR register uses and defs...
2013-06-05 Rafael EspindolaDon't print default values for NumberOfAuxSymbols and...
2013-06-05 Rafael EspindolaHandle (at least don't crash on) relocations with no...
2013-06-05 Rafael EspindolaMove BinaryRef to a new include/llvm/Object/YAML.h...
2013-06-05 Rafael EspindolaRevert "R600: Add a pass that merge Vector Register"
2013-06-05 Rafael EspindolaHandle relocations that don't point to symbols.
2013-06-04 Vincent LejeuneR600: Add a pass that merge Vector Register
2013-06-04 Vincent LejeuneR600: Const/Neg/Abs can be folded to dot4
2013-06-04 Evan ChengCortex-R5 can issue Thumb2 integer division instructions.
2013-06-04 Arnold SchwaighoferRevert series of sched model patches until I figure...
2013-06-04 Arnold SchwaighoferARM sched model: Add VFP div instruction on Swift
2013-06-04 Arnold SchwaighoferARM sched model: Add SIMD/VFP load/store instructions...
2013-06-04 Arnold SchwaighoferARM sched model: Add integer VFP/SIMD instructions...
2013-06-04 Arnold SchwaighoferARM sched model: Add integer load/store instructions...
2013-06-04 Arnold SchwaighoferARM sched model: Add integer arithmetic instructions...
2013-06-04 Arnold SchwaighoferARM sched model: Cortex A9 - More InstRW sched resources
2013-06-04 Arnold SchwaighoferARM sched model: Add branch thumb instructions
2013-06-04 Arnold SchwaighoferARM sched model: Add branch thumb2 instructions
2013-06-04 Arnold SchwaighoferARM sched model: Add branch instructions
2013-06-04 Arnold SchwaighoferARM sched model: Add preload thumb2 instructions
2013-06-04 Arnold SchwaighoferARM sched model: Add preload instructions
2013-06-04 Arnold SchwaighoferARM sched model: Add more ALU and CMP thumb instructions
2013-06-04 Arnold Schwaighofer ARM sched model: Add more ALU and CMP thumb2 instructions
2013-06-04 Arnold SchwaighoferARM sched model: Add more ALU and CMP instructions
2013-06-04 Arnold SchwaighoferARM sched model: Add divsion, loads, branches, vfp cvt
2013-06-04 Arnold SchwaighoferARMInstrInfo: Improve isSwiftFastImmShift
2013-06-04 Venkatraman Govind... Sparc: No functionality change. Cleanup whitespaces...
2013-06-04 David MajnemerIndVarSimplify: check if loop invariant expansion can...
2013-06-04 David MajnemerARM: Fix crash in ARM backend inside of ARMConstantIsla...
2013-06-04 Vincent LejeuneR600: Swizzle texture/export instructions
2013-06-04 Rafael EspindolaSecond part of pr16069
2013-06-04 Hans WennborgTypo: s/caes/cases/ in SimplifyCFG
2013-06-04 Benjamin KramerPreserve const correctness.
2013-06-04 Vladimir MedicTest commit for user vmedic, to verify commit access...
2013-06-04 Aaron BallmanSilencing an MSVC warning about mixing bool and unsigne...
2013-06-04 Aaron BallmanSilencing an MSVC warning about */ being found outside...
2013-06-04 Shuxin YangFix a defect in code-layout pass, improving Benchmarks...
2013-06-03 Nick LewyckyDelete dead safety check.
2013-06-03 David MajnemerSimplifyCFG: Do not transform PHI to select if doing...
2013-06-03 David MajnemerSimplifyCFG: Small cleanup, use ICmpInst::isEquality()
2013-06-03 Rafael EspindolaUpdate RuntimeDyldELF::findOPDEntrySection the new...
2013-06-03 Tom StellardR600/SI: Add support for work item and work group intri...
2013-06-03 Tom StellardR600/SI: Add a calling convention for compute shaders
2013-06-03 Tom StellardR600/SI: Custom lower i64 sign_extend
2013-06-03 Tom StellardR600/SI: Adjust some instructions' out register class...
2013-06-03 Tom StellardR600/SI: Handle REG_SEQUENCE in fitsRegClass()
2013-06-03 Tom StellardR600/SI: Handle nodes with glue results correctly SITar...
2013-06-03 Tom StellardR600/SI: Fixup CopyToReg register class in PostprocessI...
2013-06-03 Tom StellardR600/SI: Add support for global loads
2013-06-03 Tom StellardR600/SI: Rework MUBUF store instructions
2013-06-03 Vincent LejeuneR600: 3 op instructions have no write bit but the resul...
2013-06-03 Vincent LejeuneR600: CALL_FS consumes a stack size entry
2013-06-03 Vincent LejeuneR600: use capital letter for PV channel
2013-06-03 Vincent LejeuneR600: Constraints input regs of interp_xy,_zw
2013-06-03 Kostya Serebryany[asan] ASan Linux MIPS32 support (llvm part), patch...
2013-06-03 Ahmed BougachaX86: sub_xmm registers are 128 bits wide.
2013-06-03 Manuel KlimekIntroduce needsCleanup() for APFloat and APInt.
2013-06-03 Venkatraman Govind... Sparc: Add support for indirect branch and blockaddress...
2013-06-03 Rui Ueyama[Object/COFF] Fix Windows .lib name handling.
2013-06-03 Venkatraman Govind... Sparc: When storing 0, use %g0 directly in the store...
2013-06-02 Venkatraman Govind... Sparc: Combine add/or/sethi instruction with restore...
2013-06-02 Venkatraman Govind... Sparc: Perform leaf procedure optimization by default
2013-06-01 Nick LewyckyWhen determining the new index for an insertelement...
2013-06-01 Venkatraman Govind... Sparc: Mark functions calling llvm.vastart and llvm...
2013-06-01 David MajnemerSimplifyCFG: Fix typo in comment for ComputeSpeculationCost
2013-06-01 Benjamin KramerMove getRealLinkageName to a common place and remove...
2013-06-01 Benjamin KramerMove object construction into [] so the temporary can...
2013-06-01 Benjamin KramerAPInt: Simplify code. No functionality change.
2013-06-01 Benjamin KramerAPFloat: Use isDenormal instead of hand-rolled code...
2013-06-01 Tim NorthoverRevert r183069: "TMP: LEA64_32r fixing"
2013-06-01 Tim NorthoverTMP: LEA64_32r fixing
2013-06-01 Tim NorthoverX86: change MOV64ri64i32 into MOV32ri64
2013-06-01 Venkatraman Govind... [Sparc] Generate correct code for leaf functions with...
2013-05-31 Ahmed BougachaMake SubRegIndex size mandatory, following r183020.
2013-05-31 Andrew TrickPrevent loop-unroll from making assumptions about undef...
2013-05-31 Eric ChristopherTemporarily Revert "X86: change MOV64ri64i32 into MOV32...
2013-05-31 Eric ChristopherConst-ify some printing and dumping code for DIEValues.
2013-05-31 Eric ChristopherAdd support for adding the contents of a StringRef...
2013-05-31 Eric ChristopherConvert more unsigned char -> uint8_t.
2013-05-31 Eric ChristopherFix comment.
2013-05-31 Eric ChristopherMove "unsigned char" -> "uint8_t".
2013-05-31 Arnold SchwaighoferLoopVectorize: Change API call to get the backedge...
2013-05-31 Quentin ColombetLoop Strength Reduce: Scaling factor cost.
2013-05-31 Rafael EspindolaRename COFFYaml.h to COFFYAML.h for consistency.
2013-05-31 Rafael EspindolaDon't allocate temporary string for section data.
2013-05-31 Arnold SchwaighoferLoopVectorize: PHIs with only outside users should...
2013-05-31 Benjamin KramerNVPTX: Don't even create a regalloc if we're not going...
2013-05-31 Quentin ColombetModify how the formulae are rated in Loop Strength...
2013-05-31 Ahmed BougachaAdd a way to define the bit range covered by a SubRegIndex.
2013-05-31 Kai NackeRemove useless code from transitioning to new EH scheme
2013-05-31 Tim NorthoverARM: permit upper-case BE/LE on setend instruction
2013-05-31 Tim NorthoverARM: add fstmx and fldmx instructions for assembly
2013-05-31 Rafael EspindolaSimplify multiplications by vectors whose elements...
2013-05-31 Tim NorthoverARM: fix VEXT encoding corner case
2013-05-31 Richard Sandiford[SystemZ] Don't use LOAD and STORE REVERSED for volatil...
2013-05-31 Justin Holewinski[NVPTX] Re-enable support for virtual registers in...
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