/// otherwise.
unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;
- /// \brief Get the bit range covered by a given sub-register index.
- /// In some cases, for instance non-contiguous synthesized indices,
- /// there is no meaningful bit range to get, so return true if \p Offset
- /// and \p Size were set.
- bool getSubRegIdxCoveredBits(unsigned Idx,
- unsigned &Offset, unsigned &Size) const;
+ /// \brief Get the size of the bit range covered by a sub-register index.
+ /// If the index isn't continuous, return the sum of the sizes of its parts.
+ /// If the index is used to access subregisters of different sizes, return -1.
+ unsigned getSubRegIdxSize(unsigned Idx) const;
+
+ /// \brief Get the offset of the bit range covered by a sub-register index.
+ /// If an Offset doesn't make sense (the index isn't continuous, or is used to
+ /// access sub-registers at different offsets), return -1.
+ unsigned getSubRegIdxOffset(unsigned Idx) const;
/// \brief Return the human-readable symbolic target-specific name for the
/// specified physical register.
class RegisterClass; // Forward def
// SubRegIndex - Use instances of SubRegIndex to identify subregisters.
-class SubRegIndex<int size = -1, int offset = 0> {
+class SubRegIndex<int size, int offset = 0> {
string Namespace = "";
// Size - Size (in bits) of the sub-registers represented by this index.
int Size = size;
// Offset - Offset of the first bit that is part of this sub-register index.
+ // Set it to -1 if the same index is used to represent sub-registers that can
+ // be at different offsets (for example when using an index to access an
+ // element in a register tuple).
int Offset = offset;
// ComposedOf - A list of two SubRegIndex instances, [A, B].
// ComposedSubRegIndex - A sub-register that is the result of composing A and B.
// Offset is set to the sum of A and B's Offsets. Size is set to B's Size.
class ComposedSubRegIndex<SubRegIndex A, SubRegIndex B>
- : SubRegIndex<B.Size, -1> {
+ : SubRegIndex<B.Size, !if(!eq(A.Offset, -1), -1,
+ !if(!eq(B.Offset, -1), -1,
+ !add(A.Offset, B.Offset)))> {
// See SubRegIndex.
let ComposedOf = [A, B];
}
return 0;
}
-bool MCRegisterInfo::getSubRegIdxCoveredBits(unsigned Idx, unsigned &Offset,
- unsigned &Size) const {
+unsigned MCRegisterInfo::getSubRegIdxSize(unsigned Idx) const {
assert(Idx && Idx < getNumSubRegIndices() &&
"This is not a subregister index");
- // Get a pointer to the corresponding SubRegIdxRanges struct.
- const SubRegCoveredBits *Bits = &SubRegIdxRanges[Idx];
- if (Bits->Offset == (uint16_t)-1 || Bits->Size == (uint16_t)-1)
- return false;
- Offset = Bits->Offset;
- Size = Bits->Size;
- return true;
+ return SubRegIdxRanges[Idx].Size;
+}
+
+unsigned MCRegisterInfo::getSubRegIdxOffset(unsigned Idx) const {
+ assert(Idx && Idx < getNumSubRegIndices() &&
+ "This is not a subregister index");
+ return SubRegIdxRanges[Idx].Offset;
}
int MCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
//===----------------------------------------------------------------------===//
let Namespace = "AArch64" in {
-def sub_128 : SubRegIndex;
-def sub_64 : SubRegIndex;
-def sub_32 : SubRegIndex;
-def sub_16 : SubRegIndex;
-def sub_8 : SubRegIndex;
+def sub_128 : SubRegIndex<128>;
+def sub_64 : SubRegIndex<64>;
+def sub_32 : SubRegIndex<32>;
+def sub_16 : SubRegIndex<16>;
+def sub_8 : SubRegIndex<8>;
// The VPR registers are handled as sub-registers of FPR equivalents, but
// they're really the same thing. We give this concept a special index.
-def sub_alias : SubRegIndex;
+def sub_alias : SubRegIndex<128>;
}
// Registers are identified with 5-bit ID numbers.
let Aliases = [R];
}
- def subreg_loreg : SubRegIndex;
- def subreg_hireg : SubRegIndex;
+ def subreg_loreg : SubRegIndex<32>;
+ def subreg_hireg : SubRegIndex<32, 32>;
// Integer registers.
def R0 : Ri< 0, "r0">, DwarfRegNum<[0]>;
def R14B : MSP430Reg<14, "r14">;
def R15B : MSP430Reg<15, "r15">;
-def subreg_8bit : SubRegIndex { let Namespace = "MSP430"; }
+def subreg_8bit : SubRegIndex<8> { let Namespace = "MSP430"; }
let SubRegIndices = [subreg_8bit] in {
def PCW : MSP430RegWithSubregs<0, "r0", [PCB]>;
// Declarations that describe the MIPS register file
//===----------------------------------------------------------------------===//
let Namespace = "Mips" in {
-def sub_fpeven : SubRegIndex;
-def sub_fpodd : SubRegIndex;
-def sub_32 : SubRegIndex;
-def sub_lo : SubRegIndex;
-def sub_hi : SubRegIndex;
-def sub_dsp16_19 : SubRegIndex;
-def sub_dsp20 : SubRegIndex;
-def sub_dsp21 : SubRegIndex;
-def sub_dsp22 : SubRegIndex;
-def sub_dsp23 : SubRegIndex;
+def sub_fpeven : SubRegIndex<32>;
+def sub_fpodd : SubRegIndex<32, 32>;
+def sub_32 : SubRegIndex<32>;
+def sub_lo : SubRegIndex<32>;
+def sub_hi : SubRegIndex<32, 32>;
+def sub_dsp16_19 : SubRegIndex<4, 16>;
+def sub_dsp20 : SubRegIndex<1, 20>;
+def sub_dsp21 : SubRegIndex<1, 21>;
+def sub_dsp22 : SubRegIndex<1, 22>;
+def sub_dsp23 : SubRegIndex<1, 23>;
}
class Unallocatable {
//===----------------------------------------------------------------------===//
let Namespace = "PPC" in {
-def sub_lt : SubRegIndex;
-def sub_gt : SubRegIndex;
-def sub_eq : SubRegIndex;
-def sub_un : SubRegIndex;
-def sub_32 : SubRegIndex;
+def sub_lt : SubRegIndex<1>;
+def sub_gt : SubRegIndex<1, 1>;
+def sub_eq : SubRegIndex<1, 2>;
+def sub_un : SubRegIndex<1, 3>;
+def sub_32 : SubRegIndex<32>;
}
let Namespace = "AMDGPU" in {
foreach Index = 0-15 in {
- def sub#Index : SubRegIndex;
+ // Indices are used in a variety of ways here, so don't set a size/offset.
+ def sub#Index : SubRegIndex<-1, -1>;
}
def INDIRECT_BASE_ADDR : Register <"INDIRECT_BASE_ADDR">;
}
let Namespace = "SP" in {
-def sub_even : SubRegIndex;
-def sub_odd : SubRegIndex;
+def sub_even : SubRegIndex<32>;
+def sub_odd : SubRegIndex<32, 32>;
}
// Registers are identified with 5-bit ID numbers.
}
let Namespace = "SystemZ" in {
-def subreg_32bit : SubRegIndex; // could also be known as "subreg_high32"
-def subreg_high : SubRegIndex;
-def subreg_low : SubRegIndex;
+def subreg_32bit : SubRegIndex<32>; // could also be named "subreg_high32"
+// Indices are used in a variety of ways, so don't set an Offset.
+def subreg_high : SubRegIndex<64, -1>;
+def subreg_low : SubRegIndex<64, -1>;
def subreg_low32 : ComposedSubRegIndex<subreg_low, subreg_32bit>;
}
// None exists, synthesize one.
std::string Name = Parts.front()->getName();
+ // Determine whether all parts are contiguous.
+ bool isContinuous = true;
+ unsigned Size = Parts.front()->Size;
+ unsigned LastOffset = Parts.front()->Offset;
+ unsigned LastSize = Parts.front()->Size;
for (unsigned i = 1, e = Parts.size(); i != e; ++i) {
Name += '_';
Name += Parts[i]->getName();
+ Size += Parts[i]->Size;
+ if (Parts[i]->Offset != (LastOffset + LastSize))
+ isContinuous = false;
+ LastOffset = Parts[i]->Offset;
+ LastSize = Parts[i]->Size;
}
- return Idx = createSubRegIndex(Name, Parts.front()->getNamespace());
+ Idx = createSubRegIndex(Name, Parts.front()->getNamespace());
+ Idx->Size = Size;
+ Idx->Offset = isContinuous ? Parts.front()->Offset : -1;
+ return Idx;
}
void CodeGenRegBank::computeComposites() {
Record *const TheDef;
std::string Name;
std::string Namespace;
- uint16_t Size;
- uint16_t Offset;
public:
+ uint16_t Size;
+ uint16_t Offset;
const unsigned EnumValue;
unsigned LaneMask;
const std::string &getName() const { return Name; }
const std::string &getNamespace() const { return Namespace; }
std::string getQualifiedName() const;
- uint16_t getSize() const { return Size; }
- uint16_t getOffset() const { return Offset; }
// Order CodeGenSubRegIndex pointers by EnumValue.
struct Less {
for (ArrayRef<CodeGenSubRegIndex*>::const_iterator
SRI = SubRegIndices.begin(), SRE = SubRegIndices.end();
SRI != SRE; ++SRI) {
- OS << " { " << (*SRI)->getOffset() << ", "
- << (*SRI)->getSize()
+ OS << " { " << (*SRI)->Offset << ", "
+ << (*SRI)->Size
<< " },\t// " << (*SRI)->getName() << "\n";
}
OS << "};\n\n";
projects / oota-llvm.git / commitdiff