[Sparc] Disable tail call optimization for sparc64.
[oota-llvm.git] / lib / Target / R600 /
2013-10-08 Rafael EspindolaAdd a MCTargetStreamer interface.
2013-10-02 Vincent LejeuneR600: Add a ldptr intrinsic to support MSAA.
2013-10-01 Vincent LejeuneR600: add a pass that merges clauses.
2013-10-01 Vincent LejeuneR600: Put PRED_X instruction in its own clause
2013-10-01 Vincent LejeuneR600: Enable -verify-machineinstrs in some tests.
2013-09-30 Arnold SchwaighoferIfConverter: Use TargetSchedule for instruction latencies
2013-09-28 Robert WilhelmEven more spelling fixes for "instruction".
2013-09-28 Tom StellardR600: Fix handling of NAN in comparison instructions
2013-09-28 Tom StellardSelectionDAG: Improve legalization of SELECT_CC with...
2013-09-28 Tom StellardSelectionDAG: Try to expand all condition codes using...
2013-09-25 David MajnemerMC: Remove vestigial PCSymbol field from AsmInfo
2013-09-22 Tim NorthoverISelDAG: spot chain cycles involving MachineNodes
2013-09-20 Andrew TrickAllow subtarget selection of the default MachineSchedul...
2013-09-12 Vincent LejeuneR600: Move clamp handling code to R600IselLowering.cpp
2013-09-12 Vincent LejeuneR600: Move code handling literal folding into R600ISelL...
2013-09-12 Vincent LejeuneR600: Move fabs/fneg/sel folding logic into PostProcessIsel
2013-09-12 Tom StellardR600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL trans...
2013-09-12 Tom StellardR600: Don't use trans slot for instructions that read...
2013-09-09 Bill WendlingGenerate compact unwind encoding from CFI directives.
2013-09-06 Aaron WatryR600: Add support for LDS atomic subtract
2013-09-05 Tom StellardR600: Coding style
2013-09-05 Matt ArsenaultR600: Fix i64 to i32 trunc on SI
2013-09-05 Tom StellardR600: Add support for local memory atomic add
2013-09-05 Tom StellardR600: Expand SELECT nodes rather than custom lowering...
2013-09-05 Tom StellardR600: Fix incorrect LDS size calculation
2013-09-05 Tom StellardR600/SI: Don't emit S_WQM_B64 instruction for compute...
2013-09-05 Tom StellardR600: Fix segfault in R600TextureIntrinsicReplacer
2013-09-04 Vincent LejeuneR600: Use shared op optimization when checking cycle...
2013-09-04 Vincent LejeuneR600: Non vector only instruction can be scheduled...
2013-09-04 Vincent LejeuneR600: Use SchedModel enum for is{Trans,Vector}Only...
2013-09-04 Michael GottesmanAdd llvm namespace to llvm::next.
2013-09-04 Michael GottesmanUse llvm::next() instead of incrementing begin iterator...
2013-08-31 Benjamin KramerMark an unreachable code path with llvm_unreachable...
2013-08-26 Tom StellardR600: Add support for vector local memory loads
2013-08-26 Tom StellardR600: Add support for i8 and i16 local memory loads
2013-08-26 Tom StellardR600: Add support for i8 and i16 local memory stores
2013-08-26 Tom StellardR600: Add support for v4i32 and v2i32 local stores
2013-08-26 Tom StellardSelectionDAG: Use correct pointer size when lowering...
2013-08-22 Tom StellardR600/SI: Fix another case of illegal VGPR to SGPR copy
2013-08-21 Tom StellardR600: Remove unnecessary casts
2013-08-18 Dmitri GribenkoRemove unused stdio.h includes
2013-08-17 Tom StellardR600: Fix possible use of an uninitialized variable
2013-08-16 Tom StellardR600: Expand vector FRINT ops
2013-08-16 Tom StellardR600: Expand vector FFLOOR ops
2013-08-16 Tom StellardR600: Expand vector float operations for both SI and...
2013-08-16 Michel DanzerR600/SI: Add pattern for xor of i1
2013-08-16 Michel DanzerR600/SI: Fix broken encoding of DS_WRITE_B32
2013-08-16 Benjamin KramerR600: Allocate memoperand in the MachienFunction so...
2013-08-16 Tom StellardRevert "R600/SI: Fix incorrect encoding of DS_WRITE_B32...
2013-08-16 Tom StellardR600/SI: Fix incorrect encoding of DS_WRITE_B32 instruc...
2013-08-16 Tom StellardR600: Add support for global vector loads with element...
2013-08-16 Tom StellardR600: Add support for global vector stores with element...
2013-08-16 Tom StellardR600: Add support for i16 and i8 global stores
2013-08-16 Tom StellardR600: Add support for v4i32 stores on Cayman
2013-08-16 Tom StellardR600: Enable folding of inline literals into REQ_SEQUEN...
2013-08-16 Tom StellardR600: Add IsExport bit to TableGen instruction definitions
2013-08-16 Tom StellardR600: Change the RAT instruction assembly names so...
2013-08-15 Matt ArsenaultFix spelling
2013-08-15 Alexey SamsonovTentative fix for global-buffer-overflow caused by...
2013-08-14 Tom StellardR600/SI: Improve legalization of vector operations
2013-08-14 Tom StellardR600/SI: Replace v1i32 type with i32 in imageload and...
2013-08-14 Tom StellardR600/SI: Convert v16i8 resource descriptors to i128
2013-08-14 Tom StellardR600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2
2013-08-14 Tom StellardR600/SI: Choose the correct MOV instruction for copying...
2013-08-14 Tom StellardR600/SI: Assign a register class to the $vaddr operand...
2013-08-14 Tom StellardR600/SI: Handle MSAA texture targets
2013-08-14 Tom StellardR600/SI: Allow conversion between v32i8 and v8i32
2013-08-14 Tom StellardR600/SI: Fix an obvious typo
2013-08-14 Tom StellardR600/SI: Add pattern for fp_to_uint
2013-08-12 Tom StellardR600: Set scheduling preference to Sched::Source
2013-08-10 Niels Ole SalscheiderR600/SI: FMA is faster than fmul and fadd for f64
2013-08-10 Niels Ole SalscheiderR600/SI: Add FMA pattern
2013-08-08 Niels Ole SalscheiderR600/SI: Implement fp32<->fp64 conversions
2013-08-08 Niels Ole SalscheiderR600/SI: Implement sint<->fp64 conversions
2013-08-07 Evgeniy StepanovInitialize SIInsertWaits::ExpInstrTypesSeen in the...
2013-08-06 Tom StellardR600: Add new file from r187831 to CMakeLists.txt
2013-08-06 Tom StellardR600/SI: Use VSrc_* register classes as the default...
2013-08-06 Tom StellardR600/SI: Add more special cases for opcodes to ensureSR...
2013-08-06 NAKAMURA TakumiTarget/*/CMakeLists.txt: Add the dependency to CommonTa...
2013-08-06 Tom StellardFactor FlattenCFG out from SimplifyCFG
2013-08-05 Tom StellardR600: Implement TargetLowering::getVectorIdxTy()
2013-08-01 Tom StellardR600: Add 64-bit float load/store support
2013-08-01 Tom StellardR600: Use 64-bit alignment for 64-bit kernel arguments
2013-08-01 Tom StellardR600/SI: Custom lower i64 ZERO_EXTEND
2013-07-31 Tom StellardRevert "R600: Non vector only instruction can be schedu...
2013-07-31 Tom StellardRevert "R600: Use SchedModel enum for is{Trans,Vector...
2013-07-31 Vincent LejeuneR600: Do not mergevector after a vector reg is used
2013-07-31 Vincent LejeuneR600: Avoid more than 4 literals in the same instructio...
2013-07-31 Vincent LejeuneR600: Non vector only instruction can be scheduled...
2013-07-31 Vincent LejeuneR600: Don't mix LDS and non-LDS instructions in the...
2013-07-31 Vincent LejeuneR600: Use SchedModel enum for is{Trans,Vector}Only...
2013-07-31 Vincent LejeuneR600: Remove predicated_break inst
2013-07-30 Tom StellardR600/SI: Expand vector fp <-> int conversions
2013-07-30 Quentin Colombet[R600] Replicate old DAGCombiner behavior in target...
2013-07-27 Tom StellardSimplifyCFG: Use parallel-and and parallel-or mode...
2013-07-23 Tom StellardDAGCombiner: Pass the correct type to TargetLowering...
2013-07-23 Tom StellardR600: Treat CONSTANT_ADDRESS loads like GLOBAL_ADDRESS...
2013-07-23 Tom StellardR600: Add support for 24-bit MAD instructions
2013-07-23 Tom StellardR600: Add support for 24-bit MUL instructions
2013-07-23 Tom StellardR600: Improve support for < 32-bit loads
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