Add some more .gitignore entries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121968 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a bug in the loop in JumpThreading::ProcessThreadableEdges() where it could falsely produce a MultipleDestSentinel value if the first predecessor ended with an 'indirectbr'. If that happened, it caused an unnecessary FindMostPopularDest() call.
This wasn't a correctness problem, but it broke the fast path for single-predecessor blocks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121966 91177308-0d34-0410-b5e6-96231b3b80d8

Speculatively revert commit 121905 since it looks like it might have broken the
dragonegg self-host buildbot.  Original commit message:

Add an InstCombine transform to recognize instances of manual overflow-safe addition
(performing the addition in a wider type and explicitly checking for overflow), and
fold them down to intrinsics.  This currently only supports signed-addition, but could
be generalized if someone works out the magic constant formulas for other operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121965 91177308-0d34-0410-b5e6-96231b3b80d8

Fix some compiler warnings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121959 91177308-0d34-0410-b5e6-96231b3b80d8

MemoryBuffer now return an error_code and returns a OwningPtr<MemoryBuffer> via an out parm.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121958 91177308-0d34-0410-b5e6-96231b3b80d8

Add .gitignore. I chose not to dump the svn ignore list into this because most
of the entries there are useless for out of source builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121955 91177308-0d34-0410-b5e6-96231b3b80d8

MC: Move target specific fixup info descriptors to TargetAsmBackend instead of
the MCCodeEmitter, which seems like a better organization.
 - Also, cleaned up some magic constants while in the area.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121953 91177308-0d34-0410-b5e6-96231b3b80d8

1. ARM/MC/ELF: A few more ELF relocs for .o
2. Fixed EmitLocalCommonSymbol for ELF (Yes, they exist. :)
   Test added.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121951 91177308-0d34-0410-b5e6-96231b3b80d8

MC: Make TargetAsmBackend available to the AsmStreamer.
 - Treaty talks on the non-proliferation of MC objects broke down.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121949 91177308-0d34-0410-b5e6-96231b3b80d8

MC: Split MCFixupKindInfo out into its own header.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121948 91177308-0d34-0410-b5e6-96231b3b80d8

MC: Remove a FIXME I no longer agree with.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121947 91177308-0d34-0410-b5e6-96231b3b80d8

Update a comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121946 91177308-0d34-0410-b5e6-96231b3b80d8

-enable-tbaa is on by default now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121945 91177308-0d34-0410-b5e6-96231b3b80d8

Make memcpyopt TBAA-aware.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121944 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Support/regexec.c: Let Regex LLP64-aware.

On LLP64 Win64, 'states1' (for small version) was expanded to 'char *' for large version. Thus small version would be mischosen when nstates > 32 regardless of sizeof(long) on Win64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121942 91177308-0d34-0410-b5e6-96231b3b80d8

Delete an extra "Imm5 = ", caught by GCC's -Wsequence-point but not by Clang
(see PR4579).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121939 91177308-0d34-0410-b5e6-96231b3b80d8

Add IntervalMapOverlaps - An iterator for overlapping intervals in two
IntervalMaps.

The IntervalMaps can have different template parameters, but the KeyT and Traits
types must be the same.

Tests are forthcoming.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121935 91177308-0d34-0410-b5e6-96231b3b80d8

Remove fixup_arm_thumb_ldst. The code was never calling the "fixup" stuff for
it. I.e., it was always an immediate value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121932 91177308-0d34-0410-b5e6-96231b3b80d8

Add tSpill and tRestore to the opcodes to replace with tSTRi and tLDRi
respectively.

It may be a bug that these opcodes are getting this far into machine code
generation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121931 91177308-0d34-0410-b5e6-96231b3b80d8

Add encodings for Thumb1 Spill and Restore pseudos.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121929 91177308-0d34-0410-b5e6-96231b3b80d8

Fix elf-dump --dump-section-data for .bss section

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121927 91177308-0d34-0410-b5e6-96231b3b80d8

Enable TBAA by default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121923 91177308-0d34-0410-b5e6-96231b3b80d8

Preserve TBAA tags when doing load PRE.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121921 91177308-0d34-0410-b5e6-96231b3b80d8

Thumb1 had two patterns for the same load-from-constant-pool instruction.
Canonicalize on tLDRpci and remove tLDRcp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121920 91177308-0d34-0410-b5e6-96231b3b80d8

Don't handle -arm-long-calls in fast isel for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121919 91177308-0d34-0410-b5e6-96231b3b80d8

Start using SplitKit and MachineLoopRanges in RegAllocGreedy in preparation of
live range splitting around loops guided by register pressure.

So far, trySplit() simply prints a lot of debug output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121918 91177308-0d34-0410-b5e6-96231b3b80d8

Add MachineLoopRanges analysis.

A MachineLoopRange contains the intervals of slot indexes covered by the blocks
in a loop. This representation of the loop blocks is more efficient to compare
against interfering registers during register coalescing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121917 91177308-0d34-0410-b5e6-96231b3b80d8

If we're changing the frame register to a physical register other than SP, we
need to use tLDRi and tSTRi instead of tLDRspi and tSTRspi respectively.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121915 91177308-0d34-0410-b5e6-96231b3b80d8

Whitespace cleanups.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121914 91177308-0d34-0410-b5e6-96231b3b80d8

Teach the Neon intrinsic generator to widen half-precision float types.
This isn't currently used for anything but I ran into it when experimenting
with some changes, and it might be useful in the future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121911 91177308-0d34-0410-b5e6-96231b3b80d8

Better fix for opt build

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121910 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a typo that Bill spotted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121909 91177308-0d34-0410-b5e6-96231b3b80d8

Only rr forms of ADD*_DB are commutable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121908 91177308-0d34-0410-b5e6-96231b3b80d8

Typo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121906 91177308-0d34-0410-b5e6-96231b3b80d8

Add an InstCombine transform to recognize instances of manual overflow-safe addition
(performing the addition in a wider type and explicitly checking for overflow), and
fold them down to intrinsics.  This currently only supports signed-addition, but could
be generalized if someone works out the magic constant formulas for other operations.

Fixes <rdar://problem/8558713>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121905 91177308-0d34-0410-b5e6-96231b3b80d8

Fix opt -Werror build

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121904 91177308-0d34-0410-b5e6-96231b3b80d8

Teach machine cse to commute instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121903 91177308-0d34-0410-b5e6-96231b3b80d8

Add Neon VCVT instructions for f32 <-> f16 conversions.
Clang is now providing intrinsics for these and so we need to support them
in the backend.  Radar 8068427.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121902 91177308-0d34-0410-b5e6-96231b3b80d8

Fix misspelled target triples in MC/ARM test commands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121901 91177308-0d34-0410-b5e6-96231b3b80d8

Reapply r121886, and also update DecomposeGEPExpression to keep
it in sync.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121895 91177308-0d34-0410-b5e6-96231b3b80d8

Add SlotIndexes::getMBBRange() to get the range of a basic block in a single
lookup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121893 91177308-0d34-0410-b5e6-96231b3b80d8

Revert r121886. DecomposeGEPExpression needs to be kept
in sync.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121892 91177308-0d34-0410-b5e6-96231b3b80d8

Lower the MBlaze target specific calling conventions for "interrupt_handler"
and "save_volatiles" correctly. This completes the custom calling convention
functionality changes for the MBlaze backend that were started in 121888.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121891 91177308-0d34-0410-b5e6-96231b3b80d8

Adding target specific calling conventions to support the MBlaze GCC function
attributes "interrupt_handle" and "save_volatiles". Support for lowering these
correctly will be in an upcoming commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121888 91177308-0d34-0410-b5e6-96231b3b80d8

Strengthen GetUnderlyingObject using InstructionSimplify.

While LLVM's main design is that analysis code shouldn't
go out of its way to understand code which hasn't been
InstCombined, analysis utility routines like this can
find themselves being called in the middle of transform
passes when instcombine hasn't had a chance to run.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121886 91177308-0d34-0410-b5e6-96231b3b80d8

Move Value::getUnderlyingObject to be a standalone
function so that it can live in Analysis instead of
VMCore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121885 91177308-0d34-0410-b5e6-96231b3b80d8

Add some special purpose register definitions to the MBlaze backend and cleanup some old, unused floating point register definitions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121882 91177308-0d34-0410-b5e6-96231b3b80d8

Fix typo in r121875.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121880 91177308-0d34-0410-b5e6-96231b3b80d8

Tweak a few pseudo-inst pattern base classes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121878 91177308-0d34-0410-b5e6-96231b3b80d8

Clean up some of LVI:
 * mergeIn now uses constant folding for constants that are provably not-equal.
 * sink some sanity checks from the get*() methods into the mark*() methods, to ensure that we never have a constant/notconstant ConstantInt
 * some textual cleanups, whitespace changes, removing "else" after return, that sort of thing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121877 91177308-0d34-0410-b5e6-96231b3b80d8

The new t2LEApcrel* pseudo instructions need the size specified.
rdar://8768390

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121876 91177308-0d34-0410-b5e6-96231b3b80d8

Implement cleanups suggested by Daniel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121875 91177308-0d34-0410-b5e6-96231b3b80d8

Document some more AliasAnalysis infrastructure limitations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121874 91177308-0d34-0410-b5e6-96231b3b80d8

Fix build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121872 91177308-0d34-0410-b5e6-96231b3b80d8

Detect and enumerate bypass loops.

Bypass loops have the current live range live through, but contain no uses or
defs. Splitting around a bypass loop can free registers for other uses inside
the loop by spilling the split range.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121871 91177308-0d34-0410-b5e6-96231b3b80d8

Separate SplitAnalysis::getSplitLoops().

This method returns the set of loops with uses that are candidates for
splitting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121870 91177308-0d34-0410-b5e6-96231b3b80d8

Add a Neon intrinsic test generator.
This is still a WIP.  It's already good enough to expose a few bugs, though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121868 91177308-0d34-0410-b5e6-96231b3b80d8

Fix Neon intrinsic immediate range checking for some double-register operands.
Some quad-register intrinsics with lane operands only take a double-register
operand for the vector containing the lane.  The valid range of lane numbers
is then half as big as you would expect from the quad-register type.
Note: This currently has no effect because those intrinsics are now handled
entirely in the header file using __builtin_shufflevector, which does its own
range checking, but I want to use this for generating tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121867 91177308-0d34-0410-b5e6-96231b3b80d8

Move Sub simplifications and additional Add simplifications out of
instcombine and into InstructionSimplify.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121861 91177308-0d34-0410-b5e6-96231b3b80d8

If we detect that the instruction we are simplifying is unreachable, arrange for
it to be replaced by undef rather than not replaced at all, the idea being that
this may reduce the amount of work done by whoever called InstructionSimplify.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121860 91177308-0d34-0410-b5e6-96231b3b80d8

Teach jump threading to "look through" a select when the branch direction of a terminator depends on it.
When it sees a promising select it now tries to figure out whether the condition of the select is known in any of the predecessors and if so it maps the operands appropriately.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121859 91177308-0d34-0410-b5e6-96231b3b80d8

Add fixups for Thumb LDR/STR instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121858 91177308-0d34-0410-b5e6-96231b3b80d8

Relax alignment fragments.

With this we don't need the EffectiveSize field anymore. Without that field
LayoutFragment only updates offsets and we don't need to invalidate the
current fragment when it is relaxed (only the ones following it).

This is also a very small improvement in the accuracy of the layout info as
we now use the after relaxation size immediately.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121857 91177308-0d34-0410-b5e6-96231b3b80d8

Patch by David Meyer to avoid a O(N^2) behaviour when relaxing fragments.

Since we now don't update addresses so early, we might relax a bit more than
we need to. This is simillar to the issue in PR8467.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121856 91177308-0d34-0410-b5e6-96231b3b80d8

add another overflow idiom

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121854 91177308-0d34-0410-b5e6-96231b3b80d8

add a note about overflow idiom recognition.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121853 91177308-0d34-0410-b5e6-96231b3b80d8

Generalize an assert.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121851 91177308-0d34-0410-b5e6-96231b3b80d8

add a shift/imul missed optimization

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121850 91177308-0d34-0410-b5e6-96231b3b80d8

add a note about a SPEC hack that gcc mainline does.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121849 91177308-0d34-0410-b5e6-96231b3b80d8

take care of some todos, transforming [us]mul_lohi into
a wider mul if the wider mul is legal.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121848 91177308-0d34-0410-b5e6-96231b3b80d8

merge two tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121847 91177308-0d34-0410-b5e6-96231b3b80d8

when transforming a MULHS into a wider MUL, there is no need to SRA the
result, the top bits are truncated off anyway, just use SRL.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121846 91177308-0d34-0410-b5e6-96231b3b80d8

make qsort predicate more conformant by returning 0 for equal values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121838 91177308-0d34-0410-b5e6-96231b3b80d8

various cleanups to tblgen, patch by Garrison Venn!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121837 91177308-0d34-0410-b5e6-96231b3b80d8

Add mention that we support FreeBSD/amd64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121832 91177308-0d34-0410-b5e6-96231b3b80d8

Add some more MC tests for ARM arithmetic instructions that update or don't
update the condition codes.  These come from my test generator and are just
the ones that MC currently assembles correctly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121830 91177308-0d34-0410-b5e6-96231b3b80d8

Copy-pastos.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121829 91177308-0d34-0410-b5e6-96231b3b80d8

Remove ConvertToMAttrImpl, it became too '-march'-specific.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121828 91177308-0d34-0410-b5e6-96231b3b80d8

llvmc: Support -march arguments that should be forwarded to llc as -mcpu.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121827 91177308-0d34-0410-b5e6-96231b3b80d8

llvmc: Better -mfpu/-mcpu support for ARM & PPC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121826 91177308-0d34-0410-b5e6-96231b3b80d8

llvmc: more complete -march table for ARM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121825 91177308-0d34-0410-b5e6-96231b3b80d8

llvmc: Support -mabi/-mfloat-abi.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121824 91177308-0d34-0410-b5e6-96231b3b80d8

llvmc: Forward -march/-mcpu/-mtune to as & ld.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121823 91177308-0d34-0410-b5e6-96231b3b80d8

llvmc: make switch options ZeroOrMore by default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121822 91177308-0d34-0410-b5e6-96231b3b80d8

Reapply r121808 now that the missing patterns have been supplied.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121820 91177308-0d34-0410-b5e6-96231b3b80d8

Add some missing patterns now that tLDRB and tLDRH are split into reg and
immediate versions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121819 91177308-0d34-0410-b5e6-96231b3b80d8

Fix PR8790, another instance where unreachable code can cause instruction simplification to fail,
this case involve a select that simplifies to itself.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121817 91177308-0d34-0410-b5e6-96231b3b80d8

Cleanup trailing whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121816 91177308-0d34-0410-b5e6-96231b3b80d8

Revert r121808 until I can fix the build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121815 91177308-0d34-0410-b5e6-96231b3b80d8

thumb adr fixup needs alignment just like the t2 version.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121812 91177308-0d34-0410-b5e6-96231b3b80d8

Comments and cleaning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121809 91177308-0d34-0410-b5e6-96231b3b80d8

Make the ISel selections for LDR/STR the same as before the LDRr/LDRi split. In
particular, we want

   ldr r2, [r3]

to be equivalent to

   ldr r2, [r3, #0]

and not

   ldr r2, [r3, r0]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121808 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify RegAllocGreedy's use of register aliases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121807 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify CCState's use of register aliases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121806 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify AggressiveAntiDepBreaker's use of register aliases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121805 91177308-0d34-0410-b5e6-96231b3b80d8

Simplyfy RegAllocBasic by using getOverlaps instead of getAliasSet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121801 91177308-0d34-0410-b5e6-96231b3b80d8

Introduce TargetRegisterInfo::getOverlaps(Reg), returning a list of all
registers that alias Reg, including itself. This is almost the same as the
existing getAliasSet() method, except for the inclusion of Reg.

The name matches the reflexive TRI::regsOverlap(x, y) relation.

It is very common to do stuff to a register and all its aliases:

  stuff(Reg)
  for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias)
    stuff(*Alias);

That can now be written as the simpler:

  for (const unsigned *Alias = TRI->getOverlaps(Reg); *Alias; ++Alias)
    stuff(*Alias);

This change requires a bit more constant space for the alias lists because Reg
is included and because the empty alias list cannot be shared any longer.

If the getAliasSet method is eventually removed, this space can be reclaimed by
sharing overlap lists. For instance, %rax and %eax have identical overlap sets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121800 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121798 91177308-0d34-0410-b5e6-96231b3b80d8

Fix comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121797 91177308-0d34-0410-b5e6-96231b3b80d8

Multiclassify the LDR/STR encoding patterns. The only functionality difference
is the addition of the FoldableAsLoad & Rematerializable flags to some of the
load instructions. ARM has these flags set for them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121794 91177308-0d34-0410-b5e6-96231b3b80d8