when transforming a MULHS into a wider MUL, there is no need to SRA the

result, the top bits are truncated off anyway, just use SRL.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121846 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 740b29b57a1c1ea8c073947508d3d1840b737a7e..6f0c167d8527bff5bdc89e67fc8a462d87073d6e 100644 (file)
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -1940,7 +1940,7 @@ SDValue DAGCombiner::visitMULHS(SDNode *N) {
       N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
       N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
       N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
-      N1 = DAG.getNode(ISD::SRA, DL, NewVT, N1,
+      N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
                        DAG.getConstant(SimpleSize, getShiftAmountTy()));
       return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
     }