From: Chris Lattner <sabre@nondot.org>
Date: Wed, 15 Dec 2010 05:51:39 +0000 (+0000)
Subject: when transforming a MULHS into a wider MUL, there is no need to SRA the
X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=commitdiff_plain;h=1a0fbe2cf438ac2788df669284293789681424e1

when transforming a MULHS into a wider MUL, there is no need to SRA the
result, the top bits are truncated off anyway, just use SRL.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121846 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 740b29b57a1..6f0c167d852 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -1940,7 +1940,7 @@ SDValue DAGCombiner::visitMULHS(SDNode *N) {
       N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
       N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
       N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
-      N1 = DAG.getNode(ISD::SRA, DL, NewVT, N1,
+      N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
                        DAG.getConstant(SimpleSize, getShiftAmountTy()));
       return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
     }