list<Predicate> Predicates = [IsThumb];
}
+// PseudoInst that's Thumb2-mode only.
+class t2PseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin,
+ list<dag> pattern>
+ : PseudoInst<oops, iops, itin, pattern> {
+ let SZ = sz;
+ list<Predicate> Predicates = [IsThumb2];
+}
// Almost all ARM instructions are predicable.
class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
IndexMode im, Format f, InstrItinClass itin,
}
let neverHasSideEffects = 1, isReMaterializable = 1 in
-def t2LEApcrel : PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
- IIC_iALUi, []>;
-def t2LEApcrelJT : PseudoInst<(outs rGPR:$Rd),
- (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
- []>;
+def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
+ Size4Bytes, IIC_iALUi, []>;
+def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
+ (ins i32imm:$label, nohash_imm:$id, pred:$p),
+ Size4Bytes, IIC_iALUi,
+ []>;
// FIXME: None of these add/sub SP special instructions should be necessary