oota-llvm.git
7 years agoReformat.
NAKAMURA Takumi [Thu, 1 Oct 2015 17:01:03 +0000 (17:01 +0000)]
Reformat.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249033 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert r248959, "[WinEH] Emit int3 after noreturn calls on Win64"
NAKAMURA Takumi [Thu, 1 Oct 2015 17:00:56 +0000 (17:00 +0000)]
Revert r248959, "[WinEH] Emit int3 after noreturn calls on Win64"

It broke; LLVM :: CodeGen__Generic__2009-11-16-BadKillsCrash.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249032 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUse more strict types. NFC.
Rafael Espindola [Thu, 1 Oct 2015 15:22:42 +0000 (15:22 +0000)]
Use more strict types. NFC.

On 32 bit ELF these are 32 bit values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249022 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[InstCombine] Remove trivially empty lifetime start/end ranges.
Arnaud A. de Grandmaison [Thu, 1 Oct 2015 14:54:31 +0000 (14:54 +0000)]
[InstCombine] Remove trivially empty lifetime start/end ranges.

Summary:
Some passes may open up opportunities for optimizations, leaving empty
lifetime start/end ranges. For example, with the following code:

    void foo(char *, char *);
    void bar(int Size, bool flag) {
      for (int i = 0; i < Size; ++i) {
        char text[1];
        char buff[1];
        if (flag)
          foo(text, buff); // BBFoo
      }
    }

the loop unswitch pass will create 2 versions of the loop, one with
flag==true, and the other one with flag==false, but always leaving
the BBFoo basic block, with lifetime ranges covering the scope of the for
loop. Simplify CFG will then remove BBFoo in the case where flag==false,
but will leave the lifetime markers.

This patch teaches InstCombine to remove trivially empty lifetime marker
ranges, that is ranges ending right after they were started (ignoring
debug info or other lifetime markers in the range).

This fixes PR24598: excessive compile time after r234581.

Reviewers: reames, chandlerc

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D13305

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249018 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SystemZ] Add assembly instructions for obtaining clock values as well as CPU features
Ulrich Weigand [Thu, 1 Oct 2015 14:43:48 +0000 (14:43 +0000)]
[SystemZ] Add assembly instructions for obtaining clock values as well as CPU features

Provide assembler support for STCK, STCKF, STCKE, and STFLE.

Author: joncmu
Differential Revision: http://reviews.llvm.org/D13299

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249015 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64] Hoist commonly failing check. NFC.
Chad Rosier [Thu, 1 Oct 2015 13:43:05 +0000 (13:43 +0000)]
[AArch64] Hoist commonly failing check. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249011 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64] Rename variable to improve readability. NFC.
Chad Rosier [Thu, 1 Oct 2015 13:33:31 +0000 (13:33 +0000)]
[AArch64] Rename variable to improve readability. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249008 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64] Update comment to reflect reality.
Chad Rosier [Thu, 1 Oct 2015 13:09:44 +0000 (13:09 +0000)]
[AArch64] Update comment to reflect reality.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249007 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips][microMIPS] Implement CACHEE, WRPGPR and WSBH instructions
Zoran Jovanovic [Thu, 1 Oct 2015 12:49:27 +0000 (12:49 +0000)]
[mips][microMIPS] Implement CACHEE, WRPGPR and WSBH instructions
Differential Revision: http://reviews.llvm.org/D10337

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249004 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM] More care with Thumb1 writeback in ARMLoadStoreOptimizer
Scott Douglass [Thu, 1 Oct 2015 11:56:19 +0000 (11:56 +0000)]
[ARM] More care with Thumb1 writeback in ARMLoadStoreOptimizer

Differential Revision: http://reviews.llvm.org/D13240

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249002 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[NaryReassociate] SeenExprs records WeakVH
Jingyue Wu [Thu, 1 Oct 2015 03:51:44 +0000 (03:51 +0000)]
[NaryReassociate] SeenExprs records WeakVH

Summary:
The instructions SeenExprs records may be deleted during rewriting.
FindClosestMatchingDominator should ignore these deleted instructions.

Fixes PR24301.

Reviewers: grosser

Subscribers: grosser, llvm-commits

Differential Revision: http://reviews.llvm.org/D13315

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248983 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix performance problem in long-running SectionMemoryManagers
Keno Fischer [Thu, 1 Oct 2015 02:45:07 +0000 (02:45 +0000)]
Fix performance problem in long-running SectionMemoryManagers

Summary:
Without this patch, the memory manager would call `mprotect` on every memory
region it ever allocated whenever it wanted to finalize memory (i.e. not just
the ones it just allocated). This caused terrible performance problems for
long running memory managers. In one particular compile heavy julia benchmark,
we were spending 50% of time in `mprotect` if running under MCJIT.

Fix this by splitting allocated memory blocks into those on which memory
permissions have been set and those on which they haven't and only running
`mprotect` on the latter.

Reviewers: lhames

Subscribers: reames, llvm-commits

Differential Revision: http://reviews.llvm.org/D13156

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248981 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU/SI: Re-order PreloadedValue enum and number entries based on init order
Tom Stellard [Thu, 1 Oct 2015 02:02:46 +0000 (02:02 +0000)]
AMDGPU/SI: Re-order PreloadedValue enum and number entries based on init order

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D12451

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248978 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[llvm-objdump] Fix time of check to time of use bug.
Davide Italiano [Thu, 1 Oct 2015 01:02:37 +0000 (01:02 +0000)]
[llvm-objdump] Fix time of check to time of use bug.

There's already a test that covers this situation, so we should be
fine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248976 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert "Enable -Wdeprecated in the cmake build now that LLVM (& Clang, Polly, and...
David Blaikie [Thu, 1 Oct 2015 00:44:21 +0000 (00:44 +0000)]
Revert "Enable -Wdeprecated in the cmake build now that LLVM (& Clang, Polly, and LLD) are -Wdeprecated clean"

This reverts commit r248963.

Seems there's some standard libraries (and libcxxabi implementations)
that aren't -Wdeprecated clean... hrm.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248972 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUpdate sample profile propagation algorithm.
Dehao Chen [Thu, 1 Oct 2015 00:26:56 +0000 (00:26 +0000)]
Update sample profile propagation algorithm.

http://reviews.llvm.org/D13218

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248968 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Don't custom-lower vNi32 uint_to_fp when unsafe-fp-math.
Ahmed Bougacha [Thu, 1 Oct 2015 00:11:07 +0000 (00:11 +0000)]
[X86] Don't custom-lower vNi32 uint_to_fp when unsafe-fp-math.

The custom code produces incorrect results if later reassociated.

Since r221657, on x86, vNi32 uitofp is lowered using an optimized
sequence:

  movdqa LCPI0_0(%rip), %xmm1 ## xmm1 = [65535, ...]
  pand %xmm0, %xmm1
  por LCPI0_1(%rip), %xmm1 ## [0x4b000000, ...]
  psrld $16, %xmm0
  por LCPI0_2(%rip), %xmm0 ## [0x53000000, ...]
  addps LCPI0_3(%rip), %xmm0 ## [float -5.497642e+11, ...]
  addps %xmm1, %xmm0

Since r240361, the machine combiner opportunistically reassociates
2-instruction sequences (with -ffast-math). In the new code sequence,
the ADDPS' are eligible. In isolation, for simple examples (without
reassociable users), this makes no performance difference (the goal
being to enable reassociation of longer chains).

In the trivial example (just one uitofp), the reassociation doesn't
happen, because (I think) it would require the emission of a separate
movaps for a constantpool load (instead of folding it into addps).

However, when we have multiple uitofp sequences, and the constantpool
loads are CSE'd earlier, the machine combiner can do the reassociation.

When the ADDPS' are reassociated, the resulting sequence isn't correct
anymore, as we'd be adding large (2**39) constants with comparatively
smaller values (~2**23). Given that two of the three inputs are powers
of 2 larger than 2**16, and that ulp(2**39) == 2**(39-24) == 2**15,
the reassociated chain will produce 0 for any input in [0, 2**14[.
In my testing, it also produces wrong results for 99.5% of [0, 2**32[.

Avoid this by disabling the new lowering when -ffast-math. It does
mean that we'll get slower code than without it, but at least we
won't get egregiously incorrect code.

One might argue that, considering -ffast-math is all but meaningless,
uitofp producing wrong results isn't a compiler bug. But it really is.

Fixes PR24512.

...though this is really more of a workaround.
Ideally, we'd have some sort of Machine FMF, but that's a problem
that's not worth tackling until we do more with machine IR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248965 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoEnable -Wdeprecated in the cmake build now that LLVM (& Clang, Polly, and LLD) are...
David Blaikie [Wed, 30 Sep 2015 23:36:12 +0000 (23:36 +0000)]
Enable -Wdeprecated in the cmake build now that LLVM (& Clang, Polly, and LLD) are -Wdeprecated clean

This particularly helps enforce the C++ Rule of 5 (for new move ops this
is already an error, but for a type only using C++98 features (copy
ctor/assign, dtor) it is only deprecated, not invalid)

Applying the flag for any GCC compatible compiler - GCC doesn't warn on
the Rule of 5 cases that C++11 deprecates, but it doesn't have other
false positives so far as I could see (compiling with GCC 4.8 didn't
produce any -Wdeprecated warnings I could spot).

Reviewers: aaron.ballman

Differential Revision: http://reviews.llvm.org/D13314

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248963 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WinEH] Emit int3 after noreturn calls on Win64
Reid Kleckner [Wed, 30 Sep 2015 23:09:23 +0000 (23:09 +0000)]
[WinEH] Emit int3 after noreturn calls on Win64

The Win64 unwinder disassembles forwards from each PC to try to
determine if this PC is in an epilogue. If so, it skips calling the EH
personality function for that frame. Typically, this means you cannot
catch an exception in the same frame that you threw it, because 'throw'
calls a noreturn runtime function.

Previously we avoided this problem with the TrapUnreachable
TargetOption, but that's a much bigger hammer than we need. All we need
is a 1 byte non-epilogue instruction right after the call.  Instead,
what we got was an unconditional branch to a shared block containing the
ud2, potentially 7 bytes instead of 1. So, this reverts r206684, which
added TrapUnreachable, and replaces it with something better.

The new code pattern matches for invoke/call followed by unreachable and
inserts an int3 into the DAG. To be 100% watertight, we would need to
insert SEH_Epilogue instructions into all basic blocks ending in a call
with no terminators or successors, but in practice this is unlikely to
come up.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248959 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PowerPC] undef Relocation names in PowerPC*.def
Hal Finkel [Wed, 30 Sep 2015 22:34:35 +0000 (22:34 +0000)]
[PowerPC] undef Relocation names in PowerPC*.def

glibc's PowerPC /usr/include/asm/sigcontext.h, has this:

  #ifdef __powerpc64__
  #include <asm/elf.h>
  #endif

and that contains defines of all of the relocation symbols, like this:

  #define R_PPC_NONE              0

and if that file is included prior to including
include/llvm/Support/ELFRelocs/PowerPC*.def, which we cannot in general
prevent, the result will fail.

As it turns out, this happens when compiling
lld/unittests/DriverTests/GnuLdDriverTest.cpp under PPC64/Linux, because:

  lld/include/lld/ReaderWriter/ELFLinkingContext.h includes
  lld/unittests/DriverTests/DriverTest.h which includes
  utils/unittest/googletest/include/gtest/gtest.h which includes
  utils/unittest/googletest/include/gtest/internal/gtest-internal.h which includes
  /usr/include/sys/wait.h which includes
  /usr/include/signal.h which includes
  /usr/include/bits/sigcontext.h which includes
  /usr/include/asm/sigcontext.h which includes
  /usr/include/asm/elf.h

the test could be fixed to include ReaderWriter/ELFLinkingContext.h before
including unittests/DriverTests/DriverTest.h, but dealing with this in the
*.def files is a more-general solution that localizes the fix to the headers
instead of requiring changes to an unbounded number of other source files (both
in-tree and external).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248957 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] enable machine combiner reassociations for 256-bit vector logical integer insts
Sanjay Patel [Wed, 30 Sep 2015 22:25:55 +0000 (22:25 +0000)]
[x86] enable machine combiner reassociations for 256-bit vector logical integer insts

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248955 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[libFuzzer] Marking exported symbols as visible. Patch by Mike Aizatsky
Kostya Serebryany [Wed, 30 Sep 2015 22:22:37 +0000 (22:22 +0000)]
[libFuzzer] Marking exported symbols as visible. Patch by Mike Aizatsky

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248954 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64] Remove an unnecessary run line and other cleanup. NFC.
Chad Rosier [Wed, 30 Sep 2015 21:10:02 +0000 (21:10 +0000)]
[AArch64] Remove an unnecessary run line and other cleanup. NFC.

Unscaled load/store combining has been enabled since the initial ARM64 port.  No
need for a redundance run.  Also, add CHECK-LABEL directives.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248945 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SLP] Don't vectorize loads of non-packed types (like i1, i2).
Michael Zolotukhin [Wed, 30 Sep 2015 21:05:43 +0000 (21:05 +0000)]
[SLP] Don't vectorize loads of non-packed types (like i1, i2).

Summary:
Given an array of i2 elements, 4 consecutive scalar loads will be lowered to
i8-sized loads and thus will access 4 consecutive bytes in memory. If we
vectorize these loads into a single <4 x i2> load, it'll access only 1 byte in
memory. Hence, we should prohibit vectorization in such cases.

PS: Initial patch was proposed by Arnold.

Reviewers: aschwaighofer, nadav, hfinkel

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D13277

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248943 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix -Wsign-compare warning
David Blaikie [Wed, 30 Sep 2015 20:37:48 +0000 (20:37 +0000)]
Fix -Wsign-compare warning

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248942 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMove dw_op_minus test to DebugInfo/X86.
Evgeniy Stepanov [Wed, 30 Sep 2015 20:23:24 +0000 (20:23 +0000)]
Move dw_op_minus test to DebugInfo/X86.

The test requires X86 target support, and checks the actual debug
info contents, including register numbers which would be different on
other platforms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248938 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix debug info with SafeStack.
Evgeniy Stepanov [Wed, 30 Sep 2015 19:55:43 +0000 (19:55 +0000)]
Fix debug info with SafeStack.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248933 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64] Remove an unnecessary restriction on pre-index instructions.
Chad Rosier [Wed, 30 Sep 2015 19:44:40 +0000 (19:44 +0000)]
[AArch64] Remove an unnecessary restriction on pre-index instructions.

Previously, the index was constrained to the size of the memory operation for
no apparent reason.  This change removes that constraint so that we can form
pre-index instructions with any valid offset.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248931 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDeadCodeElimination: rewrite to be faster
Fiona Glaser [Wed, 30 Sep 2015 17:49:49 +0000 (17:49 +0000)]
DeadCodeElimination: rewrite to be faster

Same strategy as simplifyInstructionsInBlock. ~1/3 less time
on my test suite. This pass doesn't have many in-tree users,
but getting rid of an O(N^2) worst case and making it cleaner
should at least make it a viable alternative to ADCE, since
it's now consistently somewhat faster.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248927 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PowerPC] Disable shrink wrapping
Hal Finkel [Wed, 30 Sep 2015 17:29:03 +0000 (17:29 +0000)]
[PowerPC] Disable shrink wrapping

Shrink wrapping is causing a self-hosting failure on PPC64/Linux. Disable for
now until the problem can be fixed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248924 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSLPVectorizer: add a test to check if the minimum region size works.
Erik Eckstein [Wed, 30 Sep 2015 17:28:19 +0000 (17:28 +0000)]
SLPVectorizer: add a test to check if the minimum region size works.

This is an addition to rL248917.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248923 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM] Support for ARMv6-Z / ARMv6-ZK missing
Artyom Skrobov [Wed, 30 Sep 2015 17:25:52 +0000 (17:25 +0000)]
[ARM] Support for ARMv6-Z / ARMv6-ZK missing

As Richard Barton observed at http://reviews.llvm.org/D12937#inline-107121
TargetParser in LLVM has insufficient support for ARMv6Z and ARMv6ZK.

In particular, there were no tests for TrustZone being supported in these
architectures.

The patch clears a FIXME: left by Saleem Abdulrasool in r201471, and fixes
his test case which hadn't really been testing what it was claiming to test.

Differential Revision: http://reviews.llvm.org/D13236

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248921 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSLPVectorizer: limit the scheduling region size per basic block.
Erik Eckstein [Wed, 30 Sep 2015 17:00:44 +0000 (17:00 +0000)]
SLPVectorizer: limit the scheduling region size per basic block.

Usually large blocks are not a problem. But if a large block (> 10k instructions)
contains many (potential) chains of vector instructions, and those chains are
spread over a wide range of instructions, then scheduling becomes a compile time problem.
This change introduces a limit for the accumulate scheduling region size of a block.
For real-world functions this limit will never be exceeded (it's about 10x larger than
the maximum value seen in the test-suite and external test suite).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248917 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64] Use helper function to improve readability. NFC.
Chad Rosier [Wed, 30 Sep 2015 16:50:41 +0000 (16:50 +0000)]
[AArch64] Use helper function to improve readability. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248914 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[InstCombine] Teach how to convert SSSE3/AVX2 byte shuffles to builtin shuffles if...
Andrea Di Biagio [Wed, 30 Sep 2015 16:44:39 +0000 (16:44 +0000)]
[InstCombine] Teach how to convert SSSE3/AVX2 byte shuffles to builtin shuffles if the shuffle mask is constant.

This patch teaches InstCombiner how to convert a SSSE3/AVX2 byte shuffle to a
builtin shuffle if the mask is constant.

Converting byte shuffle intrinsic calls to builtin shuffles can help finding
more opportunities for combining shuffles later on in selection dag.

We may end up with byte shuffles with constant masks as the result of inlining.

Differential Revision: http://reviews.llvm.org/D13252

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248913 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[CMake] Make the bindir and libdir arguments to set_output_directory optional
John Brawn [Wed, 30 Sep 2015 15:20:51 +0000 (15:20 +0000)]
[CMake] Make the bindir and libdir arguments to set_output_directory optional

When building a plugin against an installed LLVM toolchain using
add_llvm_loadable_module (in the documented manner) doesn't work as nothing sets
the *_OUTPUT_INTDIR variables causing an error when set_output_directory is
called. Making those arguments optional (causing the default output directory
to be used) fixes this.

Differential Revision: http://reviews.llvm.org/D13215

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248911 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd support for sub-byte aligned writes to lib/Support/Endian.h
Teresa Johnson [Wed, 30 Sep 2015 13:20:37 +0000 (13:20 +0000)]
Add support for sub-byte aligned writes to lib/Support/Endian.h

Summary:
As per Duncan's review for D12536, I extracted the sub-byte bit aligned
reading and writing code into lib/Support, and generalized it. Added calls from
BackpatchWord. Also added unittests.

Reviewers: dexonsmith

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D13189

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248897 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRefactor computeKnownBits alignment handling code
Artur Pilipenko [Wed, 30 Sep 2015 11:55:45 +0000 (11:55 +0000)]
Refactor computeKnownBits alignment handling code

Reviewed By: reames, hfinkel

Differential Revision: http://reviews.llvm.org/D12958

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248892 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane)...
Jeroen Ketema [Wed, 30 Sep 2015 10:56:37 +0000 (10:56 +0000)]
[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions

This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234],
vst[234]lane ARM neon intrinsics and associates an address space with the
pointer that these intrinsics take. This changes, e.g.,

<2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32)

to

<2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32)

This change ensures that address spaces are fully taken into account in the ARM
target during lowering of interleaved loads and stores.

Differential Revision: http://reviews.llvm.org/D12985

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248887 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[CMake] Adjust the variables set by LLVMConfig.cmake
John Brawn [Wed, 30 Sep 2015 10:34:06 +0000 (10:34 +0000)]
[CMake] Adjust the variables set by LLVMConfig.cmake

When using LLVMConfig.cmake from an installed toolchain in order to build a
loadable pass using add_llvm_loadable_module LLVM_ENABLE_PLUGINS and
LLVM_PLUGIN_EXT must be set. Also make LLVM_DEFINITIONS be set to what it
actually is.

Differential Revision: http://reviews.llvm.org/D13214

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248884 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86][XOP] Added support for the lowering of 128-bit vector shifts to XOP shift instr...
Simon Pilgrim [Wed, 30 Sep 2015 08:17:50 +0000 (08:17 +0000)]
[X86][XOP] Added support for the lowering of 128-bit vector shifts to XOP shift instructions

The XOP shifts just have logical/arithmetic versions and the left/right shifts are controlled by whether the value is positive/negative. Because of this I've added new X86ISD nodes instead of trying to force them to use the existing shift nodes.

Additionally Excavator cores (bdver4) support XOP and AVX2 - meaning that it should use the AVX2 shifts when it can and fall back to XOP in other cases.

Differential Revision: http://reviews.llvm.org/D8690

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248878 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoInstrProf: Don't call std::unique twice here
Justin Bogner [Wed, 30 Sep 2015 02:02:08 +0000 (02:02 +0000)]
InstrProf: Don't call std::unique twice here

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248872 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd unittest for new samle profile format.
Dehao Chen [Wed, 30 Sep 2015 01:05:37 +0000 (01:05 +0000)]
Add unittest for new samle profile format.

http://reviews.llvm.org/D13145

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248870 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agohttp://reviews.llvm.org/D13145
Dehao Chen [Wed, 30 Sep 2015 00:42:46 +0000 (00:42 +0000)]
http://reviews.llvm.org/D13145

Support hierarachical sample profile format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248865 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[safestack] Fix a stupid mix-up in the direct-tls code path.
Evgeniy Stepanov [Wed, 30 Sep 2015 00:01:47 +0000 (00:01 +0000)]
[safestack] Fix a stupid mix-up in the direct-tls code path.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248863 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoInstrProf: Add a missing const_cast from r248833
Justin Bogner [Tue, 29 Sep 2015 23:42:47 +0000 (23:42 +0000)]
InstrProf: Add a missing const_cast from r248833

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248859 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU/SI: Don't set DATA_FORMAT if ADD_TID_ENABLE is set
Marek Olsak [Tue, 29 Sep 2015 23:37:32 +0000 (23:37 +0000)]
AMDGPU/SI: Don't set DATA_FORMAT if ADD_TID_ENABLE is set

to prevent setting a huge stride, because DATA_FORMAT has a different
meaning if ADD_TID_ENABLE is set.

This is a candidate for stable llvm 3.7.

Tested-and-Reviewed-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248858 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WinEH] Setup RBP correctly in Win64 funclet prologues
Reid Kleckner [Tue, 29 Sep 2015 23:32:01 +0000 (23:32 +0000)]
[WinEH] Setup RBP correctly in Win64 funclet prologues

Previously local variable captures just didn't work in 64-bit. Now we
can access local variables more or less correctly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248857 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WinEH] Ensure that funclets obey the x64 ABI
David Majnemer [Tue, 29 Sep 2015 22:33:36 +0000 (22:33 +0000)]
[WinEH] Ensure that funclets obey the x64 ABI

The x64 ABI requires that epilogues do not contain code other than stack
adjustments and some limited control flow.  However, we'd insert code to
initialize the return address after stack adjustments.  Instead, insert
EAX/RAX with the current value before we create the stack adjustments in
the epilogue.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248839 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoInstrProf: Support for value profiling in the indexed profile format
Justin Bogner [Tue, 29 Sep 2015 22:13:58 +0000 (22:13 +0000)]
InstrProf: Support for value profiling in the indexed profile format

Add support to the indexed instrprof reader and writer for the format
that will be used for value profiling.

Patch by Betul Buyukkurt, with minor modifications.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248833 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoHHVM calling conventions.
Maksim Panchenko [Tue, 29 Sep 2015 22:09:16 +0000 (22:09 +0000)]
HHVM calling conventions.

HHVM calling convention, hhvmcc, is used by HHVM JIT for
functions in translated cache. We currently support LLVM back end to
generate code for X86-64 and may support other architectures in the
future.

In HHVM calling convention any GP register could be used to pass and
return values, with the exception of R12 which is reserved for
thread-local area and is callee-saved. Other than R12, we always
pass RBX and RBP as args, which are our virtual machine's stack pointer
and frame pointer respectively.

When we enter translation cache via hhvmcc function, we expect
the stack to be aligned at 16 bytes, i.e. skewed by 8 bytes as opposed
to standard ABI alignment. This affects stack object alignment and stack
adjustments for function calls.

One extra calling convention, hhvm_ccc, is used to call C++ helpers from
HHVM's translation cache. It is almost identical to standard C calling
convention with an exception of first argument which is passed in RBP
(before we use RDI, RSI, etc.)

Differential Revision: http://reviews.llvm.org/D12681

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248832 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix test from r248825.
Chad Rosier [Tue, 29 Sep 2015 20:50:15 +0000 (20:50 +0000)]
Fix test from r248825.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248827 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64] Add support for pre- and post-index LDPSWs.
Chad Rosier [Tue, 29 Sep 2015 20:39:55 +0000 (20:39 +0000)]
[AArch64] Add support for pre- and post-index LDPSWs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248825 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WinEH] Teach AsmPrinter about funclets
David Majnemer [Tue, 29 Sep 2015 20:12:33 +0000 (20:12 +0000)]
[WinEH] Teach AsmPrinter about funclets

Summary:
Funclets have been turned into functions by the time they hit the object
file.  Make sure that they have decent names for the symbol table and
CFI directives explaining how to reason about their prologues.

Differential Revision: http://reviews.llvm.org/D13261

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248824 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[llvm-pdbdump] Add include-only filters.
Zachary Turner [Tue, 29 Sep 2015 19:49:06 +0000 (19:49 +0000)]
[llvm-pdbdump] Add include-only filters.

PDB files have a lot of noise in them, with hundreds (or thousands)
of symbols from system libraries and compiler generated types.  If
you're only looking for a specific type, this can be problematic.

This CL allows you to display *only* types, variables, or compilands
matching a particular pattern.  These filters can even be combined
with exclude filters.  Include-only filters are given priority, so
that first the set of items to display is limited only to those that
match the include filters, and then the set of exclude filters is
applied to those.  If there are no include filters specified, then
it means "display everything".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248822 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRename some function arguments in MachineBasicBlock.cpp/h by turning the first letter...
Cong Hou [Tue, 29 Sep 2015 19:46:09 +0000 (19:46 +0000)]
Rename some function arguments in MachineBasicBlock.cpp/h by turning the first letter into upper case. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248821 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agohttp://reviews.llvm.org/D13231
Dehao Chen [Tue, 29 Sep 2015 18:28:15 +0000 (18:28 +0000)]
http://reviews.llvm.org/D13231

Change lookup functions to const functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248818 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64] Add integer pre- and post-index halfword/byte loads and stores.
Chad Rosier [Tue, 29 Sep 2015 18:26:15 +0000 (18:26 +0000)]
[AArch64] Add integer pre- and post-index halfword/byte loads and stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248817 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert r248810 which breaks tests.
Dehao Chen [Tue, 29 Sep 2015 18:18:49 +0000 (18:18 +0000)]
Revert r248810 which breaks tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248814 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix Clang-tidy modernize-use-nullptr warnings in examples and include directories...
Hans Wennborg [Tue, 29 Sep 2015 18:02:48 +0000 (18:02 +0000)]
Fix Clang-tidy modernize-use-nullptr warnings in examples and include directories; other minor cleanups.

Patch by Eugene Zelenko!

Differential Revision: http://reviews.llvm.org/D13172

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248811 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agohttp://reviews.llvm.org/D13231
Dehao Chen [Tue, 29 Sep 2015 17:59:58 +0000 (17:59 +0000)]
http://reviews.llvm.org/D13231

Change lookup functions to const functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248810 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAddition of interfaces the BE to conform to Table A-2 of ELF V2 ABI V1.1
Nemanja Ivanovic [Tue, 29 Sep 2015 17:41:53 +0000 (17:41 +0000)]
Addition of interfaces the BE to conform to Table A-2 of ELF V2 ABI V1.1

This patch corresponds to review:
http://reviews.llvm.org/D13191

Back end portion of the fifth round of additions to altivec.h.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248809 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64] Scale offsets by the size of the memory operation. NFC.
Chad Rosier [Tue, 29 Sep 2015 16:07:32 +0000 (16:07 +0000)]
[AArch64] Scale offsets by the size of the memory operation. NFC.

The immediate in the load/store should be scaled by the size of the memory
operation, not the size of the register being loaded/stored.  This change gets
us one step closer to forming LDPSW instructions.  This change also enables
pre- and post-indexing for halfword and byte loads and stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248804 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ValueTracking] Lower dom-conditions-dom-blocks and dom-conditions-max-uses thresholds
Igor Laevsky [Tue, 29 Sep 2015 14:57:52 +0000 (14:57 +0000)]
[ValueTracking] Lower dom-conditions-dom-blocks and dom-conditions-max-uses thresholds

On some of our benchmarks this change shows about 50% compile time improvement without any noticeable performance difference.

Differential Revision: http://reviews.llvm.org/D13248

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248801 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64] Remove some redundant cases. NFC.
Chad Rosier [Tue, 29 Sep 2015 14:57:10 +0000 (14:57 +0000)]
[AArch64] Remove some redundant cases. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248800 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[CMake] Move the setting of LLVM_COMPILER_IS_GCC_COMPATIBLE to a separate file
John Brawn [Tue, 29 Sep 2015 14:33:58 +0000 (14:33 +0000)]
[CMake] Move the setting of LLVM_COMPILER_IS_GCC_COMPATIBLE to a separate file

Currently LLVM_COMPILER_IS_GCC_COMPATIBLE is set as a side-effect of determining
the stdlib to use in HandleLLVMStdlib, which causes problems when attempting to
use AddLLVM from an installed LLVM toolchain, as HandleLLVMStdlib is not used.
Move the setting of this variable into DetermineGCCCompatible and include that
from both AddLLVM and HandleLLVMStdlib.

Differential Revision: http://reviews.llvm.org/D13216

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248798 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ValueTracking] Teach isKnownNonZero about monotonically increasing PHIs
James Molloy [Tue, 29 Sep 2015 14:08:45 +0000 (14:08 +0000)]
[ValueTracking] Teach isKnownNonZero about monotonically increasing PHIs

If a PHI starts at a non-negative constant, monotonically increases
(only adds of a constant are supported at the moment) and that add
does not wrap, then the PHI is known never to be zero.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248796 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoArguments spilled on the stack before a function call may have
Jeroen Ketema [Tue, 29 Sep 2015 10:12:57 +0000 (10:12 +0000)]
Arguments spilled on the stack before a function call may have
alignment requirements, for example in the case of vectors.
These requirements are exploited by the code generator by using
move instructions that have similar alignment requirements, e.g.,
movaps on x86.

Although the code generator properly aligns the arguments with
respect to the displacement of the stack pointer it computes,
the displacement itself may cause misalignment. For example if
we have

%3 = load <16 x float>, <16 x float>* %1, align 64
call void @bar(<16 x float> %3, i32 0)

the x86 back-end emits:

movaps  32(%ecx), %xmm2
movaps  (%ecx), %xmm0
movaps  16(%ecx), %xmm1
movaps  48(%ecx), %xmm3
subl    $20, %esp       <-- if %esp was 16-byte aligned before this instruction, it no longer will be afterwards
movaps  %xmm3, (%esp)   <-- movaps requires 16-byte alignment, while %esp is not aligned as such.
movl    $0, 16(%esp)
calll   __bar

To solve this, we need to make sure that the computed value with which
the stack pointer is changed is a multiple af the maximal alignment seen
during its computation. With this change we get proper alignment:

subl    $32, %esp
movaps  %xmm3, (%esp)

Differential Revision: http://reviews.llvm.org/D12337

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248786 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[InstCombine] Improve Vector Demanded Bits Through Bitcasts
Simon Pilgrim [Tue, 29 Sep 2015 08:19:11 +0000 (08:19 +0000)]
[InstCombine] Improve Vector Demanded Bits Through Bitcasts

Currently SimplifyDemandedVectorElts can only peek through bitcasts if the vectors have the same number of elements.

This patch fixes and enables some existing (disabled) code to support bitcasting to vectors with more/fewer elements. It currently only accepts cases when vectors alias cleanly (i.e. number of elements are an exact multiple of the other vector).

This was added to improve the demanded vector elements support for SSE vector shifts which require the __m128i (<2 x i64>) argument type to be bitcast to the vector type for the builtin shift. I've added extra tests for various additional bitcasts.

Differential Revision: http://reviews.llvm.org/D12935

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248784 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WebAssembly] Rename test files to match platform naming conventions.
Dan Gohman [Tue, 29 Sep 2015 08:13:58 +0000 (08:13 +0000)]
[WebAssembly] Rename test files to match platform naming conventions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248783 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[LoopUnswitch] Add block frequency analysis to recognize hot/cold regions
Chen Li [Tue, 29 Sep 2015 05:03:32 +0000 (05:03 +0000)]
[LoopUnswitch] Add block frequency analysis to recognize hot/cold regions

Summary: This patch adds block frequency analysis to LoopUnswitch pass to recognize hot/cold regions. For cold regions the pass only performs trivial unswitches since they do not increase code size, and for hot regions everything works as before. This helps to minimize code growth in cold regions and be more aggressive in hot regions. Currently the default cold regions are blocks with frequencies below 20% of function entry frequency, and it can be adjusted via -loop-unswitch-cold-block-frequency flag. The entire feature is controlled via -loop-unswitch-with-block-frequency flag and it is off by default.

Reviewers: broune, silvas, dnovillo, reames

Subscribers: davidxl, llvm-commits

Differential Revision: http://reviews.llvm.org/D11605

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248777 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[CMake] X86AsmParser: Prune redundant LINK_LIBS.
NAKAMURA Takumi [Tue, 29 Sep 2015 01:25:01 +0000 (01:25 +0000)]
[CMake] X86AsmParser: Prune redundant LINK_LIBS.

It is described in LLVMBuild.txt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248771 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMove dbg.declare intrinsics when merging and replacing allocas.
Evgeniy Stepanov [Tue, 29 Sep 2015 00:30:19 +0000 (00:30 +0000)]
Move dbg.declare intrinsics when merging and replacing allocas.

Place new and update dbg.declare calls immediately after the
corresponding alloca.

Current code in replaceDbgDeclareForAlloca puts the new dbg.declare
at the end of the basic block. LLVM codegen has problems emitting
debug info in a situation when dbg.declare appears after all uses of
the variable. This usually kinda works for inlining and ASan (two
users of this function) but not for SafeStack (see the pending change
in http://reviews.llvm.org/D13178).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248769 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRegisterPressure: LiveRegSet tracks register units not physregs
Matthias Braun [Tue, 29 Sep 2015 00:20:32 +0000 (00:20 +0000)]
RegisterPressure: LiveRegSet tracks register units not physregs

There are always more physical registers and register units so the
previous behaviour was correct but we can do with less memory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248767 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WinEH] Fix ip2state table emission with funclets
Reid Kleckner [Mon, 28 Sep 2015 23:56:30 +0000 (23:56 +0000)]
[WinEH] Fix ip2state table emission with funclets

Previously we were hijacking the old LandingPadInfo data structures to
communicate our state numbers. Now we don't need that anymore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248763 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix unused variable warning in non-debug builds.
Richard Trieu [Mon, 28 Sep 2015 22:54:43 +0000 (22:54 +0000)]
Fix unused variable warning in non-debug builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248754 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agotidy up comments; NFC
Sanjay Patel [Mon, 28 Sep 2015 22:14:51 +0000 (22:14 +0000)]
tidy up comments; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248750 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoadd a FIXME for a CPU model check that should have an attribute instead
Sanjay Patel [Mon, 28 Sep 2015 22:00:24 +0000 (22:00 +0000)]
add a FIXME for a CPU model check that should have an attribute instead

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248746 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agomove one-use check under the comment that describes it; NFCI
Sanjay Patel [Mon, 28 Sep 2015 21:44:46 +0000 (21:44 +0000)]
move one-use check under the comment that describes it; NFCI

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248745 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SCEV] Don't crash on pointer comparisons
Sanjoy Das [Mon, 28 Sep 2015 21:14:32 +0000 (21:14 +0000)]
[SCEV] Don't crash on pointer comparisons

`ScalarEvolution::isImpliedCondOperandsViaNoOverflow` tries to cast the
operand type of the comparison it is given to an `IntegerType`.  This is
incorrect because it could actually be simplifying a comparison between
two pointers.  Switch it to using `getTypeSizeInBits` instead, which
does the right thing for both pointers and integers.

Fixed PR24956.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248743 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU: Factor switch into separate function
Matt Arsenault [Mon, 28 Sep 2015 20:54:57 +0000 (20:54 +0000)]
AMDGPU: Factor switch into separate function

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248742 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU: Fix splitting x16 SMRD loads
Matt Arsenault [Mon, 28 Sep 2015 20:54:52 +0000 (20:54 +0000)]
AMDGPU: Fix splitting x16 SMRD loads

When used recursively, this would set the kill flag
on the intermediate step from first splitting
x16 to x8.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248741 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU: Fix moving SMRD loads with literal offsets on CI
Matt Arsenault [Mon, 28 Sep 2015 20:54:46 +0000 (20:54 +0000)]
AMDGPU: Fix moving SMRD loads with literal offsets on CI

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248740 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU: Fix splitting SMRD with large offset
Matt Arsenault [Mon, 28 Sep 2015 20:54:42 +0000 (20:54 +0000)]
AMDGPU: Fix splitting SMRD with large offset

The splitting of > 4 dword SMRD instructions
if using an offset in an SGPR instead of an immediate
was not setting the destination register,
resulting an an instruction missing an operand
which would assert later.

Test will be included in a following commit
which fixes a related issue.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248739 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU: Add testcases
Matt Arsenault [Mon, 28 Sep 2015 20:54:38 +0000 (20:54 +0000)]
AMDGPU: Add testcases

Make sure we are testing moving users
of the moved and split SMRD loads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248738 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU: Cleanup test
Matt Arsenault [Mon, 28 Sep 2015 20:54:32 +0000 (20:54 +0000)]
AMDGPU: Cleanup test

Run instnamer on it, and rename check prefix.

This is in preparation for adding new testcases to cover
bugs on other subtargets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248737 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoImproved the interface of methods commuting operands, improved X86-FMA3 mem-folding...
Andrew Kaylor [Mon, 28 Sep 2015 20:33:22 +0000 (20:33 +0000)]
Improved the interface of methods commuting operands, improved X86-FMA3 mem-folding&coalescing.

Patch by Slava Klochkov (vyacheslav.n.klochkov@intel.com)

Differential Revision: http://reviews.llvm.org/D11370

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248735 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[GlobalOpt] Sort members of llvm.used deterministically
Sean Silva [Mon, 28 Sep 2015 19:02:11 +0000 (19:02 +0000)]
[GlobalOpt] Sort members of llvm.used deterministically

Patch by Jake VanAdrighem!

Summary:
Fix the way we sort the llvm.used and llvm.compiler.used members.

This bug seems to have been introduced in rL183756 through a set of improper casts to GlobalValue*. In subsequent patches this problem was missed and transformed into a getName call on a ConstantExpr.

Reviewers: silvas

Subscribers: silvas, llvm-commits

Differential Revision: http://reviews.llvm.org/D12851

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248728 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoImprove performance of SimplifyInstructionsInBlock
Fiona Glaser [Mon, 28 Sep 2015 18:56:07 +0000 (18:56 +0000)]
Improve performance of SimplifyInstructionsInBlock

1. Use a worklist, not a recursive approach, to avoid needless
   revisitation and being repeatedly forced to jump back to the
   start of the BB if a handle is invalidated.

2. Only insert operands to the worklist if they become unused
   after a dead instruction is removed, so we don’t have to
   visit them again in most cases.

3. Use a SmallSetVector to track the worklist.

4. Instead of pre-initting the SmallSetVector like in
   DeadCodeEliminationPass, only put things into the worklist
   if they have to be revisited after the first run-through.
   This minimizes how much the actual SmallSetVector gets used,
   which saves a lot of time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248727 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips][p5600] Added P5600 processor and initial scheduler.
Daniel Sanders [Mon, 28 Sep 2015 18:24:08 +0000 (18:24 +0000)]
[mips][p5600] Added P5600 processor and initial scheduler.

Summary:
The P5600 is an out-of-order, superscalar implementation of the MIPS32R5
architecture.

The scheduler has a few missing details (see the 'Tricky Instructions'
section and some quirks of the P5600 are deliberately omitted due to
implementation difficulty and low chance of significant benefit (e.g. the
predicate on P5600WriteEitherALU). However, testing on SingleSource is
showing significant performance benefits on some apps (seven in the 10-30%
range) and only one significant regression (12%) when
-pre-RA-sched=linearize is given. Without -pre-RA-sched=linearize the
results are more variable. Some do even better (up to 55% improvement) but
increased numbers of copies are slowing others down (up to 12%).

Overall, the scheduler as it currently stands is a 2.4% win with
-pre-RA-sched=linearize and a 2.7% win without -pre-RA-sched=linearize.
I'm sure we can improve on this further.

For completeness, the FPGA this was tested on shows some failures with and
without the P5600 scheduler. These appear to be scheduling related since
the two test runs have fairly different sets of failing tests even after
accounting for other factors (e.g. spurious connection failures) however
it's not P5600 specific since we also get some for the generic scheduler.

Reviewers: vkalintiris

Subscribers: mpf, llvm-commits, atrick, vkalintiris

Differential Revision: http://reviews.llvm.org/D12193

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248725 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoIntroduce !align metadata for load instruction
Artur Pilipenko [Mon, 28 Sep 2015 17:41:08 +0000 (17:41 +0000)]
Introduce !align metadata for load instruction

Reviewed By: hfinkel

Differential Revision: http://reviews.llvm.org/D12853

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248721 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[InstSimplify] Fold simple known implications to true
Philip Reames [Mon, 28 Sep 2015 17:14:24 +0000 (17:14 +0000)]
[InstSimplify] Fold simple known implications to true

This was split off of http://reviews.llvm.org/D13040 to make it easier to test the correctness of the implication logic. For the moment, this only handles a single easy case which shows up when eliminating and combining range checks. In the (near) future, I plan to extend this for other cases which show up in range checks, but I wanted to make those changes incrementally once the framework was in place.

At the moment, the implication logic will be used by three places. One in InstSimplify (this review) and two in SimplifyCFG (http://reviews.llvm.org/D13040 & http://reviews.llvm.org/D13070). Can anyone think of other locations this style of reasoning would make sense?

Differential Revision: http://reviews.llvm.org/D13074

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248719 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[LoopReroll] Ignore debug intrinsics
Weiming Zhao [Mon, 28 Sep 2015 17:03:23 +0000 (17:03 +0000)]
[LoopReroll] Ignore debug intrinsics

Originally, debug intrinsics and annotation intrinsics may prevent
the loop to be rerolled, now they are ignored.

Differential Revision: http://reviews.llvm.org/D13150

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248718 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WebAssembly] Support for direct call and call_indirect.
Dan Gohman [Mon, 28 Sep 2015 16:22:39 +0000 (16:22 +0000)]
[WebAssembly] Support for direct call and call_indirect.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248716 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips] Handling of immediates bigger than 16 bits
Zoran Jovanovic [Mon, 28 Sep 2015 11:11:34 +0000 (11:11 +0000)]
[mips] Handling of immediates bigger than 16 bits
Differential Revision: http://reviews.llvm.org/D10539

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248706 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM] Avoid redundant checks for isThumb1Only() after supportsTailCall()
Artyom Skrobov [Mon, 28 Sep 2015 09:44:11 +0000 (09:44 +0000)]
[ARM] Avoid redundant checks for isThumb1Only() after supportsTailCall()

supportsTailCall() has two callers. Both of them double-check isThumb1Only(),
and refuse to proceed with tail-calling in that case.
Therefore, it makes sense to move this check to
ARMSubtarget::initSubtargetFeatures, where SupportsTailCall is initialized;
and to eliminate the extra checks at the call sites.

Following a review comment, added an "assert(supportsTailCall())"
in IsEligibleForTailCall.

NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248703 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[DAGCombine] Fix getStoreMergeAndAliasCandidates's AA-enabled chain walking
Hal Finkel [Mon, 28 Sep 2015 08:02:14 +0000 (08:02 +0000)]
[DAGCombine] Fix getStoreMergeAndAliasCandidates's AA-enabled chain walking

When AA is being used, non-aliasing stores are canonicalized to use the same
chain, and DAGCombiner::getStoreMergeAndAliasCandidates can take advantage of
this by looking only as users of a store's chain operand. However, user
iteration is not result-number specific, we need to check that the use is as a
chain operand, and not via some other operand. It is certainly possible to have
another potentially-aliasing store, which shares the first's base pointer, and
uses the first's chain's node via some other operand.

Failure to catch this situation caused, at least in the included test case, an
assert later because the relative sequence-number ordering caused later
replacement to create a cycle in the DAG.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248698 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove 'const' from some ArrayRefs. ArrayRefs are already immutable. NFC
Craig Topper [Mon, 28 Sep 2015 00:15:34 +0000 (00:15 +0000)]
Remove 'const' from some ArrayRefs. ArrayRefs are already immutable. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248693 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAsmWriter: Print the argument names in declarations while debugging
Justin Bogner [Sun, 27 Sep 2015 22:38:50 +0000 (22:38 +0000)]
AsmWriter: Print the argument names in declarations while debugging

When llvm declarations have argument names, it's helpful to actually
print those names when debugging. Arguably, it'd be nice to print them
all the time, but that would mean the IR we output wouldn't round trip
through bitcode, which doesn't store the names.

Make the varous print() methods in AsmWriter optionally print "for
debug" and set that flag in the dump() methods. The only thing this
does differently for now is print the argument names in declarations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248692 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSilence clang warning: variable ‘Status’ set but not used.
Yaron Keren [Sun, 27 Sep 2015 21:31:33 +0000 (21:31 +0000)]
Silence clang warning: variable ‘Status’ set but not used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248691 91177308-0d34-0410-b5e6-96231b3b80d8