[X86][XOP] Added support for the lowering of 128-bit vector shifts to XOP shift instr...
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Wed, 30 Sep 2015 08:17:50 +0000 (08:17 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Wed, 30 Sep 2015 08:17:50 +0000 (08:17 +0000)
commit4e042482c8714aec2a3433e8db055d7983bdabe9
treeba0d64dad63810b092244045bf57ec60dedc1c33
parent40be10cf3a2248f2baf0c1b4dc8a75fb5b26dd13
[X86][XOP] Added support for the lowering of 128-bit vector shifts to XOP shift instructions

The XOP shifts just have logical/arithmetic versions and the left/right shifts are controlled by whether the value is positive/negative. Because of this I've added new X86ISD nodes instead of trying to force them to use the existing shift nodes.

Additionally Excavator cores (bdver4) support XOP and AVX2 - meaning that it should use the AVX2 shifts when it can and fall back to XOP in other cases.

Differential Revision: http://reviews.llvm.org/D8690

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248878 91177308-0d34-0410-b5e6-96231b3b80d8
13 files changed:
lib/Target/X86/X86ISelLowering.cpp
lib/Target/X86/X86ISelLowering.h
lib/Target/X86/X86InstrFragmentsSIMD.td
lib/Target/X86/X86InstrXOP.td
lib/Target/X86/X86IntrinsicsInfo.h
lib/Target/X86/X86TargetTransformInfo.cpp
test/Analysis/CostModel/X86/vshift-cost.ll
test/CodeGen/X86/vector-shift-ashr-128.ll
test/CodeGen/X86/vector-shift-ashr-256.ll
test/CodeGen/X86/vector-shift-lshr-128.ll
test/CodeGen/X86/vector-shift-lshr-256.ll
test/CodeGen/X86/vector-shift-shl-128.ll
test/CodeGen/X86/vector-shift-shl-256.ll