Teach instCombine to remove malloc+free if malloc's only uses are comparisons
[oota-llvm.git] / lib / Target /
2010-05-27 Dan GohmanFastISel doesn't yet handle callee-pop functions.
2010-05-27 Jim Grosbachadd ISD::STACKADDR to get the current stack pointer...
2010-05-27 Bruno Cardoso LopesMerge basic binops SSE 1 & 2 instruction classes. This...
2010-05-26 Daniel DunbarAsmMatcher/X86: Mark _REV instructions as "code gen...
2010-05-26 Jakob Stoklund OlesenGive SubRegIndex names to all ARM subregisters. This...
2010-05-26 Daniel DunbarMC: Add TargetMachine support for setting the value...
2010-05-26 Jakob Stoklund OlesenAdd StringRef::compare_numeric and use it to sort Table...
2010-05-26 Jim GrosbachAdjust eh.sjlj.setjmp to properly have a chain and...
2010-05-26 Kevin EnderbyFix the x86 move to/from segment register instructions.
2010-05-26 Daniel DunbarMC: Change RelaxInstruction to only take the input...
2010-05-26 Dan GohmanFix a typo in a comment that Gabor noticed.
2010-05-26 Daniel DunbarMC: Simplify MayNeedRelaxation to not provide the fixup...
2010-05-26 Jakob Stoklund OlesenReplace the SubRegSet tablegen class with a less error...
2010-05-26 Daniel DunbarMC: Eliminate MCAsmFixup, replace with MCFixup.
2010-05-26 Daniel DunbarMC: Use accessors for access to MCAsmFixup.
2010-05-26 Daniel DunbarMC: Change MCInst::dump_pretty to not include a trailin...
2010-05-26 Zhongxing XuSRetReturnReg was set in LowerFormalArguments(). So...
2010-05-26 Shih-wei LiaoCoding style change (Adding 1 missing space.)
2010-05-26 Shih-wei LiaoAdding the missing implementation for ARM::SBFX and...
2010-05-26 Jim Grosbachfix off by 1 (insn) error in eh.sjlj.setjmp thumb code...
2010-05-26 Jakob Stoklund OlesenRevert "Replace the SubRegSet tablegen class with a...
2010-05-26 Jakob Stoklund OlesenReplace the SubRegSet tablegen class with a less error...
2010-05-26 Shih-wei LiaoAdding the missing implementation of Bitfield's "clear...
2010-05-26 Shih-wei LiaoTo handle s* registers in emitVFPLoadStoreMultipleInstr...
2010-05-25 Jakob Stoklund OlesenDrop the SuperregHashTable. It is essentially the same...
2010-05-25 Kevin EnderbyChanged the encoding of X86 floating point stack operat...
2010-05-25 Jakob Stoklund OlesenSeparate unrelated cases that once shared a numeric...
2010-05-25 Jakob Stoklund OlesenPrint symbolic SubRegIndex names on machine operands.
2010-05-25 Jakob Stoklund OlesenRemove NumberHack entirely.
2010-05-25 Daniel DunbarMC/X86: Add a hack to allow recognizing 'cmpltps' and...
2010-05-25 Daniel DunbarMC/X86: Define explicit immediate forms of cmp{ss,sd...
2010-05-25 Kevin EnderbyThe BT64ri8 record in X86Instr64bit.td was missing...
2010-05-25 Eric ChristopherMake sure aeskeygenassist uses an unsigned immediate...
2010-05-25 Jakob Stoklund OlesenIgnore NumberHack and give each SubRegIndex instance...
2010-05-25 Jakob Stoklund OlesenUse enums instead of literals for SystemZ subregisters
2010-05-25 Jakob Stoklund OlesenUse enums instead of literals for X86 subregisters.
2010-05-25 Zonr ChangAdd missing implementation to the materialization of...
2010-05-25 Zonr ChangAdd support to MOVimm32 using movt/movw for ARM JIT
2010-05-25 Bob WilsonAllow t2MOVsrl_flag and t2MOVsra_flag instructions...
2010-05-25 Bob WilsonFix up instruction classes for Thumb2 RSB instructions...
2010-05-25 Bob WilsonClean up indentation.
2010-05-25 Jakob Stoklund OlesenUse enums instead of literals in the ARM backend.
2010-05-24 Jakob Stoklund OlesenSwitch SubRegSet to using symbolic SubRegIndices
2010-05-24 Bob WilsonAllow Thumb2 MVN instructions to set condition codes...
2010-05-24 Jakob Stoklund OlesenLose the dummies
2010-05-24 Jakob Stoklund OlesenReplace the tablegen RegisterClass field SubRegClassLis...
2010-05-24 Dan GohmanFix an mmx movd encoding.
2010-05-24 Kevin EnderbyMC/X86: Add aliases for CMOVcc variants.
2010-05-24 Bob WilsonClean up some extra whitespace.
2010-05-24 Bob WilsonThumb2 RSBS instructions were being printed without...
2010-05-24 Evan ChengLR is in GPR, not tGPR even in Thumb1 mode.
2010-05-24 Jakob Stoklund OlesenAdd SubRegIndex defs to PowerPC. It looks like the...
2010-05-24 Jakob Stoklund OlesenUse SubRegIndex in SystemZ.
2010-05-24 Jakob Stoklund OlesenSubRegIndex'ize Mips
2010-05-24 Jakob Stoklund OlesenSubRegIndex'ize MSP430
2010-05-24 Jakob Stoklund OlesenFix a few places that depended on the numeric value...
2010-05-24 Jakob Stoklund OlesenSwitch ARMRegisterInfo.td to use SubRegIndex and elimin...
2010-05-24 Jakob Stoklund OlesenRename X86 subregister indices to something shorter.
2010-05-24 Jakob Stoklund OlesenAdd the SubRegIndex TableGen class.
2010-05-23 Bob WilsonVDUP doesn't support vectors with 64-bit elements.
2010-05-22 Daniel DunbarMC/X86: Subdivide immediates a bit more, so that we...
2010-05-22 Daniel Dunbartblgen/AsmMatcher: Change AsmOperandClass to allow...
2010-05-22 Daniel DunbarMC/X86: Add alias for setz, setnz, jz, jnz.
2010-05-22 Evan ChengImplement @llvm.returnaddress. rdar://8015977.
2010-05-22 Jim GrosbachImplement eh.sjlj.longjmp for ARM. Clean up the intrins...
2010-05-22 Bob WilsonRecognize more BUILD_VECTORs and VECTOR_SHUFFLEs that...
2010-05-21 Chris Lattneradd a note
2010-05-21 Kevin EnderbyAdded retl for 32-bit x86 and added retq for 64-bit...
2010-05-21 Evan Cheng- Change MachineInstr::findRegisterDefOperandIdx so...
2010-05-21 Dale JohannesenPrevious commit message should refer to 104308.
2010-05-21 Dale JohannesenFix two bugs in 104348:
2010-05-21 Chris Lattnernow that fp reg kill insertion stuff happens as a separate
2010-05-21 Chris LattnerUse less evil form of switch stmt.
2010-05-21 Chris Lattneruse continue to reduce nesting.
2010-05-21 Chris Lattnerpull a nested loop of this pass out to its own function,
2010-05-21 Chris Lattnermodernize this pass a bit, fit in 80 columns.
2010-05-21 Matt FlemingCurrently, createMachOStreamer() is invoked directly...
2010-05-21 Matt FlemingSplit out the x86_32 an x86_64 ELF backends as they...
2010-05-21 Dale JohannesenFix i64->f64 conversion, x86-64, -no-sse. A bit
2010-05-21 Evan ChengChange ARM scheduling default to list-hybrid if the...
2010-05-20 Evan ChengAllow targets more controls on what nodes are scheduled...
2010-05-20 Daniel DunbarMC/X86: Add movq alias for movabsq, to allow matching...
2010-05-20 Daniel DunbarX86: Model i64i32imm properly, as a subclass of all...
2010-05-20 Daniel DunbarX86: Fix immediate type of FOO64i32 operations.
2010-05-20 Bob WilsonHandle Neon v2f64 and v2i64 vector shuffles as register...
2010-05-20 Dan GohmanDelete MMX_MOVQ64gmr. It was the same as MMX_MOVQ64mr...
2010-05-20 Dale JohannesenThe PPC MFCR instruction implicitly uses all 8 of the CR
2010-05-20 Dan GohmanFix assembly parsing and encoding of the pushf and...
2010-05-20 Dan GohmanSet neverHasSideEffects on 64-bit pushf and popf, for...
2010-05-20 Dan GohmanDefine the x86 pause instruction.
2010-05-20 Dan GohmanFix the sfence instruction to use MRM_F8 instead of...
2010-05-19 Evan ChengCode refactoring: pull SchedPreference enum from Target...
2010-05-19 Daniel DunbarMC/X86: Add missing entry for TAILJMP_1 to getRelaxedOp...
2010-05-19 Daniel DunbarMC/X86: Lower TAILCALLd[64] to JMP_1, to allow relaxati...
2010-05-19 Daniel DunbarMC/X86: Strip spurious operands from TAILJMPr64 as...
2010-05-19 Evan Chengt2LEApcrel and tLEApcrel are re-materializable. This...
2010-05-19 Evan ChengUse 'adr' for LEApcrel and LEApcrel. Mark LEApcrel...
2010-05-19 Daniel DunbarMC/X86: Lower MOV{8,16,32,64}{rm,mr} to fixed-register...
2010-05-19 Evan ChengMark pattern-less mayLoad / mayStore instructions never...
2010-05-19 Evan ChengTarget instruction selection should copy memoperands.
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