X86: Model i64i32imm properly, as a subclass of all immediates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104272 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp
index e6d546b33e7b35a1e789bb9963bb95435cceb455..479f4e43dfeb9d3562fb184f64ee4ec6bb7ea74d 100644 (file)
--- a/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -200,6 +200,20 @@ struct X86Operand : public MCParsedAsmOperand {
     return true;
   }
   
+  bool isImmSExt32() const {
+    // Accept immediates which fit in 32 bits when sign extended, and
+    // non-absolute immediates.
+    if (!isImm())
+      return false;
+
+    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
+      int64_t Value = CE->getValue();
+      return Value == (int64_t) (int32_t) Value;
+    }
+
+    return true;
+  }
+
   bool isMem() const { return Kind == Memory; }
 
   bool isAbsMem() const {
@@ -237,6 +251,12 @@ struct X86Operand : public MCParsedAsmOperand {
     addExpr(Inst, getImm());
   }
 
+  void addImmSExt32Operands(MCInst &Inst, unsigned N) const {
+    // FIXME: Support user customization of the render method.
+    assert(N == 1 && "Invalid number of operands!");
+    addExpr(Inst, getImm());
+  }
+
   void addMemOperands(MCInst &Inst, unsigned N) const {
     assert((N == 5) && "Invalid number of operands!");
     Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));

diff --git a/lib/Target/X86/X86Instr64bit.td b/lib/Target/X86/X86Instr64bit.td
index 36932813b34f6139a7614f8a73aa093c3a6d6591..3cbb2f5a8ce8e6ae648eb8d1884b3ba81538f369 100644 (file)
--- a/lib/Target/X86/X86Instr64bit.td
+++ b/lib/Target/X86/X86Instr64bit.td
@@ -18,7 +18,9 @@
 //
 
 // 64-bits but only 32 bits are significant.
-def i64i32imm  : Operand<i64>;
+def i64i32imm  : Operand<i64> {
+  let ParserMatchClass = ImmSExt32AsmOperand;
+}
 
 // 64-bits but only 32 bits are significant, and those bits are treated as being
 // pc relative.

diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index 502921647f8aad76370642a2361f3e87a885d12b..803ca2fe566d6c9407f042d25b9a2165c75874d1 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -270,9 +270,14 @@ def SSECC : Operand<i8> {
   let PrintMethod = "printSSECC";
 }
 
+def ImmSExt32AsmOperand : AsmOperandClass {
+  let Name = "ImmSExt32";
+  let SuperClass = ImmAsmOperand;
+}
+
 def ImmSExt8AsmOperand : AsmOperandClass {
   let Name = "ImmSExt8";
-  let SuperClass = ImmAsmOperand;
+  let SuperClass = ImmSExt32AsmOperand;
 }
 
 // A couple of more descriptive operand definitions.