1 //===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/Target/TargetAsmParser.h"
12 #include "llvm/ADT/SmallVector.h"
13 #include "llvm/ADT/StringSwitch.h"
14 #include "llvm/ADT/Twine.h"
15 #include "llvm/MC/MCStreamer.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCParser/MCAsmLexer.h"
19 #include "llvm/MC/MCParser/MCAsmParser.h"
20 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
21 #include "llvm/Support/SourceMgr.h"
22 #include "llvm/Target/TargetRegistry.h"
23 #include "llvm/Target/TargetAsmParser.h"
29 class X86ATTAsmParser : public TargetAsmParser {
36 MCAsmParser &getParser() const { return Parser; }
38 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
40 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
42 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
44 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
46 X86Operand *ParseOperand();
47 X86Operand *ParseMemOperand(unsigned SegReg, SMLoc StartLoc);
49 bool ParseDirectiveWord(unsigned Size, SMLoc L);
51 void InstructionCleanup(MCInst &Inst);
53 /// @name Auto-generated Match Functions
56 bool MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
59 bool MatchInstructionImpl(
60 const SmallVectorImpl<MCParsedAsmOperand*> &Operands, MCInst &Inst);
65 X86ATTAsmParser(const Target &T, MCAsmParser &_Parser)
66 : TargetAsmParser(T), Parser(_Parser) {}
68 virtual bool ParseInstruction(const StringRef &Name, SMLoc NameLoc,
69 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
71 virtual bool ParseDirective(AsmToken DirectiveID);
74 class X86_32ATTAsmParser : public X86ATTAsmParser {
76 X86_32ATTAsmParser(const Target &T, MCAsmParser &_Parser)
77 : X86ATTAsmParser(T, _Parser) {
82 class X86_64ATTAsmParser : public X86ATTAsmParser {
84 X86_64ATTAsmParser(const Target &T, MCAsmParser &_Parser)
85 : X86ATTAsmParser(T, _Parser) {
90 } // end anonymous namespace
92 /// @name Auto-generated Match Functions
95 static unsigned MatchRegisterName(StringRef Name);
101 /// X86Operand - Instances of this class represent a parsed X86 machine
103 struct X86Operand : public MCParsedAsmOperand {
111 SMLoc StartLoc, EndLoc;
136 X86Operand(KindTy K, SMLoc Start, SMLoc End)
137 : Kind(K), StartLoc(Start), EndLoc(End) {}
139 /// getStartLoc - Get the location of the first token of this operand.
140 SMLoc getStartLoc() const { return StartLoc; }
141 /// getEndLoc - Get the location of the last token of this operand.
142 SMLoc getEndLoc() const { return EndLoc; }
144 StringRef getToken() const {
145 assert(Kind == Token && "Invalid access!");
146 return StringRef(Tok.Data, Tok.Length);
148 void setTokenValue(StringRef Value) {
149 assert(Kind == Token && "Invalid access!");
150 Tok.Data = Value.data();
151 Tok.Length = Value.size();
154 unsigned getReg() const {
155 assert(Kind == Register && "Invalid access!");
159 const MCExpr *getImm() const {
160 assert(Kind == Immediate && "Invalid access!");
164 const MCExpr *getMemDisp() const {
165 assert(Kind == Memory && "Invalid access!");
168 unsigned getMemSegReg() const {
169 assert(Kind == Memory && "Invalid access!");
172 unsigned getMemBaseReg() const {
173 assert(Kind == Memory && "Invalid access!");
176 unsigned getMemIndexReg() const {
177 assert(Kind == Memory && "Invalid access!");
180 unsigned getMemScale() const {
181 assert(Kind == Memory && "Invalid access!");
185 bool isToken() const {return Kind == Token; }
187 bool isImm() const { return Kind == Immediate; }
189 bool isImmSExt8() const {
190 // Accept immediates which fit in 8 bits when sign extended, and
191 // non-absolute immediates.
195 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
196 int64_t Value = CE->getValue();
197 return Value == (int64_t) (int8_t) Value;
203 bool isMem() const { return Kind == Memory; }
205 bool isAbsMem() const {
206 return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
207 !getMemIndexReg() && getMemScale() == 1;
210 bool isNoSegMem() const {
211 return Kind == Memory && !getMemSegReg();
214 bool isReg() const { return Kind == Register; }
216 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
217 // Add as immediates when possible.
218 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
219 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
221 Inst.addOperand(MCOperand::CreateExpr(Expr));
224 void addRegOperands(MCInst &Inst, unsigned N) const {
225 assert(N == 1 && "Invalid number of operands!");
226 Inst.addOperand(MCOperand::CreateReg(getReg()));
229 void addImmOperands(MCInst &Inst, unsigned N) const {
230 assert(N == 1 && "Invalid number of operands!");
231 addExpr(Inst, getImm());
234 void addImmSExt8Operands(MCInst &Inst, unsigned N) const {
235 // FIXME: Support user customization of the render method.
236 assert(N == 1 && "Invalid number of operands!");
237 addExpr(Inst, getImm());
240 void addMemOperands(MCInst &Inst, unsigned N) const {
241 assert((N == 5) && "Invalid number of operands!");
242 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
243 Inst.addOperand(MCOperand::CreateImm(getMemScale()));
244 Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
245 addExpr(Inst, getMemDisp());
246 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
249 void addAbsMemOperands(MCInst &Inst, unsigned N) const {
250 assert((N == 1) && "Invalid number of operands!");
251 Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
254 void addNoSegMemOperands(MCInst &Inst, unsigned N) const {
255 assert((N == 4) && "Invalid number of operands!");
256 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
257 Inst.addOperand(MCOperand::CreateImm(getMemScale()));
258 Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
259 addExpr(Inst, getMemDisp());
262 static X86Operand *CreateToken(StringRef Str, SMLoc Loc) {
263 X86Operand *Res = new X86Operand(Token, Loc, Loc);
264 Res->Tok.Data = Str.data();
265 Res->Tok.Length = Str.size();
269 static X86Operand *CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc) {
270 X86Operand *Res = new X86Operand(Register, StartLoc, EndLoc);
271 Res->Reg.RegNo = RegNo;
275 static X86Operand *CreateImm(const MCExpr *Val, SMLoc StartLoc, SMLoc EndLoc){
276 X86Operand *Res = new X86Operand(Immediate, StartLoc, EndLoc);
281 /// Create an absolute memory operand.
282 static X86Operand *CreateMem(const MCExpr *Disp, SMLoc StartLoc,
284 X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
286 Res->Mem.Disp = Disp;
287 Res->Mem.BaseReg = 0;
288 Res->Mem.IndexReg = 0;
293 /// Create a generalized memory operand.
294 static X86Operand *CreateMem(unsigned SegReg, const MCExpr *Disp,
295 unsigned BaseReg, unsigned IndexReg,
296 unsigned Scale, SMLoc StartLoc, SMLoc EndLoc) {
297 // We should never just have a displacement, that should be parsed as an
298 // absolute memory operand.
299 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
301 // The scale should always be one of {1,2,4,8}.
302 assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
304 X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
305 Res->Mem.SegReg = SegReg;
306 Res->Mem.Disp = Disp;
307 Res->Mem.BaseReg = BaseReg;
308 Res->Mem.IndexReg = IndexReg;
309 Res->Mem.Scale = Scale;
314 } // end anonymous namespace.
317 bool X86ATTAsmParser::ParseRegister(unsigned &RegNo,
318 SMLoc &StartLoc, SMLoc &EndLoc) {
320 const AsmToken &TokPercent = Parser.getTok();
321 assert(TokPercent.is(AsmToken::Percent) && "Invalid token kind!");
322 StartLoc = TokPercent.getLoc();
323 Parser.Lex(); // Eat percent token.
325 const AsmToken &Tok = Parser.getTok();
326 if (Tok.isNot(AsmToken::Identifier))
327 return Error(Tok.getLoc(), "invalid register name");
329 // FIXME: Validate register for the current architecture; we have to do
330 // validation later, so maybe there is no need for this here.
331 RegNo = MatchRegisterName(Tok.getString());
333 // Parse %st(1) and "%st" as "%st(0)"
334 if (RegNo == 0 && Tok.getString() == "st") {
336 EndLoc = Tok.getLoc();
337 Parser.Lex(); // Eat 'st'
339 // Check to see if we have '(4)' after %st.
340 if (getLexer().isNot(AsmToken::LParen))
345 const AsmToken &IntTok = Parser.getTok();
346 if (IntTok.isNot(AsmToken::Integer))
347 return Error(IntTok.getLoc(), "expected stack index");
348 switch (IntTok.getIntVal()) {
349 case 0: RegNo = X86::ST0; break;
350 case 1: RegNo = X86::ST1; break;
351 case 2: RegNo = X86::ST2; break;
352 case 3: RegNo = X86::ST3; break;
353 case 4: RegNo = X86::ST4; break;
354 case 5: RegNo = X86::ST5; break;
355 case 6: RegNo = X86::ST6; break;
356 case 7: RegNo = X86::ST7; break;
357 default: return Error(IntTok.getLoc(), "invalid stack index");
360 if (getParser().Lex().isNot(AsmToken::RParen))
361 return Error(Parser.getTok().getLoc(), "expected ')'");
363 EndLoc = Tok.getLoc();
364 Parser.Lex(); // Eat ')'
369 return Error(Tok.getLoc(), "invalid register name");
371 EndLoc = Tok.getLoc();
372 Parser.Lex(); // Eat identifier token.
376 X86Operand *X86ATTAsmParser::ParseOperand() {
377 switch (getLexer().getKind()) {
379 // Parse a memory operand with no segment register.
380 return ParseMemOperand(0, Parser.getTok().getLoc());
381 case AsmToken::Percent: {
382 // Read the register.
385 if (ParseRegister(RegNo, Start, End)) return 0;
387 // If this is a segment register followed by a ':', then this is the start
388 // of a memory reference, otherwise this is a normal register reference.
389 if (getLexer().isNot(AsmToken::Colon))
390 return X86Operand::CreateReg(RegNo, Start, End);
393 getParser().Lex(); // Eat the colon.
394 return ParseMemOperand(RegNo, Start);
396 case AsmToken::Dollar: {
398 SMLoc Start = Parser.getTok().getLoc(), End;
401 if (getParser().ParseExpression(Val, End))
403 return X86Operand::CreateImm(Val, Start, End);
408 /// ParseMemOperand: segment: disp(basereg, indexreg, scale). The '%ds:' prefix
409 /// has already been parsed if present.
410 X86Operand *X86ATTAsmParser::ParseMemOperand(unsigned SegReg, SMLoc MemStart) {
412 // We have to disambiguate a parenthesized expression "(4+5)" from the start
413 // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
414 // only way to do this without lookahead is to eat the '(' and see what is
416 const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
417 if (getLexer().isNot(AsmToken::LParen)) {
419 if (getParser().ParseExpression(Disp, ExprEnd)) return 0;
421 // After parsing the base expression we could either have a parenthesized
422 // memory address or not. If not, return now. If so, eat the (.
423 if (getLexer().isNot(AsmToken::LParen)) {
424 // Unless we have a segment register, treat this as an immediate.
426 return X86Operand::CreateMem(Disp, MemStart, ExprEnd);
427 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
433 // Okay, we have a '('. We don't know if this is an expression or not, but
434 // so we have to eat the ( to see beyond it.
435 SMLoc LParenLoc = Parser.getTok().getLoc();
436 Parser.Lex(); // Eat the '('.
438 if (getLexer().is(AsmToken::Percent) || getLexer().is(AsmToken::Comma)) {
439 // Nothing to do here, fall into the code below with the '(' part of the
440 // memory operand consumed.
444 // It must be an parenthesized expression, parse it now.
445 if (getParser().ParseParenExpression(Disp, ExprEnd))
448 // After parsing the base expression we could either have a parenthesized
449 // memory address or not. If not, return now. If so, eat the (.
450 if (getLexer().isNot(AsmToken::LParen)) {
451 // Unless we have a segment register, treat this as an immediate.
453 return X86Operand::CreateMem(Disp, LParenLoc, ExprEnd);
454 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
462 // If we reached here, then we just ate the ( of the memory operand. Process
463 // the rest of the memory operand.
464 unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
466 if (getLexer().is(AsmToken::Percent)) {
468 if (ParseRegister(BaseReg, L, L)) return 0;
471 if (getLexer().is(AsmToken::Comma)) {
472 Parser.Lex(); // Eat the comma.
474 // Following the comma we should have either an index register, or a scale
475 // value. We don't support the later form, but we want to parse it
478 // Not that even though it would be completely consistent to support syntax
479 // like "1(%eax,,1)", the assembler doesn't.
480 if (getLexer().is(AsmToken::Percent)) {
482 if (ParseRegister(IndexReg, L, L)) return 0;
484 if (getLexer().isNot(AsmToken::RParen)) {
485 // Parse the scale amount:
486 // ::= ',' [scale-expression]
487 if (getLexer().isNot(AsmToken::Comma)) {
488 Error(Parser.getTok().getLoc(),
489 "expected comma in scale expression");
492 Parser.Lex(); // Eat the comma.
494 if (getLexer().isNot(AsmToken::RParen)) {
495 SMLoc Loc = Parser.getTok().getLoc();
498 if (getParser().ParseAbsoluteExpression(ScaleVal))
501 // Validate the scale amount.
502 if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8){
503 Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
506 Scale = (unsigned)ScaleVal;
509 } else if (getLexer().isNot(AsmToken::RParen)) {
510 // Otherwise we have the unsupported form of a scale amount without an
512 SMLoc Loc = Parser.getTok().getLoc();
515 if (getParser().ParseAbsoluteExpression(Value))
518 Error(Loc, "cannot have scale factor without index register");
523 // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
524 if (getLexer().isNot(AsmToken::RParen)) {
525 Error(Parser.getTok().getLoc(), "unexpected token in memory operand");
528 SMLoc MemEnd = Parser.getTok().getLoc();
529 Parser.Lex(); // Eat the ')'.
531 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
535 bool X86ATTAsmParser::
536 ParseInstruction(const StringRef &Name, SMLoc NameLoc,
537 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
538 // The various flavors of pushf and popf use Requires<In32BitMode> and
539 // Requires<In64BitMode>, but the assembler doesn't yet implement that.
540 // For now, just do a manual check to prevent silent misencoding.
543 return Error(NameLoc, "popfl cannot be encoded in 64-bit mode");
544 else if (Name == "pushfl")
545 return Error(NameLoc, "pushfl cannot be encoded in 64-bit mode");
548 return Error(NameLoc, "popfq cannot be encoded in 32-bit mode");
549 else if (Name == "pushfq")
550 return Error(NameLoc, "pushfq cannot be encoded in 32-bit mode");
553 // FIXME: Hack to recognize "sal..." and "rep..." for now. We need a way to
554 // represent alternative syntaxes in the .td file, without requiring
555 // instruction duplication.
556 StringRef PatchedName = StringSwitch<StringRef>(Name)
558 .Case("salb", "shlb")
559 .Case("sall", "shll")
560 .Case("salq", "shlq")
561 .Case("salw", "shlw")
564 .Case("repnz", "repne")
565 .Case("pushf", Is64Bit ? "pushfq" : "pushfl")
566 .Case("popf", Is64Bit ? "popfq" : "popfl")
568 Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
570 if (getLexer().isNot(AsmToken::EndOfStatement)) {
572 // Parse '*' modifier.
573 if (getLexer().is(AsmToken::Star)) {
574 SMLoc Loc = Parser.getTok().getLoc();
575 Operands.push_back(X86Operand::CreateToken("*", Loc));
576 Parser.Lex(); // Eat the star.
579 // Read the first operand.
580 if (X86Operand *Op = ParseOperand())
581 Operands.push_back(Op);
585 while (getLexer().is(AsmToken::Comma)) {
586 Parser.Lex(); // Eat the comma.
588 // Parse and remember the operand.
589 if (X86Operand *Op = ParseOperand())
590 Operands.push_back(Op);
596 // FIXME: Hack to handle recognizing s{hr,ar,hl}? $1.
597 if ((Name.startswith("shr") || Name.startswith("sar") ||
598 Name.startswith("shl")) &&
599 Operands.size() == 3 &&
600 static_cast<X86Operand*>(Operands[1])->isImm() &&
601 isa<MCConstantExpr>(static_cast<X86Operand*>(Operands[1])->getImm()) &&
602 cast<MCConstantExpr>(static_cast<X86Operand*>(Operands[1])->getImm())->getValue() == 1) {
604 Operands.erase(Operands.begin() + 1);
610 bool X86ATTAsmParser::ParseDirective(AsmToken DirectiveID) {
611 StringRef IDVal = DirectiveID.getIdentifier();
612 if (IDVal == ".word")
613 return ParseDirectiveWord(2, DirectiveID.getLoc());
617 /// ParseDirectiveWord
618 /// ::= .word [ expression (, expression)* ]
619 bool X86ATTAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
620 if (getLexer().isNot(AsmToken::EndOfStatement)) {
623 if (getParser().ParseExpression(Value))
626 getParser().getStreamer().EmitValue(Value, Size, 0 /*addrspace*/);
628 if (getLexer().is(AsmToken::EndOfStatement))
631 // FIXME: Improve diagnostic.
632 if (getLexer().isNot(AsmToken::Comma))
633 return Error(L, "unexpected token in directive");
642 /// LowerMOffset - Lower an 'moffset' form of an instruction, which just has a
643 /// imm operand, to having "rm" or "mr" operands with the offset in the disp
645 static void LowerMOffset(MCInst &Inst, unsigned Opc, unsigned RegNo,
647 MCOperand Disp = Inst.getOperand(0);
649 // Start over with an empty instruction.
654 Inst.addOperand(MCOperand::CreateReg(RegNo));
656 // Add the mem operand.
657 Inst.addOperand(MCOperand::CreateReg(0)); // Segment
658 Inst.addOperand(MCOperand::CreateImm(1)); // Scale
659 Inst.addOperand(MCOperand::CreateReg(0)); // IndexReg
660 Inst.addOperand(Disp); // Displacement
661 Inst.addOperand(MCOperand::CreateReg(0)); // BaseReg
664 Inst.addOperand(MCOperand::CreateReg(RegNo));
667 // FIXME: Custom X86 cleanup function to implement a temporary hack to handle
668 // matching INCL/DECL correctly for x86_64. This needs to be replaced by a
669 // proper mechanism for supporting (ambiguous) feature dependent instructions.
670 void X86ATTAsmParser::InstructionCleanup(MCInst &Inst) {
671 if (!Is64Bit) return;
673 switch (Inst.getOpcode()) {
674 case X86::DEC16r: Inst.setOpcode(X86::DEC64_16r); break;
675 case X86::DEC16m: Inst.setOpcode(X86::DEC64_16m); break;
676 case X86::DEC32r: Inst.setOpcode(X86::DEC64_32r); break;
677 case X86::DEC32m: Inst.setOpcode(X86::DEC64_32m); break;
678 case X86::INC16r: Inst.setOpcode(X86::INC64_16r); break;
679 case X86::INC16m: Inst.setOpcode(X86::INC64_16m); break;
680 case X86::INC32r: Inst.setOpcode(X86::INC64_32r); break;
681 case X86::INC32m: Inst.setOpcode(X86::INC64_32m); break;
683 // moffset instructions are x86-32 only.
684 case X86::MOV8o8a: LowerMOffset(Inst, X86::MOV8rm , X86::AL , false); break;
685 case X86::MOV16o16a: LowerMOffset(Inst, X86::MOV16rm, X86::AX , false); break;
686 case X86::MOV32o32a: LowerMOffset(Inst, X86::MOV32rm, X86::EAX, false); break;
687 case X86::MOV8ao8: LowerMOffset(Inst, X86::MOV8mr , X86::AL , true); break;
688 case X86::MOV16ao16: LowerMOffset(Inst, X86::MOV16mr, X86::AX , true); break;
689 case X86::MOV32ao32: LowerMOffset(Inst, X86::MOV32mr, X86::EAX, true); break;
694 X86ATTAsmParser::MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*>
697 // First, try a direct match.
698 if (!MatchInstructionImpl(Operands, Inst))
701 // Ignore anything which is obviously not a suffix match.
702 if (Operands.size() == 0)
704 X86Operand *Op = static_cast<X86Operand*>(Operands[0]);
705 if (!Op->isToken() || Op->getToken().size() > 15)
708 // FIXME: Ideally, we would only attempt suffix matches for things which are
709 // valid prefixes, and we could just infer the right unambiguous
710 // type. However, that requires substantially more matcher support than the
713 // Change the operand to point to a temporary token.
715 StringRef Base = Op->getToken();
716 memcpy(Tmp, Base.data(), Base.size());
717 Op->setTokenValue(StringRef(Tmp, Base.size() + 1));
719 // Check for the various suffix matches.
720 Tmp[Base.size()] = 'b';
721 bool MatchB = MatchInstructionImpl(Operands, Inst);
722 Tmp[Base.size()] = 'w';
723 bool MatchW = MatchInstructionImpl(Operands, Inst);
724 Tmp[Base.size()] = 'l';
725 bool MatchL = MatchInstructionImpl(Operands, Inst);
726 Tmp[Base.size()] = 'q';
727 bool MatchQ = MatchInstructionImpl(Operands, Inst);
729 // Restore the old token.
730 Op->setTokenValue(Base);
732 // If exactly one matched, then we treat that as a successful match (and the
733 // instruction will already have been filled in correctly, since the failing
734 // matches won't have modified it).
735 if (MatchB + MatchW + MatchL + MatchQ == 3)
738 // Otherwise, the match failed.
743 extern "C" void LLVMInitializeX86AsmLexer();
745 // Force static initialization.
746 extern "C" void LLVMInitializeX86AsmParser() {
747 RegisterAsmParser<X86_32ATTAsmParser> X(TheX86_32Target);
748 RegisterAsmParser<X86_64ATTAsmParser> Y(TheX86_64Target);
749 LLVMInitializeX86AsmLexer();
752 #include "X86GenAsmMatcher.inc"