Replace the tablegen RegisterClass field SubRegClassList with an alist-like data
authorJakob Stoklund Olesen <stoklund@2pi.dk>
Mon, 24 May 2010 21:46:58 +0000 (21:46 +0000)
committerJakob Stoklund Olesen <stoklund@2pi.dk>
Mon, 24 May 2010 21:46:58 +0000 (21:46 +0000)
commit09bc0298650c76db1a06e20ca84c1dcb34071600
tree6fb4e150957445020262c64bacf93e4a91b5705a
parent3946043a80a043b3cf43b34bf068feaadc46485b
Replace the tablegen RegisterClass field SubRegClassList with an alist-like data
structure that represents a mapping without any dependencies on SubRegIndex
numbering.

This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8
13 files changed:
include/llvm/Target/Target.td
include/llvm/Target/TargetRegisterInfo.h
lib/Target/ARM/ARMRegisterInfo.td
lib/Target/Blackfin/BlackfinRegisterInfo.td
lib/Target/MSP430/MSP430RegisterInfo.td
lib/Target/Mips/MipsRegisterInfo.td
lib/Target/PowerPC/PPCRegisterInfo.td
lib/Target/SystemZ/SystemZRegisterInfo.td
lib/Target/X86/X86RegisterInfo.td
utils/TableGen/CodeGenRegisters.h
utils/TableGen/CodeGenTarget.cpp
utils/TableGen/CodeGenTarget.h
utils/TableGen/RegisterInfoEmitter.cpp