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R600/SI: Add missing SOP1 instructions
[oota-llvm.git]
/
lib
/
Target
/
R600
/
SIInstructions.td
2015-02-18
Tom Stellard
R600/SI: Add missing SOP1 instructions
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2015-02-18
Matt Arsenault
R600/SI: Fix not setting clamp / omod for v_cndmask_b32_e64
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2015-02-18
Matt Arsenault
R600/SI: Add missing offset operand to buffer bothen
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2015-02-14
Matt Arsenault
R600/SI: Implement correct f64 fdiv
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2015-02-14
Matt Arsenault
R600/SI: Fix implicit vcc operand to v_div_fmas_*
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2015-02-14
Matt Arsenault
R600/SI: Fix schedule model for v_div_scale_{f32|f64}
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2015-02-11
Tom Stellard
R600/SI: Add soffset operand to mubuf addr64 instruction
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2015-02-06
Michel Danzer
R600/SI: Also enable WQM for image opcodes which calcul...
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2015-02-05
Matt Arsenault
R600/SI: Fix i64 truncate to i1
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2015-02-03
Marek Olsak
R600/SI: Remove useless patterns in VALU which are...
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2015-02-03
Marek Olsak
R600/SI: Fix B64 VALU shifts on VI
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2015-02-03
Marek Olsak
R600/SI: Don't generate non-existent LSHL, LSHR, ASHR...
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2015-02-03
Marek Olsak
R600/SI: Remove VOP2_REV definitions from target-specif...
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2015-02-03
Marek Olsak
R600/SI: Trivial instruction definition corrections...
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2015-01-30
Eric Christopher
Reuse a bunch of cached subtargets and remove getSubtar...
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2015-01-27
Marek Olsak
R600/SI: Fix MIN3/MAX3 on VI, define MED3
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2015-01-27
Marek Olsak
R600/SI: Add VI versions of LDS atomics
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2015-01-27
Marek Olsak
R600/SI: Add VI versions of MUBUF atomics
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2015-01-27
Marek Olsak
R600/SI: Add VI versions of MUBUF loads and stores
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2015-01-20
Tom Stellard
R600/SI: Use external symbols for scratch buffer
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2015-01-15
Matt Arsenault
R600/SI: Add patterns for v_cvt_{flr|rpi}_i32_f32
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2015-01-15
Marek Olsak
R600/SI: Unify VOP2 instructions which are VOP3-only...
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2015-01-15
Marek Olsak
R600/SI: Use 64-bit encoding by default for opcodes...
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2015-01-15
Marek Olsak
R600/SI: Add V_READLANE_B32 and V_WRITELANE_B32 for VI
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2015-01-15
Marek Olsak
R600/SI: Don't select SI-only VOP3 opcodes on VI
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2015-01-14
Tom Stellard
R600/SI: Spill VGPRs to scratch space for compute shaders
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2015-01-14
Tom Stellard
R600/SI: Define a schedule model
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2015-01-13
Tom Stellard
R600/SI: Add pattern for bitcasting fp immediates to...
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2015-01-07
Tom Stellard
R600/SI: Remove VReg_32 register class
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2015-01-07
Tom Stellard
R600/SI: Add a V_MOV_B64 pseudo instruction
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2015-01-06
Matt Arsenault
R600/SI: Add class intrinsic
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2014-12-17
Matt Arsenault
R600/SI: Fix f64 inline immediates
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2014-12-12
Matt Arsenault
R600: Fix min/max matching problems with unordered...
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2014-12-12
Matt Arsenault
R600/SI: Don't promote f32 select to i32
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2014-12-11
Matt Arsenault
R600/SI: Use unordered equal instructions
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2014-12-11
Matt Arsenault
R600/SI: Make more unordered comparisons legal
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2014-12-11
Matt Arsenault
R600/SI: Use unordered not equal instructions
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2014-12-07
Marek Olsak
R600/SI: Set 20-bit immediate byte offset for SMRD...
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2014-12-07
Marek Olsak
R600/SI: Add VI instructions
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2014-12-07
Marek Olsak
R600/SI: Add SCC Defs/Uses to SOP1 and SOP2 opcodes
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2014-12-03
Matt Arsenault
R600/SI: Remove i1 pseudo VALU ops
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2014-11-25
Chandler Carruth
Revert r222746: That commit did not update any tests...
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2014-11-25
Marek Olsak
R600/SI: Disable commutativity for MIN/MAX_LEGACY
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2014-11-21
Tom Stellard
R600/SI: Add an s_mov_b32 to patterns which use the...
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2014-11-21
Tom Stellard
R600/SI: Emit s_mov_b32 m0, -1 before every DS instruction
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2014-11-21
Tom Stellard
R600/SI: Mark s_mov_b32 and s_mov_b64 as rematerializable
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2014-11-14
Tom Stellard
R600/SI: Mark s_movk_i32 as rematerializable
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2014-11-14
Matt Arsenault
R600/SI: Combine min3/max3 instructions
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2014-11-14
Matt Arsenault
R600/SI: Use S_BFE_I64 for 64-bit sext_inreg
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2014-11-14
Tom Stellard
R600/SI: Start implementing an assembler
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2014-11-13
Matt Arsenault
R600/SI: Fix fmin_legacy / fmax_legacy matching for SI
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2014-11-13
Matt Arsenault
R600/SI: Fix definition for s_cselect_b32
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2014-11-13
Matt Arsenault
R600/SI: Get rid of FCLAMP_SI pseudo
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2014-11-13
Matt Arsenault
R600/SI: Allow commuting some 3 op instructions
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2014-11-05
Matt Arsenault
R600/SI: Remove SI_ADDR64_RSRC
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2014-11-05
Tom Stellard
R600/SI: Change all instruction assembly names to lower...
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2014-11-02
Matt Arsenault
R600/SI: Use REG_SEQUENCE instead of INSERT_SUBREGs
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2014-11-02
Matt Arsenault
Support REG_SEQUENCE in tablegen.
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2014-10-21
Matt Arsenault
Add minnum / maxnum codegen
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2014-10-21
Matt Arsenault
R600/SI: Add pattern for bswap
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2014-10-17
Aaron Watry
R600/SI: Add global atomicrmw xchg
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2014-10-17
Aaron Watry
R600/SI: Add global atomicrmw xor
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2014-10-17
Aaron Watry
R600/SI: Add global atomicrmw or
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2014-10-17
Aaron Watry
R600/SI: Add global atomicrmw min/umin
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2014-10-17
Aaron Watry
R600/SI: Add global atomicrmw max/umax
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2014-10-17
Aaron Watry
R600/SI: Add global atomicrmw and
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2014-10-17
Aaron Watry
R600/SI: Add global atomicrmw sub
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2014-10-17
Matt Arsenault
R600/SI: Remove redundant setting of instruction bits
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2014-10-17
Matt Arsenault
R600/SI: Use complex pattern for MUBUF load patterns.
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2014-10-17
Matt Arsenault
R600/SI: Remove SI_BUFFER_RSRC pseudo
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2014-10-16
Matt Arsenault
R600/SI: Remove another VALU pattern
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2014-10-16
Matt Arsenault
R600/SI: Remove unnecessary VALU patterns
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2014-10-07
Tom Stellard
R600/SI: Refactor VOP3 instruction defs
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2014-10-07
Tom Stellard
R600/SI: Refactor VOPC instruction defs
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2014-10-07
Tom Stellard
R600/SI: Refactor VOP2 instruction defs
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2014-10-07
Tom Stellard
R600/SI: Refactor VOP1 instruction defs
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2014-10-01
Tom Stellard
R600/SI: Add a generic pseudo EXP instruction
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2014-10-01
Tom Stellard
R600/SI: Add generic pseudo MTBUF instructions
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2014-09-25
Tom Stellard
R600/SI: Add support for global atomic add
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2014-09-24
Tom Stellard
R600/SI: Enable selecting SALU inside branches
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2014-09-24
Tom Stellard
R600/SI: Fix the FixSGPRLiveRanges pass
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2014-09-24
Tom Stellard
R600/SI: Implement VGPR register spilling for compute...
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2014-09-22
Tom Stellard
Revert "R600/SI: Add support for global atomic add"
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2014-09-22
Tom Stellard
R600/SI: Add support for global atomic add
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2014-09-22
Tom Stellard
R600/SI: Remove modifier operands from V_CNDMASK_B32_e64
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2014-09-15
Matt Arsenault
R600/SI: Prefer selecting more e64 instruction forms.
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2014-09-15
Matt Arsenault
R600/SI: Add preliminary support for flat address space
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2014-09-08
Matt Arsenault
R600/SI: Replace LDS atomics with no return versions
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2014-09-08
Matt Arsenault
R600/SI: Add InstrMapping for noret atomics.
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2014-09-07
Matt Arsenault
R600/SI: Fix register class for some 64-bit atomics
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2014-09-05
Matt Arsenault
R600/SI: Use same complex patterns for DS atomics
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2014-09-05
Tom Stellard
R600/SI: Use S_ADD_U32 and S_SUB_U32 for low half of...
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2014-09-03
Matt Arsenault
R600/SI: Un-move pattern I forgot to remove in last...
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2014-09-03
Matt Arsenault
R600/SI: Try to keep i32 mul on SALU
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2014-09-03
Tom Stellard
R600/SI: Add a pattern for i64 and in a branch
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2014-08-29
Matt Arsenault
R600/SI: Use mad for fsub + fmul
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2014-08-22
Tom Stellard
R600/SI: Use READ2/WRITE2 instructions for 64-bit mem...
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2014-08-22
Tom Stellard
R600/SI: Use a ComplexPattern for DS loads and stores
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2014-08-21
Tom Stellard
R600/SI: Use eliminateFrameIndex() to expand SGPR spill...
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2014-08-15
Matt Arsenault
R600/SI: Move all fabs / fneg handling to patterns
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