R600/SI: Remove redundant unsetting of hasSideEffects
[oota-llvm.git] / lib / Target / R600 / SIInstructions.td
2015-03-23 Matt ArsenaultR600/SI: Remove redundant unsetting of hasSideEffects
2015-03-23 Matt ArsenaultR600/SI: Move hasSideEffects setting into VOPCX classes
2015-03-23 Matt ArsenaultR600/SI: Allow commuting compares
2015-03-23 Matt ArsenaultR600/SI: Use right class for cmpsx f64 instructions
2015-03-20 Craig Topper[Tablegen] Attempt to add support for patterns containi...
2015-03-12 Tom StellardR600/SI: Remove _e32 and _e64 suffixes from mnemonics
2015-03-10 Tom StellardR600/SI: Re-order MUBUF operands to match asm strings.
2015-03-10 Tom StellardR600/SI: Add 32-bit encoding of v_cndmask_b32
2015-03-09 Tom StellardR600/SI: Move gds operand to the end of operand list
2015-03-09 Tom StellardR600/SI: Refactor DS instruction defs
2015-03-09 Tom StellardR600/SI: Fix DS definitions and add missing instructions
2015-03-09 Tom StellardR600/SI: Fix opcode for ds_read2_b64 and ds_read2st64_b64
2015-03-04 Marek OlsakR600/SI: Add an intrinsic for S_FLBIT_I32 / V_FFBH_I32
2015-02-27 Tom StellardR600/SI: Add missing mubuf instructions
2015-02-27 Tom StellardR600/SI: Consistently put soffset before the offset...
2015-02-27 Tom StellardR600/SI: Add slc, glc, and tfe to non-atomic _ADDR64...
2015-02-21 Matt ArsenaultR600/SI: Fix mad*k definitions
2015-02-20 Matt ArsenaultR600/SI: Remove v_sub_f64 pseudo
2015-02-20 Matt ArsenaultR600: Use new fmad node.
2015-02-18 Marek OlsakR600/SI: Fix READLANE and WRITELANE lane select for VI
2015-02-18 Tom StellardR600/SI: Add missing VOP1 instructions
2015-02-18 Tom StellardR600/SI: Add missing VOP2 instructions
2015-02-18 Tom StellardR600/SI: Add definition for S_CBRANCH_G_FORK
2015-02-18 Tom StellardR600/SI: Add missing SOP1 instructions
2015-02-18 Matt ArsenaultR600/SI: Fix not setting clamp / omod for v_cndmask_b32_e64
2015-02-18 Matt ArsenaultR600/SI: Add missing offset operand to buffer bothen
2015-02-14 Matt ArsenaultR600/SI: Implement correct f64 fdiv
2015-02-14 Matt ArsenaultR600/SI: Fix implicit vcc operand to v_div_fmas_*
2015-02-14 Matt ArsenaultR600/SI: Fix schedule model for v_div_scale_{f32|f64}
2015-02-11 Tom StellardR600/SI: Add soffset operand to mubuf addr64 instruction
2015-02-06 Michel DanzerR600/SI: Also enable WQM for image opcodes which calcul...
2015-02-05 Matt ArsenaultR600/SI: Fix i64 truncate to i1
2015-02-03 Marek OlsakR600/SI: Remove useless patterns in VALU which are...
2015-02-03 Marek OlsakR600/SI: Fix B64 VALU shifts on VI
2015-02-03 Marek OlsakR600/SI: Don't generate non-existent LSHL, LSHR, ASHR...
2015-02-03 Marek OlsakR600/SI: Remove VOP2_REV definitions from target-specif...
2015-02-03 Marek OlsakR600/SI: Trivial instruction definition corrections...
2015-01-30 Eric ChristopherReuse a bunch of cached subtargets and remove getSubtar...
2015-01-27 Marek OlsakR600/SI: Fix MIN3/MAX3 on VI, define MED3
2015-01-27 Marek OlsakR600/SI: Add VI versions of LDS atomics
2015-01-27 Marek OlsakR600/SI: Add VI versions of MUBUF atomics
2015-01-27 Marek OlsakR600/SI: Add VI versions of MUBUF loads and stores
2015-01-20 Tom StellardR600/SI: Use external symbols for scratch buffer
2015-01-15 Matt ArsenaultR600/SI: Add patterns for v_cvt_{flr|rpi}_i32_f32
2015-01-15 Marek OlsakR600/SI: Unify VOP2 instructions which are VOP3-only...
2015-01-15 Marek OlsakR600/SI: Use 64-bit encoding by default for opcodes...
2015-01-15 Marek OlsakR600/SI: Add V_READLANE_B32 and V_WRITELANE_B32 for VI
2015-01-15 Marek OlsakR600/SI: Don't select SI-only VOP3 opcodes on VI
2015-01-14 Tom StellardR600/SI: Spill VGPRs to scratch space for compute shaders
2015-01-14 Tom StellardR600/SI: Define a schedule model
2015-01-13 Tom StellardR600/SI: Add pattern for bitcasting fp immediates to...
2015-01-07 Tom StellardR600/SI: Remove VReg_32 register class
2015-01-07 Tom StellardR600/SI: Add a V_MOV_B64 pseudo instruction
2015-01-06 Matt ArsenaultR600/SI: Add class intrinsic
2014-12-17 Matt ArsenaultR600/SI: Fix f64 inline immediates
2014-12-12 Matt ArsenaultR600: Fix min/max matching problems with unordered...
2014-12-12 Matt ArsenaultR600/SI: Don't promote f32 select to i32
2014-12-11 Matt ArsenaultR600/SI: Use unordered equal instructions
2014-12-11 Matt ArsenaultR600/SI: Make more unordered comparisons legal
2014-12-11 Matt ArsenaultR600/SI: Use unordered not equal instructions
2014-12-07 Marek OlsakR600/SI: Set 20-bit immediate byte offset for SMRD...
2014-12-07 Marek OlsakR600/SI: Add VI instructions
2014-12-07 Marek OlsakR600/SI: Add SCC Defs/Uses to SOP1 and SOP2 opcodes
2014-12-03 Matt ArsenaultR600/SI: Remove i1 pseudo VALU ops
2014-11-25 Chandler CarruthRevert r222746: That commit did not update any tests...
2014-11-25 Marek OlsakR600/SI: Disable commutativity for MIN/MAX_LEGACY
2014-11-21 Tom StellardR600/SI: Add an s_mov_b32 to patterns which use the...
2014-11-21 Tom StellardR600/SI: Emit s_mov_b32 m0, -1 before every DS instruction
2014-11-21 Tom StellardR600/SI: Mark s_mov_b32 and s_mov_b64 as rematerializable
2014-11-14 Tom StellardR600/SI: Mark s_movk_i32 as rematerializable
2014-11-14 Matt ArsenaultR600/SI: Combine min3/max3 instructions
2014-11-14 Matt ArsenaultR600/SI: Use S_BFE_I64 for 64-bit sext_inreg
2014-11-14 Tom StellardR600/SI: Start implementing an assembler
2014-11-13 Matt ArsenaultR600/SI: Fix fmin_legacy / fmax_legacy matching for SI
2014-11-13 Matt ArsenaultR600/SI: Fix definition for s_cselect_b32
2014-11-13 Matt ArsenaultR600/SI: Get rid of FCLAMP_SI pseudo
2014-11-13 Matt ArsenaultR600/SI: Allow commuting some 3 op instructions
2014-11-05 Matt ArsenaultR600/SI: Remove SI_ADDR64_RSRC
2014-11-05 Tom StellardR600/SI: Change all instruction assembly names to lower...
2014-11-02 Matt ArsenaultR600/SI: Use REG_SEQUENCE instead of INSERT_SUBREGs
2014-11-02 Matt ArsenaultSupport REG_SEQUENCE in tablegen.
2014-10-21 Matt ArsenaultAdd minnum / maxnum codegen
2014-10-21 Matt ArsenaultR600/SI: Add pattern for bswap
2014-10-17 Aaron WatryR600/SI: Add global atomicrmw xchg
2014-10-17 Aaron WatryR600/SI: Add global atomicrmw xor
2014-10-17 Aaron WatryR600/SI: Add global atomicrmw or
2014-10-17 Aaron WatryR600/SI: Add global atomicrmw min/umin
2014-10-17 Aaron WatryR600/SI: Add global atomicrmw max/umax
2014-10-17 Aaron WatryR600/SI: Add global atomicrmw and
2014-10-17 Aaron WatryR600/SI: Add global atomicrmw sub
2014-10-17 Matt ArsenaultR600/SI: Remove redundant setting of instruction bits
2014-10-17 Matt ArsenaultR600/SI: Use complex pattern for MUBUF load patterns.
2014-10-17 Matt ArsenaultR600/SI: Remove SI_BUFFER_RSRC pseudo
2014-10-16 Matt ArsenaultR600/SI: Remove another VALU pattern
2014-10-16 Matt ArsenaultR600/SI: Remove unnecessary VALU patterns
2014-10-07 Tom StellardR600/SI: Refactor VOP3 instruction defs
2014-10-07 Tom StellardR600/SI: Refactor VOPC instruction defs
2014-10-07 Tom StellardR600/SI: Refactor VOP2 instruction defs
2014-10-07 Tom StellardR600/SI: Refactor VOP1 instruction defs
2014-10-01 Tom StellardR600/SI: Add a generic pseudo EXP instruction
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