R600/SI: Fix READLANE and WRITELANE lane select for VI
authorMarek Olsak <marek.olsak@amd.com>
Wed, 18 Feb 2015 22:12:45 +0000 (22:12 +0000)
committerMarek Olsak <marek.olsak@amd.com>
Wed, 18 Feb 2015 22:12:45 +0000 (22:12 +0000)
commit4f5a891372beec6bb848be78aa3337688f326390
tree37832dab98ee742324ad8a9232c66bd9c0219614
parent2a0d0dedf0c419256c2827f4e8506237e087a09e
R600/SI: Fix READLANE and WRITELANE lane select for VI

VOP2 declares vsrc1, but VOP3 declares src1.
We can't use the same "ins" if the operands have different names in VOP2
and VOP3 encodings.

This fixes a hang in geometry shaders which spill M0 on VI.
(BTW it doesn't look like M0 needs spilling and the spilling seems
duplicated 3 times)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229752 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/R600/SIInstrFormats.td
lib/Target/R600/SIInstructions.td