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Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since...
[oota-llvm.git]
/
lib
/
Target
/
Hexagon
/
HexagonInstrInfo.cpp
2012-04-20
Craig Topper
Convert more uses of XXXRegisterClass to &XXXRegClass...
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2012-04-18
Chandler Carruth
This reverts a long string of commits to the Hexagon...
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2012-04-16
Sirish Pande
Hexagon V5 (Floating Point) Support.
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2012-04-13
Sirish Pande
Add support for Hexagon Architectural feature, New...
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2012-04-13
Craig Topper
Silence various build warnings from Hexagon backend...
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2012-04-12
Sirish Pande
HexagonPacketizer patch.
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2012-04-12
Evandro Menezes
Hexagon: enable assembler output through the MC layer.
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2012-03-17
Craig Topper
Reorder includes in Target backends to following coding...
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2012-02-22
Sirish Pande
Efficient pattern for store truncate. Patch by Evandro...
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2012-02-18
Jia Liu
Emacs-tag and some comment fix for all ARM, CellSPU...
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2012-02-15
Sirish Pande
Optimize redundant sign extends and negation of predicates.
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2012-02-15
Eric Christopher
Revert "Optimize redundant sign extends and negation...
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2012-02-15
Sirish Pande
Optimize redundant sign extends and negation of predicates
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2012-02-08
Brendon Cahoon
Use TSFlag bit to describe instruction properties.
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2012-02-07
Craig Topper
Convert assert(0) to llvm_unreachable
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2012-02-06
Benjamin Kramer
Hexagon: Remove forbidden iostream includes (it introdu...
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2012-02-01
Andrew Trick
VLIW specific scheduler framework that utilizes determi...
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2012-01-20
David Blaikie
More dead code removal (using -Wunreachable-code)
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2011-12-27
Benjamin Kramer
Clean up some Release build warnings.
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2011-12-15
Tony Linthicum
Add MCTargetDesc library to Hexagon target
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2011-12-12
Tony Linthicum
Hexagon backend support
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