1 //===- HexagonInstrInfo.cpp - Hexagon Instruction Information -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonRegisterInfo.h"
15 #include "HexagonInstrInfo.h"
16 #include "HexagonSubtarget.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/DFAPacketizer.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineMemOperand.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Support/MathExtras.h"
27 #define GET_INSTRINFO_CTOR
28 #include "HexagonGenInstrInfo.inc"
29 #include "HexagonGenDFAPacketizer.inc"
34 /// Constants for Hexagon instructions.
36 const int Hexagon_MEMW_OFFSET_MAX = 4095;
37 const int Hexagon_MEMW_OFFSET_MIN = 4096;
38 const int Hexagon_MEMD_OFFSET_MAX = 8191;
39 const int Hexagon_MEMD_OFFSET_MIN = 8192;
40 const int Hexagon_MEMH_OFFSET_MAX = 2047;
41 const int Hexagon_MEMH_OFFSET_MIN = 2048;
42 const int Hexagon_MEMB_OFFSET_MAX = 1023;
43 const int Hexagon_MEMB_OFFSET_MIN = 1024;
44 const int Hexagon_ADDI_OFFSET_MAX = 32767;
45 const int Hexagon_ADDI_OFFSET_MIN = 32768;
46 const int Hexagon_MEMD_AUTOINC_MAX = 56;
47 const int Hexagon_MEMD_AUTOINC_MIN = 64;
48 const int Hexagon_MEMW_AUTOINC_MAX = 28;
49 const int Hexagon_MEMW_AUTOINC_MIN = 32;
50 const int Hexagon_MEMH_AUTOINC_MAX = 14;
51 const int Hexagon_MEMH_AUTOINC_MIN = 16;
52 const int Hexagon_MEMB_AUTOINC_MAX = 7;
53 const int Hexagon_MEMB_AUTOINC_MIN = 8;
57 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
58 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
59 RI(ST, *this), Subtarget(ST) {
63 /// isLoadFromStackSlot - If the specified machine instruction is a direct
64 /// load from a stack slot, return the virtual or physical register number of
65 /// the destination along with the FrameIndex of the loaded stack slot. If
66 /// not, return 0. This predicate must return 0 if the instruction has
67 /// any side effects other than loading from the stack slot.
68 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
69 int &FrameIndex) const {
72 switch (MI->getOpcode()) {
78 if (MI->getOperand(2).isFI() &&
79 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
80 FrameIndex = MI->getOperand(2).getIndex();
81 return MI->getOperand(0).getReg();
93 /// isStoreToStackSlot - If the specified machine instruction is a direct
94 /// store to a stack slot, return the virtual or physical register number of
95 /// the source reg along with the FrameIndex of the loaded stack slot. If
96 /// not, return 0. This predicate must return 0 if the instruction has
97 /// any side effects other than storing to the stack slot.
98 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
99 int &FrameIndex) const {
100 switch (MI->getOpcode()) {
105 if (MI->getOperand(2).isFI() &&
106 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
107 FrameIndex = MI->getOperand(2).getIndex();
108 return MI->getOperand(0).getReg();
121 HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
122 MachineBasicBlock *FBB,
123 const SmallVectorImpl<MachineOperand> &Cond,
126 int BOpc = Hexagon::JMP;
127 int BccOpc = Hexagon::JMP_Pred;
129 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
132 // Check if ReverseBranchCondition has asked to reverse this branch
133 // If we want to reverse the branch an odd number of times, we want
135 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
136 BccOpc = Hexagon::JMP_PredNot;
142 // Due to a bug in TailMerging/CFG Optimization, we need to add a
143 // special case handling of a predicated jump followed by an
144 // unconditional jump. If not, Tail Merging and CFG Optimization go
145 // into an infinite loop.
146 MachineBasicBlock *NewTBB, *NewFBB;
147 SmallVector<MachineOperand, 4> Cond;
148 MachineInstr *Term = MBB.getFirstTerminator();
149 if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
151 MachineBasicBlock *NextBB =
152 llvm::next(MachineFunction::iterator(&MBB));
153 if (NewTBB == NextBB) {
154 ReverseBranchCondition(Cond);
156 return InsertBranch(MBB, TBB, 0, Cond, DL);
159 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
162 get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
167 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
168 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
174 bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
175 MachineBasicBlock *&TBB,
176 MachineBasicBlock *&FBB,
177 SmallVectorImpl<MachineOperand> &Cond,
178 bool AllowModify) const {
181 // If the block has no terminators, it just falls into the block after it.
182 MachineBasicBlock::iterator I = MBB.end();
183 if (I == MBB.begin())
186 // A basic block may looks like this:
196 // It has two succs but does not have a terminator
197 // Don't know how to handle it.
202 } while (I != MBB.begin());
207 while (I->isDebugValue()) {
208 if (I == MBB.begin())
212 if (!isUnpredicatedTerminator(I))
215 // Get the last instruction in the block.
216 MachineInstr *LastInst = I;
218 // If there is only one terminator instruction, process it.
219 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
220 if (LastInst->getOpcode() == Hexagon::JMP) {
221 TBB = LastInst->getOperand(0).getMBB();
224 if (LastInst->getOpcode() == Hexagon::JMP_Pred) {
225 // Block ends with fall-through true condbranch.
226 TBB = LastInst->getOperand(1).getMBB();
227 Cond.push_back(LastInst->getOperand(0));
230 if (LastInst->getOpcode() == Hexagon::JMP_PredNot) {
231 // Block ends with fall-through false condbranch.
232 TBB = LastInst->getOperand(1).getMBB();
233 Cond.push_back(MachineOperand::CreateImm(0));
234 Cond.push_back(LastInst->getOperand(0));
237 // Otherwise, don't know what this is.
241 // Get the instruction before it if it's a terminator.
242 MachineInstr *SecondLastInst = I;
244 // If there are three terminators, we don't know what sort of block this is.
245 if (SecondLastInst && I != MBB.begin() &&
246 isUnpredicatedTerminator(--I))
249 // If the block ends with Hexagon::BRCOND and Hexagon:JMP, handle it.
250 if (((SecondLastInst->getOpcode() == Hexagon::BRCOND) ||
251 (SecondLastInst->getOpcode() == Hexagon::JMP_Pred)) &&
252 LastInst->getOpcode() == Hexagon::JMP) {
253 TBB = SecondLastInst->getOperand(1).getMBB();
254 Cond.push_back(SecondLastInst->getOperand(0));
255 FBB = LastInst->getOperand(0).getMBB();
259 // If the block ends with Hexagon::JMP_PredNot and Hexagon:JMP, handle it.
260 if ((SecondLastInst->getOpcode() == Hexagon::JMP_PredNot) &&
261 LastInst->getOpcode() == Hexagon::JMP) {
262 TBB = SecondLastInst->getOperand(1).getMBB();
263 Cond.push_back(MachineOperand::CreateImm(0));
264 Cond.push_back(SecondLastInst->getOperand(0));
265 FBB = LastInst->getOperand(0).getMBB();
269 // If the block ends with two Hexagon:JMPs, handle it. The second one is not
270 // executed, so remove it.
271 if (SecondLastInst->getOpcode() == Hexagon::JMP &&
272 LastInst->getOpcode() == Hexagon::JMP) {
273 TBB = SecondLastInst->getOperand(0).getMBB();
276 I->eraseFromParent();
280 // Otherwise, can't handle this.
285 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
286 int BOpc = Hexagon::JMP;
287 int BccOpc = Hexagon::JMP_Pred;
288 int BccOpcNot = Hexagon::JMP_PredNot;
290 MachineBasicBlock::iterator I = MBB.end();
291 if (I == MBB.begin()) return 0;
293 if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc &&
294 I->getOpcode() != BccOpcNot)
297 // Remove the branch.
298 I->eraseFromParent();
302 if (I == MBB.begin()) return 1;
304 if (I->getOpcode() != BccOpc && I->getOpcode() != BccOpcNot)
307 // Remove the branch.
308 I->eraseFromParent();
313 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
314 MachineBasicBlock::iterator I, DebugLoc DL,
315 unsigned DestReg, unsigned SrcReg,
316 bool KillSrc) const {
317 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
318 BuildMI(MBB, I, DL, get(Hexagon::TFR), DestReg).addReg(SrcReg);
321 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
322 BuildMI(MBB, I, DL, get(Hexagon::TFR_64), DestReg).addReg(SrcReg);
325 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
326 // Map Pd = Ps to Pd = or(Ps, Ps).
327 BuildMI(MBB, I, DL, get(Hexagon::OR_pp),
328 DestReg).addReg(SrcReg).addReg(SrcReg);
331 if (Hexagon::DoubleRegsRegClass.contains(DestReg, SrcReg)) {
332 // We can have an overlap between single and double reg: r1:0 = r0.
333 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
335 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
336 Hexagon::subreg_hireg))).addImm(0);
338 // r1:0 = r1 or no overlap.
339 BuildMI(MBB, I, DL, get(Hexagon::TFR), (RI.getSubReg(DestReg,
340 Hexagon::subreg_loreg))).addReg(SrcReg);
341 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
342 Hexagon::subreg_hireg))).addImm(0);
346 if (Hexagon::CRRegsRegClass.contains(DestReg, SrcReg)) {
347 BuildMI(MBB, I, DL, get(Hexagon::TFCR), DestReg).addReg(SrcReg);
351 assert (0 && "Unimplemented");
355 void HexagonInstrInfo::
356 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
357 unsigned SrcReg, bool isKill, int FI,
358 const TargetRegisterClass *RC,
359 const TargetRegisterInfo *TRI) const {
361 DebugLoc DL = MBB.findDebugLoc(I);
362 MachineFunction &MF = *MBB.getParent();
363 MachineFrameInfo &MFI = *MF.getFrameInfo();
364 unsigned Align = MFI.getObjectAlignment(FI);
366 MachineMemOperand *MMO =
367 MF.getMachineMemOperand(
368 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
369 MachineMemOperand::MOStore,
370 MFI.getObjectSize(FI),
373 if (Hexagon::IntRegsRegisterClass->hasSubClassEq(RC)) {
374 BuildMI(MBB, I, DL, get(Hexagon::STriw))
375 .addFrameIndex(FI).addImm(0)
376 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
377 } else if (Hexagon::DoubleRegsRegisterClass->hasSubClassEq(RC)) {
378 BuildMI(MBB, I, DL, get(Hexagon::STrid))
379 .addFrameIndex(FI).addImm(0)
380 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
381 } else if (Hexagon::PredRegsRegisterClass->hasSubClassEq(RC)) {
382 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
383 .addFrameIndex(FI).addImm(0)
384 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
386 llvm_unreachable("Unimplemented");
391 void HexagonInstrInfo::storeRegToAddr(
392 MachineFunction &MF, unsigned SrcReg,
394 SmallVectorImpl<MachineOperand> &Addr,
395 const TargetRegisterClass *RC,
396 SmallVectorImpl<MachineInstr*> &NewMIs) const
398 llvm_unreachable("Unimplemented");
402 void HexagonInstrInfo::
403 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
404 unsigned DestReg, int FI,
405 const TargetRegisterClass *RC,
406 const TargetRegisterInfo *TRI) const {
407 DebugLoc DL = MBB.findDebugLoc(I);
408 MachineFunction &MF = *MBB.getParent();
409 MachineFrameInfo &MFI = *MF.getFrameInfo();
410 unsigned Align = MFI.getObjectAlignment(FI);
412 MachineMemOperand *MMO =
413 MF.getMachineMemOperand(
414 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
415 MachineMemOperand::MOLoad,
416 MFI.getObjectSize(FI),
419 if (RC == Hexagon::IntRegsRegisterClass) {
420 BuildMI(MBB, I, DL, get(Hexagon::LDriw), DestReg)
421 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
422 } else if (RC == Hexagon::DoubleRegsRegisterClass) {
423 BuildMI(MBB, I, DL, get(Hexagon::LDrid), DestReg)
424 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
425 } else if (RC == Hexagon::PredRegsRegisterClass) {
426 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
427 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
429 llvm_unreachable("Can't store this register to stack slot");
434 void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
435 SmallVectorImpl<MachineOperand> &Addr,
436 const TargetRegisterClass *RC,
437 SmallVectorImpl<MachineInstr*> &NewMIs) const {
438 llvm_unreachable("Unimplemented");
442 MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
444 const SmallVectorImpl<unsigned> &Ops,
446 // Hexagon_TODO: Implement.
451 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
453 MachineRegisterInfo &RegInfo = MF->getRegInfo();
454 const TargetRegisterClass *TRC;
456 TRC = Hexagon::PredRegsRegisterClass;
457 } else if (VT == MVT::i32) {
458 TRC = Hexagon::IntRegsRegisterClass;
459 } else if (VT == MVT::i64) {
460 TRC = Hexagon::DoubleRegsRegisterClass;
462 llvm_unreachable("Cannot handle this register class");
465 unsigned NewReg = RegInfo.createVirtualRegister(TRC);
471 bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
472 bool isPred = MI->getDesc().isPredicable();
477 const int Opc = MI->getOpcode();
481 return isInt<12>(MI->getOperand(1).getImm());
484 case Hexagon::STrid_indexed:
485 return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
488 case Hexagon::STriw_indexed:
489 case Hexagon::STriw_nv_V4:
490 return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
493 case Hexagon::STrih_indexed:
494 case Hexagon::STrih_nv_V4:
495 return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
498 case Hexagon::STrib_indexed:
499 case Hexagon::STrib_nv_V4:
500 return isUInt<6>(MI->getOperand(1).getImm());
503 case Hexagon::LDrid_indexed:
504 return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
507 case Hexagon::LDriw_indexed:
508 return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
511 case Hexagon::LDriuh:
512 case Hexagon::LDrih_indexed:
513 case Hexagon::LDriuh_indexed:
514 return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
517 case Hexagon::LDriub:
518 case Hexagon::LDrib_indexed:
519 case Hexagon::LDriub_indexed:
520 return isUInt<6>(MI->getOperand(2).getImm());
522 case Hexagon::POST_LDrid:
523 return isShiftedInt<4,3>(MI->getOperand(3).getImm());
525 case Hexagon::POST_LDriw:
526 return isShiftedInt<4,2>(MI->getOperand(3).getImm());
528 case Hexagon::POST_LDrih:
529 case Hexagon::POST_LDriuh:
530 return isShiftedInt<4,1>(MI->getOperand(3).getImm());
532 case Hexagon::POST_LDrib:
533 case Hexagon::POST_LDriub:
534 return isInt<4>(MI->getOperand(3).getImm());
536 case Hexagon::STrib_imm_V4:
537 case Hexagon::STrih_imm_V4:
538 case Hexagon::STriw_imm_V4:
539 return (isUInt<6>(MI->getOperand(1).getImm()) &&
540 isInt<6>(MI->getOperand(2).getImm()));
542 case Hexagon::ADD_ri:
543 return isInt<8>(MI->getOperand(2).getImm());
551 return Subtarget.getHexagonArchVersion() == HexagonSubtarget::V4;
562 int HexagonInstrInfo::
563 getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
566 return !invertPredicate ? Hexagon::TFR_cPt :
569 return !invertPredicate ? Hexagon::TFRI_cPt :
570 Hexagon::TFRI_cNotPt;
572 return !invertPredicate ? Hexagon::JMP_Pred :
573 Hexagon::JMP_PredNot;
574 case Hexagon::ADD_ri:
575 return !invertPredicate ? Hexagon::ADD_ri_cPt :
576 Hexagon::ADD_ri_cNotPt;
577 case Hexagon::ADD_rr:
578 return !invertPredicate ? Hexagon::ADD_rr_cPt :
579 Hexagon::ADD_rr_cNotPt;
580 case Hexagon::XOR_rr:
581 return !invertPredicate ? Hexagon::XOR_rr_cPt :
582 Hexagon::XOR_rr_cNotPt;
583 case Hexagon::AND_rr:
584 return !invertPredicate ? Hexagon::AND_rr_cPt :
585 Hexagon::AND_rr_cNotPt;
587 return !invertPredicate ? Hexagon::OR_rr_cPt :
588 Hexagon::OR_rr_cNotPt;
589 case Hexagon::SUB_rr:
590 return !invertPredicate ? Hexagon::SUB_rr_cPt :
591 Hexagon::SUB_rr_cNotPt;
592 case Hexagon::COMBINE_rr:
593 return !invertPredicate ? Hexagon::COMBINE_rr_cPt :
594 Hexagon::COMBINE_rr_cNotPt;
596 return !invertPredicate ? Hexagon::ASLH_cPt_V4 :
597 Hexagon::ASLH_cNotPt_V4;
599 return !invertPredicate ? Hexagon::ASRH_cPt_V4 :
600 Hexagon::ASRH_cNotPt_V4;
602 return !invertPredicate ? Hexagon::SXTB_cPt_V4 :
603 Hexagon::SXTB_cNotPt_V4;
605 return !invertPredicate ? Hexagon::SXTH_cPt_V4 :
606 Hexagon::SXTH_cNotPt_V4;
608 return !invertPredicate ? Hexagon::ZXTB_cPt_V4 :
609 Hexagon::ZXTB_cNotPt_V4;
611 return !invertPredicate ? Hexagon::ZXTH_cPt_V4 :
612 Hexagon::ZXTH_cNotPt_V4;
615 return !invertPredicate ? Hexagon::JMPR_cPt :
616 Hexagon::JMPR_cNotPt;
618 // V4 indexed+scaled load.
619 case Hexagon::LDrid_indexed_V4:
620 return !invertPredicate ? Hexagon::LDrid_indexed_cPt_V4 :
621 Hexagon::LDrid_indexed_cNotPt_V4;
622 case Hexagon::LDrid_indexed_shl_V4:
623 return !invertPredicate ? Hexagon::LDrid_indexed_shl_cPt_V4 :
624 Hexagon::LDrid_indexed_shl_cNotPt_V4;
625 case Hexagon::LDrib_indexed_V4:
626 return !invertPredicate ? Hexagon::LDrib_indexed_cPt_V4 :
627 Hexagon::LDrib_indexed_cNotPt_V4;
628 case Hexagon::LDriub_indexed_V4:
629 return !invertPredicate ? Hexagon::LDriub_indexed_cPt_V4 :
630 Hexagon::LDriub_indexed_cNotPt_V4;
631 case Hexagon::LDriub_ae_indexed_V4:
632 return !invertPredicate ? Hexagon::LDriub_indexed_cPt_V4 :
633 Hexagon::LDriub_indexed_cNotPt_V4;
634 case Hexagon::LDrib_indexed_shl_V4:
635 return !invertPredicate ? Hexagon::LDrib_indexed_shl_cPt_V4 :
636 Hexagon::LDrib_indexed_shl_cNotPt_V4;
637 case Hexagon::LDriub_indexed_shl_V4:
638 return !invertPredicate ? Hexagon::LDriub_indexed_shl_cPt_V4 :
639 Hexagon::LDriub_indexed_shl_cNotPt_V4;
640 case Hexagon::LDriub_ae_indexed_shl_V4:
641 return !invertPredicate ? Hexagon::LDriub_indexed_shl_cPt_V4 :
642 Hexagon::LDriub_indexed_shl_cNotPt_V4;
643 case Hexagon::LDrih_indexed_V4:
644 return !invertPredicate ? Hexagon::LDrih_indexed_cPt_V4 :
645 Hexagon::LDrih_indexed_cNotPt_V4;
646 case Hexagon::LDriuh_indexed_V4:
647 return !invertPredicate ? Hexagon::LDriuh_indexed_cPt_V4 :
648 Hexagon::LDriuh_indexed_cNotPt_V4;
649 case Hexagon::LDriuh_ae_indexed_V4:
650 return !invertPredicate ? Hexagon::LDriuh_indexed_cPt_V4 :
651 Hexagon::LDriuh_indexed_cNotPt_V4;
652 case Hexagon::LDrih_indexed_shl_V4:
653 return !invertPredicate ? Hexagon::LDrih_indexed_shl_cPt_V4 :
654 Hexagon::LDrih_indexed_shl_cNotPt_V4;
655 case Hexagon::LDriuh_indexed_shl_V4:
656 return !invertPredicate ? Hexagon::LDriuh_indexed_shl_cPt_V4 :
657 Hexagon::LDriuh_indexed_shl_cNotPt_V4;
658 case Hexagon::LDriuh_ae_indexed_shl_V4:
659 return !invertPredicate ? Hexagon::LDriuh_indexed_shl_cPt_V4 :
660 Hexagon::LDriuh_indexed_shl_cNotPt_V4;
661 case Hexagon::LDriw_indexed_V4:
662 return !invertPredicate ? Hexagon::LDriw_indexed_cPt_V4 :
663 Hexagon::LDriw_indexed_cNotPt_V4;
664 case Hexagon::LDriw_indexed_shl_V4:
665 return !invertPredicate ? Hexagon::LDriw_indexed_shl_cPt_V4 :
666 Hexagon::LDriw_indexed_shl_cNotPt_V4;
668 case Hexagon::POST_STbri:
669 return !invertPredicate ? Hexagon::POST_STbri_cPt :
670 Hexagon::POST_STbri_cNotPt;
672 return !invertPredicate ? Hexagon::STrib_cPt :
673 Hexagon::STrib_cNotPt;
674 case Hexagon::STrib_indexed:
675 return !invertPredicate ? Hexagon::STrib_indexed_cPt :
676 Hexagon::STrib_indexed_cNotPt;
677 case Hexagon::STrib_imm_V4:
678 return !invertPredicate ? Hexagon::STrib_imm_cPt_V4 :
679 Hexagon::STrib_imm_cNotPt_V4;
680 case Hexagon::STrib_indexed_shl_V4:
681 return !invertPredicate ? Hexagon::STrib_indexed_shl_cPt_V4 :
682 Hexagon::STrib_indexed_shl_cNotPt_V4;
684 case Hexagon::POST_SThri:
685 return !invertPredicate ? Hexagon::POST_SThri_cPt :
686 Hexagon::POST_SThri_cNotPt;
688 return !invertPredicate ? Hexagon::STrih_cPt :
689 Hexagon::STrih_cNotPt;
690 case Hexagon::STrih_indexed:
691 return !invertPredicate ? Hexagon::STrih_indexed_cPt :
692 Hexagon::STrih_indexed_cNotPt;
693 case Hexagon::STrih_imm_V4:
694 return !invertPredicate ? Hexagon::STrih_imm_cPt_V4 :
695 Hexagon::STrih_imm_cNotPt_V4;
696 case Hexagon::STrih_indexed_shl_V4:
697 return !invertPredicate ? Hexagon::STrih_indexed_shl_cPt_V4 :
698 Hexagon::STrih_indexed_shl_cNotPt_V4;
700 case Hexagon::POST_STwri:
701 return !invertPredicate ? Hexagon::POST_STwri_cPt :
702 Hexagon::POST_STwri_cNotPt;
704 return !invertPredicate ? Hexagon::STriw_cPt :
705 Hexagon::STriw_cNotPt;
706 case Hexagon::STriw_indexed:
707 return !invertPredicate ? Hexagon::STriw_indexed_cPt :
708 Hexagon::STriw_indexed_cNotPt;
709 case Hexagon::STriw_indexed_shl_V4:
710 return !invertPredicate ? Hexagon::STriw_indexed_shl_cPt_V4 :
711 Hexagon::STriw_indexed_shl_cNotPt_V4;
712 case Hexagon::STriw_imm_V4:
713 return !invertPredicate ? Hexagon::STriw_imm_cPt_V4 :
714 Hexagon::STriw_imm_cNotPt_V4;
716 case Hexagon::POST_STdri:
717 return !invertPredicate ? Hexagon::POST_STdri_cPt :
718 Hexagon::POST_STdri_cNotPt;
720 return !invertPredicate ? Hexagon::STrid_cPt :
721 Hexagon::STrid_cNotPt;
722 case Hexagon::STrid_indexed:
723 return !invertPredicate ? Hexagon::STrid_indexed_cPt :
724 Hexagon::STrid_indexed_cNotPt;
725 case Hexagon::STrid_indexed_shl_V4:
726 return !invertPredicate ? Hexagon::STrid_indexed_shl_cPt_V4 :
727 Hexagon::STrid_indexed_shl_cNotPt_V4;
730 return !invertPredicate ? Hexagon::LDrid_cPt :
731 Hexagon::LDrid_cNotPt;
733 return !invertPredicate ? Hexagon::LDriw_cPt :
734 Hexagon::LDriw_cNotPt;
736 return !invertPredicate ? Hexagon::LDrih_cPt :
737 Hexagon::LDrih_cNotPt;
738 case Hexagon::LDriuh:
739 return !invertPredicate ? Hexagon::LDriuh_cPt :
740 Hexagon::LDriuh_cNotPt;
742 return !invertPredicate ? Hexagon::LDrib_cPt :
743 Hexagon::LDrib_cNotPt;
744 case Hexagon::LDriub:
745 return !invertPredicate ? Hexagon::LDriub_cPt :
746 Hexagon::LDriub_cNotPt;
747 case Hexagon::LDriubit:
748 return !invertPredicate ? Hexagon::LDriub_cPt :
749 Hexagon::LDriub_cNotPt;
751 case Hexagon::LDrid_indexed:
752 return !invertPredicate ? Hexagon::LDrid_indexed_cPt :
753 Hexagon::LDrid_indexed_cNotPt;
754 case Hexagon::LDriw_indexed:
755 return !invertPredicate ? Hexagon::LDriw_indexed_cPt :
756 Hexagon::LDriw_indexed_cNotPt;
757 case Hexagon::LDrih_indexed:
758 return !invertPredicate ? Hexagon::LDrih_indexed_cPt :
759 Hexagon::LDrih_indexed_cNotPt;
760 case Hexagon::LDriuh_indexed:
761 return !invertPredicate ? Hexagon::LDriuh_indexed_cPt :
762 Hexagon::LDriuh_indexed_cNotPt;
763 case Hexagon::LDrib_indexed:
764 return !invertPredicate ? Hexagon::LDrib_indexed_cPt :
765 Hexagon::LDrib_indexed_cNotPt;
766 case Hexagon::LDriub_indexed:
767 return !invertPredicate ? Hexagon::LDriub_indexed_cPt :
768 Hexagon::LDriub_indexed_cNotPt;
769 // Post Increment Load.
770 case Hexagon::POST_LDrid:
771 return !invertPredicate ? Hexagon::POST_LDrid_cPt :
772 Hexagon::POST_LDrid_cNotPt;
773 case Hexagon::POST_LDriw:
774 return !invertPredicate ? Hexagon::POST_LDriw_cPt :
775 Hexagon::POST_LDriw_cNotPt;
776 case Hexagon::POST_LDrih:
777 return !invertPredicate ? Hexagon::POST_LDrih_cPt :
778 Hexagon::POST_LDrih_cNotPt;
779 case Hexagon::POST_LDriuh:
780 return !invertPredicate ? Hexagon::POST_LDriuh_cPt :
781 Hexagon::POST_LDriuh_cNotPt;
782 case Hexagon::POST_LDrib:
783 return !invertPredicate ? Hexagon::POST_LDrib_cPt :
784 Hexagon::POST_LDrib_cNotPt;
785 case Hexagon::POST_LDriub:
786 return !invertPredicate ? Hexagon::POST_LDriub_cPt :
787 Hexagon::POST_LDriub_cNotPt;
789 case Hexagon::DEALLOC_RET_V4:
790 return !invertPredicate ? Hexagon::DEALLOC_RET_cPt_V4 :
791 Hexagon::DEALLOC_RET_cNotPt_V4;
793 llvm_unreachable("Unexpected predicable instruction");
797 bool HexagonInstrInfo::
798 PredicateInstruction(MachineInstr *MI,
799 const SmallVectorImpl<MachineOperand> &Cond) const {
800 int Opc = MI->getOpcode();
801 assert (isPredicable(MI) && "Expected predicable instruction");
802 bool invertJump = (!Cond.empty() && Cond[0].isImm() &&
803 (Cond[0].getImm() == 0));
804 MI->setDesc(get(getMatchingCondBranchOpcode(Opc, invertJump)));
806 // This assumes that the predicate is always the first operand
807 // in the set of inputs.
809 MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
811 for (oper = MI->getNumOperands() - 3; oper >= 0; --oper) {
812 MachineOperand MO = MI->getOperand(oper);
813 if ((MO.isReg() && !MO.isUse() && !MO.isImplicit())) {
818 MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(),
819 MO.isImplicit(), MO.isKill(),
820 MO.isDead(), MO.isUndef(),
822 } else if (MO.isImm()) {
823 MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
825 llvm_unreachable("Unexpected operand type");
829 int regPos = invertJump ? 1 : 0;
830 MachineOperand PredMO = Cond[regPos];
831 MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(),
832 PredMO.isImplicit(), PredMO.isKill(),
833 PredMO.isDead(), PredMO.isUndef(),
842 isProfitableToIfCvt(MachineBasicBlock &MBB,
844 unsigned ExtraPredCycles,
845 const BranchProbability &Probability) const {
852 isProfitableToIfCvt(MachineBasicBlock &TMBB,
854 unsigned ExtraTCycles,
855 MachineBasicBlock &FMBB,
857 unsigned ExtraFCycles,
858 const BranchProbability &Probability) const {
863 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
864 const uint64_t F = MI->getDesc().TSFlags;
866 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
871 HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
872 std::vector<MachineOperand> &Pred) const {
873 for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
874 MachineOperand MO = MI->getOperand(oper);
875 if (MO.isReg() && MO.isDef()) {
876 const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg());
877 if (RC == Hexagon::PredRegsRegisterClass) {
889 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
890 const SmallVectorImpl<MachineOperand> &Pred2) const {
897 // We indicate that we want to reverse the branch by
898 // inserting a 0 at the beginning of the Cond vector.
900 bool HexagonInstrInfo::
901 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
902 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
903 Cond.erase(Cond.begin());
905 Cond.insert(Cond.begin(), MachineOperand::CreateImm(0));
911 bool HexagonInstrInfo::
912 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs,
913 const BranchProbability &Probability) const {
914 return (NumInstrs <= 4);
917 bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
918 switch (MI->getOpcode()) {
919 case Hexagon::DEALLOC_RET_V4 :
920 case Hexagon::DEALLOC_RET_cPt_V4 :
921 case Hexagon::DEALLOC_RET_cNotPt_V4 :
922 case Hexagon::DEALLOC_RET_cdnPnt_V4 :
923 case Hexagon::DEALLOC_RET_cNotdnPnt_V4 :
924 case Hexagon::DEALLOC_RET_cdnPt_V4 :
925 case Hexagon::DEALLOC_RET_cNotdnPt_V4 :
932 bool HexagonInstrInfo::
933 isValidOffset(const int Opcode, const int Offset) const {
934 // This function is to check whether the "Offset" is in the correct range of
935 // the given "Opcode". If "Offset" is not in the correct range, "ADD_ri" is
936 // inserted to calculate the final address. Due to this reason, the function
937 // assumes that the "Offset" has correct alignment.
943 case Hexagon::STriwt:
944 assert((Offset % 4 == 0) && "Offset has incorrect alignment");
945 return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
946 (Offset <= Hexagon_MEMW_OFFSET_MAX);
950 assert((Offset % 8 == 0) && "Offset has incorrect alignment");
951 return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
952 (Offset <= Hexagon_MEMD_OFFSET_MAX);
955 case Hexagon::LDriuh:
957 case Hexagon::LDrih_ae:
958 assert((Offset % 2 == 0) && "Offset has incorrect alignment");
959 return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
960 (Offset <= Hexagon_MEMH_OFFSET_MAX);
964 case Hexagon::LDriub:
965 case Hexagon::LDriubit:
966 case Hexagon::LDrib_ae:
967 case Hexagon::LDriub_ae:
968 return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
969 (Offset <= Hexagon_MEMB_OFFSET_MAX);
971 case Hexagon::ADD_ri:
972 case Hexagon::TFR_FI:
973 return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
974 (Offset <= Hexagon_ADDI_OFFSET_MAX);
976 case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 :
977 case Hexagon::MEMw_ADDi_indexed_MEM_V4 :
978 case Hexagon::MEMw_SUBi_indexed_MEM_V4 :
979 case Hexagon::MEMw_ADDr_indexed_MEM_V4 :
980 case Hexagon::MEMw_SUBr_indexed_MEM_V4 :
981 case Hexagon::MEMw_ANDr_indexed_MEM_V4 :
982 case Hexagon::MEMw_ORr_indexed_MEM_V4 :
983 case Hexagon::MEMw_ADDSUBi_MEM_V4 :
984 case Hexagon::MEMw_ADDi_MEM_V4 :
985 case Hexagon::MEMw_SUBi_MEM_V4 :
986 case Hexagon::MEMw_ADDr_MEM_V4 :
987 case Hexagon::MEMw_SUBr_MEM_V4 :
988 case Hexagon::MEMw_ANDr_MEM_V4 :
989 case Hexagon::MEMw_ORr_MEM_V4 :
990 assert ((Offset % 4) == 0 && "MEMOPw offset is not aligned correctly." );
991 return (0 <= Offset && Offset <= 255);
993 case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 :
994 case Hexagon::MEMh_ADDi_indexed_MEM_V4 :
995 case Hexagon::MEMh_SUBi_indexed_MEM_V4 :
996 case Hexagon::MEMh_ADDr_indexed_MEM_V4 :
997 case Hexagon::MEMh_SUBr_indexed_MEM_V4 :
998 case Hexagon::MEMh_ANDr_indexed_MEM_V4 :
999 case Hexagon::MEMh_ORr_indexed_MEM_V4 :
1000 case Hexagon::MEMh_ADDSUBi_MEM_V4 :
1001 case Hexagon::MEMh_ADDi_MEM_V4 :
1002 case Hexagon::MEMh_SUBi_MEM_V4 :
1003 case Hexagon::MEMh_ADDr_MEM_V4 :
1004 case Hexagon::MEMh_SUBr_MEM_V4 :
1005 case Hexagon::MEMh_ANDr_MEM_V4 :
1006 case Hexagon::MEMh_ORr_MEM_V4 :
1007 assert ((Offset % 2) == 0 && "MEMOPh offset is not aligned correctly." );
1008 return (0 <= Offset && Offset <= 127);
1010 case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 :
1011 case Hexagon::MEMb_ADDi_indexed_MEM_V4 :
1012 case Hexagon::MEMb_SUBi_indexed_MEM_V4 :
1013 case Hexagon::MEMb_ADDr_indexed_MEM_V4 :
1014 case Hexagon::MEMb_SUBr_indexed_MEM_V4 :
1015 case Hexagon::MEMb_ANDr_indexed_MEM_V4 :
1016 case Hexagon::MEMb_ORr_indexed_MEM_V4 :
1017 case Hexagon::MEMb_ADDSUBi_MEM_V4 :
1018 case Hexagon::MEMb_ADDi_MEM_V4 :
1019 case Hexagon::MEMb_SUBi_MEM_V4 :
1020 case Hexagon::MEMb_ADDr_MEM_V4 :
1021 case Hexagon::MEMb_SUBr_MEM_V4 :
1022 case Hexagon::MEMb_ANDr_MEM_V4 :
1023 case Hexagon::MEMb_ORr_MEM_V4 :
1024 return (0 <= Offset && Offset <= 63);
1026 // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
1027 // any size. Later pass knows how to handle it.
1028 case Hexagon::STriw_pred:
1029 case Hexagon::LDriw_pred:
1032 // INLINEASM is very special.
1033 case Hexagon::INLINEASM:
1037 llvm_unreachable("No offset range is defined for this opcode. "
1038 "Please define it in the above switch statement!");
1043 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
1045 bool HexagonInstrInfo::
1046 isValidAutoIncImm(const EVT VT, const int Offset) const {
1048 if (VT == MVT::i64) {
1049 return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
1050 Offset <= Hexagon_MEMD_AUTOINC_MAX &&
1051 (Offset & 0x7) == 0);
1053 if (VT == MVT::i32) {
1054 return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
1055 Offset <= Hexagon_MEMW_AUTOINC_MAX &&
1056 (Offset & 0x3) == 0);
1058 if (VT == MVT::i16) {
1059 return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
1060 Offset <= Hexagon_MEMH_AUTOINC_MAX &&
1061 (Offset & 0x1) == 0);
1063 if (VT == MVT::i8) {
1064 return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
1065 Offset <= Hexagon_MEMB_AUTOINC_MAX);
1068 llvm_unreachable("Not an auto-inc opc!");
1072 bool HexagonInstrInfo::
1073 isMemOp(const MachineInstr *MI) const {
1074 switch (MI->getOpcode())
1076 case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 :
1077 case Hexagon::MEMw_ADDi_indexed_MEM_V4 :
1078 case Hexagon::MEMw_SUBi_indexed_MEM_V4 :
1079 case Hexagon::MEMw_ADDr_indexed_MEM_V4 :
1080 case Hexagon::MEMw_SUBr_indexed_MEM_V4 :
1081 case Hexagon::MEMw_ANDr_indexed_MEM_V4 :
1082 case Hexagon::MEMw_ORr_indexed_MEM_V4 :
1083 case Hexagon::MEMw_ADDSUBi_MEM_V4 :
1084 case Hexagon::MEMw_ADDi_MEM_V4 :
1085 case Hexagon::MEMw_SUBi_MEM_V4 :
1086 case Hexagon::MEMw_ADDr_MEM_V4 :
1087 case Hexagon::MEMw_SUBr_MEM_V4 :
1088 case Hexagon::MEMw_ANDr_MEM_V4 :
1089 case Hexagon::MEMw_ORr_MEM_V4 :
1090 case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 :
1091 case Hexagon::MEMh_ADDi_indexed_MEM_V4 :
1092 case Hexagon::MEMh_SUBi_indexed_MEM_V4 :
1093 case Hexagon::MEMh_ADDr_indexed_MEM_V4 :
1094 case Hexagon::MEMh_SUBr_indexed_MEM_V4 :
1095 case Hexagon::MEMh_ANDr_indexed_MEM_V4 :
1096 case Hexagon::MEMh_ORr_indexed_MEM_V4 :
1097 case Hexagon::MEMh_ADDSUBi_MEM_V4 :
1098 case Hexagon::MEMh_ADDi_MEM_V4 :
1099 case Hexagon::MEMh_SUBi_MEM_V4 :
1100 case Hexagon::MEMh_ADDr_MEM_V4 :
1101 case Hexagon::MEMh_SUBr_MEM_V4 :
1102 case Hexagon::MEMh_ANDr_MEM_V4 :
1103 case Hexagon::MEMh_ORr_MEM_V4 :
1104 case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 :
1105 case Hexagon::MEMb_ADDi_indexed_MEM_V4 :
1106 case Hexagon::MEMb_SUBi_indexed_MEM_V4 :
1107 case Hexagon::MEMb_ADDr_indexed_MEM_V4 :
1108 case Hexagon::MEMb_SUBr_indexed_MEM_V4 :
1109 case Hexagon::MEMb_ANDr_indexed_MEM_V4 :
1110 case Hexagon::MEMb_ORr_indexed_MEM_V4 :
1111 case Hexagon::MEMb_ADDSUBi_MEM_V4 :
1112 case Hexagon::MEMb_ADDi_MEM_V4 :
1113 case Hexagon::MEMb_SUBi_MEM_V4 :
1114 case Hexagon::MEMb_ADDr_MEM_V4 :
1115 case Hexagon::MEMb_SUBr_MEM_V4 :
1116 case Hexagon::MEMb_ANDr_MEM_V4 :
1117 case Hexagon::MEMb_ORr_MEM_V4 :
1124 bool HexagonInstrInfo::
1125 isSpillPredRegOp(const MachineInstr *MI) const {
1126 switch (MI->getOpcode())
1128 case Hexagon::STriw_pred :
1129 case Hexagon::LDriw_pred :
1136 bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
1137 const HexagonRegisterInfo& QRI = getRegisterInfo();
1138 switch (MI->getOpcode())
1140 case Hexagon::ADD_ri_cPt:
1141 case Hexagon::ADD_ri_cNotPt:
1142 case Hexagon::ADD_rr_cPt:
1143 case Hexagon::ADD_rr_cNotPt:
1144 case Hexagon::XOR_rr_cPt:
1145 case Hexagon::XOR_rr_cNotPt:
1146 case Hexagon::AND_rr_cPt:
1147 case Hexagon::AND_rr_cNotPt:
1148 case Hexagon::OR_rr_cPt:
1149 case Hexagon::OR_rr_cNotPt:
1150 case Hexagon::SUB_rr_cPt:
1151 case Hexagon::SUB_rr_cNotPt:
1152 case Hexagon::COMBINE_rr_cPt:
1153 case Hexagon::COMBINE_rr_cNotPt:
1155 case Hexagon::ASLH_cPt_V4:
1156 case Hexagon::ASLH_cNotPt_V4:
1157 case Hexagon::ASRH_cPt_V4:
1158 case Hexagon::ASRH_cNotPt_V4:
1159 case Hexagon::SXTB_cPt_V4:
1160 case Hexagon::SXTB_cNotPt_V4:
1161 case Hexagon::SXTH_cPt_V4:
1162 case Hexagon::SXTH_cNotPt_V4:
1163 case Hexagon::ZXTB_cPt_V4:
1164 case Hexagon::ZXTB_cNotPt_V4:
1165 case Hexagon::ZXTH_cPt_V4:
1166 case Hexagon::ZXTH_cNotPt_V4:
1167 return QRI.Subtarget.getHexagonArchVersion() == HexagonSubtarget::V4;
1175 bool HexagonInstrInfo::
1176 isConditionalLoad (const MachineInstr* MI) const {
1177 const HexagonRegisterInfo& QRI = getRegisterInfo();
1178 switch (MI->getOpcode())
1180 case Hexagon::LDrid_cPt :
1181 case Hexagon::LDrid_cNotPt :
1182 case Hexagon::LDrid_indexed_cPt :
1183 case Hexagon::LDrid_indexed_cNotPt :
1184 case Hexagon::LDriw_cPt :
1185 case Hexagon::LDriw_cNotPt :
1186 case Hexagon::LDriw_indexed_cPt :
1187 case Hexagon::LDriw_indexed_cNotPt :
1188 case Hexagon::LDrih_cPt :
1189 case Hexagon::LDrih_cNotPt :
1190 case Hexagon::LDrih_indexed_cPt :
1191 case Hexagon::LDrih_indexed_cNotPt :
1192 case Hexagon::LDrib_cPt :
1193 case Hexagon::LDrib_cNotPt :
1194 case Hexagon::LDrib_indexed_cPt :
1195 case Hexagon::LDrib_indexed_cNotPt :
1196 case Hexagon::LDriuh_cPt :
1197 case Hexagon::LDriuh_cNotPt :
1198 case Hexagon::LDriuh_indexed_cPt :
1199 case Hexagon::LDriuh_indexed_cNotPt :
1200 case Hexagon::LDriub_cPt :
1201 case Hexagon::LDriub_cNotPt :
1202 case Hexagon::LDriub_indexed_cPt :
1203 case Hexagon::LDriub_indexed_cNotPt :
1205 case Hexagon::POST_LDrid_cPt :
1206 case Hexagon::POST_LDrid_cNotPt :
1207 case Hexagon::POST_LDriw_cPt :
1208 case Hexagon::POST_LDriw_cNotPt :
1209 case Hexagon::POST_LDrih_cPt :
1210 case Hexagon::POST_LDrih_cNotPt :
1211 case Hexagon::POST_LDrib_cPt :
1212 case Hexagon::POST_LDrib_cNotPt :
1213 case Hexagon::POST_LDriuh_cPt :
1214 case Hexagon::POST_LDriuh_cNotPt :
1215 case Hexagon::POST_LDriub_cPt :
1216 case Hexagon::POST_LDriub_cNotPt :
1217 return QRI.Subtarget.getHexagonArchVersion() == HexagonSubtarget::V4;
1218 case Hexagon::LDrid_indexed_cPt_V4 :
1219 case Hexagon::LDrid_indexed_cNotPt_V4 :
1220 case Hexagon::LDrid_indexed_shl_cPt_V4 :
1221 case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
1222 case Hexagon::LDrib_indexed_cPt_V4 :
1223 case Hexagon::LDrib_indexed_cNotPt_V4 :
1224 case Hexagon::LDrib_indexed_shl_cPt_V4 :
1225 case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
1226 case Hexagon::LDriub_indexed_cPt_V4 :
1227 case Hexagon::LDriub_indexed_cNotPt_V4 :
1228 case Hexagon::LDriub_indexed_shl_cPt_V4 :
1229 case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
1230 case Hexagon::LDrih_indexed_cPt_V4 :
1231 case Hexagon::LDrih_indexed_cNotPt_V4 :
1232 case Hexagon::LDrih_indexed_shl_cPt_V4 :
1233 case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
1234 case Hexagon::LDriuh_indexed_cPt_V4 :
1235 case Hexagon::LDriuh_indexed_cNotPt_V4 :
1236 case Hexagon::LDriuh_indexed_shl_cPt_V4 :
1237 case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
1238 case Hexagon::LDriw_indexed_cPt_V4 :
1239 case Hexagon::LDriw_indexed_cNotPt_V4 :
1240 case Hexagon::LDriw_indexed_shl_cPt_V4 :
1241 case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
1242 return QRI.Subtarget.getHexagonArchVersion() == HexagonSubtarget::V4;
1248 DFAPacketizer *HexagonInstrInfo::
1249 CreateTargetScheduleState(const TargetMachine *TM,
1250 const ScheduleDAG *DAG) const {
1251 const InstrItineraryData *II = TM->getInstrItineraryData();
1252 return TM->getSubtarget<HexagonGenSubtargetInfo>().createDFAPacketizer(II);
1255 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1256 const MachineBasicBlock *MBB,
1257 const MachineFunction &MF) const {
1258 // Debug info is never a scheduling boundary. It's necessary to be explicit
1259 // due to the special treatment of IT instructions below, otherwise a
1260 // dbg_value followed by an IT will result in the IT instruction being
1261 // considered a scheduling hazard, which is wrong. It should be the actual
1262 // instruction preceding the dbg_value instruction(s), just like it is
1263 // when debug info is not present.
1264 if (MI->isDebugValue())
1267 // Terminators and labels can't be scheduled around.
1268 if (MI->getDesc().isTerminator() || MI->isLabel() || MI->isInlineAsm())