Encode the multi-load/store instructions with their respective modes ('ia',
[oota-llvm.git] / lib / Target / ARM / ARMBaseInstrInfo.cpp
2010-11-16 Bill WendlingEncode the multi-load/store instructions with their...
2010-11-15 Evan ChengCode clean up. The peephole pass should be the one...
2010-11-11 Eric ChristopherRevert this temporarily.
2010-11-11 Eric ChristopherChange the prologue and epilogue to use push/pop for...
2010-11-03 Evan ChengTwo sets of changes. Sorry they are intermingled.
2010-11-01 Bill WendlingWhen we look at instructions to convert to setting...
2010-10-29 Evan ChengFix fpscr <-> GPR latency info.
2010-10-29 Evan ChengAvoiding overly aggressive latency scheduling. If the...
2010-10-28 Evan ChengRe-commit 117518 and 117519 now that ARM MC test failur...
2010-10-28 Evan ChengRevert 117518 and 117519 for now. They changed scheduli...
2010-10-28 Evan Cheng- Assign load / store with shifter op address modes...
2010-10-27 Jim GrosbachRefactor ARM STR/STRB instruction patterns into STR...
2010-10-27 Jim GrosbachThe immediate operands of an LDRi12 instruction doesn...
2010-10-27 Jim GrosbachLDRi12 machine instructions handle negative offset...
2010-10-27 Jim GrosbachSplit ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordi...
2010-10-26 Jim GrosbachFirst part of refactoring ARM addrmode2 (load/store...
2010-10-26 Evan ChengUse instruction itinerary to determine what instruction...
2010-10-23 Chandler CarruthMove the remaining attribute macros to systematic names...
2010-10-23 Evan ChengLatency between CPSR def and branch is zero.
2010-10-19 Evan ChengRe-enable register pressure aware machine licm with...
2010-10-19 Daniel DunbarRevert r116781 "- Add a hook for target to determine...
2010-10-19 Evan Cheng- Add a hook for target to determine whether an instruc...
2010-10-18 Bill WendlingDon't recompute MachineRegisterInfo in the Optimize...
2010-10-09 Bill WendlingCheck to make sure that the iterator isn't at the begin...
2010-10-07 Evan ChengCode refactoring.
2010-10-07 Evan ChengModel operand cycles of vldm / vstm; also fixes schedul...
2010-10-06 Jim GrosbachClean up MOVi32imm and t2MOVi32imm pseudo instruction...
2010-10-06 Evan Cheng- Add TargetInstrInfo::getOperandLatency() to compute...
2010-10-05 Michael J. Spencerfix MSVC 2010 build.
2010-10-05 Michael J. SpencerCleanup Whitespace.
2010-10-01 Owen AndersonThread the determination of branch prediction hit rates...
2010-10-01 Owen AndersonMake the spelling of the flags for old-style if-convers...
2010-09-30 Owen AndersonTemporarily add a flag to make it easier to compare...
2010-09-29 Gabor Greifimprove heuristics to find the 'and' corresponding...
2010-09-28 Owen AndersonAdd a subtarget hook for reporting the misprediction...
2010-09-28 Owen AndersonPart one of switching to using a more sane heuristic...
2010-09-28 Eric Christopher80-col fixups.
2010-09-23 Evan ChengFix r114632. Return if the only terminator is an uncond...
2010-09-23 Evan ChengIf there are multiple unconditional branches terminatin...
2010-09-21 Evan ChengOptimizeCompareInstr should avoid iterating pass the...
2010-09-21 Gabor GreifFix buglet when the TST instruction directly uses the...
2010-09-21 Gabor GreifMove the search for the appropriate AND instruction
2010-09-21 Chris Lattnerconvert targets to the new MF.getMachineMemOperand...
2010-09-15 Jakob Stoklund OlesenRemember VLDMQ.
2010-09-15 Jakob Stoklund OlesenAdd missing break.
2010-09-15 Jakob Stoklund OlesenRecognize VST1q64Pseudo and VSTMQ as stack slot stores.
2010-09-15 Bob WilsonReapply Gabor's 113839, 113840, and 113876 with a fix...
2010-09-15 Gabor Greifthe darwin9-powerpc buildbot keeps consistently crashing,
2010-09-15 Jakob Stoklund OlesenMove ARM is{LoadFrom,StoreTo}StackSlot closer to their...
2010-09-15 Bob WilsonSpelling fix.
2010-09-15 Bob WilsonUse VLD1/VST1 pseudo instructions for loadRegFromStackS...
2010-09-14 Gabor Greifan attempt to salvage the darwin9-powerpc buildbot...
2010-09-14 Gabor GreifEliminate a 'tst' that immediately follows an 'and'
2010-09-11 Bill WendlingRename ConvertToSetZeroFlag to something more general.
2010-09-10 Bill WendlingNo need to recompute the SrcReg and CmpValue.
2010-09-10 Bill WendlingMove some of the decision logic for converting an instr...
2010-09-10 Bill WendlingModify the comparison optimizations in the peephole...
2010-09-10 Jim GrosbachAdd a missing case to duplicateCPV() for LSDA constants...
2010-09-10 Evan ChengTeach if-converter to be more careful with predicating...
2010-09-09 Evan ChengFor each instruction itinerary class, specify the numbe...
2010-09-08 Jim Grosbachremove obsolete comment
2010-09-08 Jim Grosbachcorrect spill code to properly determine if dynamic...
2010-08-27 Bob WilsonChange ARM VFP VLDM/VSTM instructions to use addressing...
2010-08-18 Bill WendlingMinor simplification. Gets rid of a needless temporary.
2010-08-11 Bill WendlingHandle ARM compares as well as converting for ARM adds...
2010-08-10 Bill WendlingTurn optimize compares back on with fix. We needed...
2010-08-08 Bill WendlingUse the "isCompare" machine instruction attribute inste...
2010-08-06 Bill WendlingAdd the Optimize Compares pass (disabled by default).
2010-07-30 Jim GrosbachMany Thumb2 instructions can reference the full ARM...
2010-07-20 Chris Lattnerprune #includes a little.
2010-07-16 Jakob Stoklund OlesenRemove the isMoveInstr() hook.
2010-07-16 Bill WendlingRename DBG_LABEL PROLOG_LABEL, because it's only used...
2010-07-11 Jakob Stoklund OlesenRISC architectures get their memory operand folding...
2010-07-11 Jakob Stoklund OlesenReplace copyRegToReg with copyPhysReg for ARM.
2010-07-09 Jakob Stoklund OlesenAutomatically fold COPY instructions into stack load...
2010-07-08 Bob WilsonFor big-endian systems, VLD2/VST2 with 32-bit vector...
2010-07-06 Bob WilsonRepresent NEON load/store alignments in bytes, not...
2010-07-06 Rafael EspindolaDon't create neon moves in CopyRegToReg. NEONMoveFixPas...
2010-06-29 Rafael EspindolaAdd a VT argument to getMinimalPhysRegClass and replace...
2010-06-25 Evan ChengChange if-conversion block size limit checks to add...
2010-06-25 Jim GrosbachIT instructions are considered to be scheduling hazards...
2010-06-23 Bill WendlingWe are missing opportunites to use ldm. Take code like...
2010-06-18 Evan ChengAllow ARM if-converter to be run after post allocation...
2010-06-18 Bob WilsonRewrite chained if's as switches and replace assertions...
2010-06-17 Stuart HastingsAdd a DebugLoc parameter to TargetInstrInfo::InsertBran...
2010-06-15 Dale JohannesenNext round of tail call changes. Register used in...
2010-06-15 Bob WilsonVMOVQQ and VMOVQQQQ are pseudo instructions and not...
2010-06-08 Bruno Cardoso LopesReapply r105521, this time appending "LLU" to 64 bit
2010-06-05 Chris Lattnerrevert r105521, which is breaking the buildbots with...
2010-06-05 Bruno Cardoso LopesInitial AVX support for some instructions. No patterns...
2010-06-02 Jakob Stoklund OlesenSlightly change the meaning of the reMaterialize target...
2010-06-02 Jim GrosbachClean up 80 column violations. No functional change.
2010-06-02 Rafael EspindolaRemove the TargetRegisterClass member from CalleeSavedInfo
2010-05-27 Jim GrosbachUpdate the saved stack pointer in the sjlj function...
2010-05-24 Jakob Stoklund OlesenSwitch ARMRegisterInfo.td to use SubRegIndex and elimin...
2010-05-22 Evan ChengImplement @llvm.returnaddress. rdar://8015977.
2010-05-22 Jim GrosbachImplement eh.sjlj.longjmp for ARM. Clean up the intrins...
2010-05-14 Evan ChengAdded a QQQQ register file to model 4-consecutive Q...
2010-05-13 Evan ChengBring back VLD1q and VST1q and use them for reloading...
2010-05-07 Evan ChengUse VLD2q32 / VST2q32 to reload / spill QQ (pair of...
next