Added STRHT for disassembly only and fixed a bug in AI3sthpo class where the W

bit should be set to 0 instead of 1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97481 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td
index 7b5a1e3a7ed7340e4519292f095d9221ee02371c..76595fa2952a144432a07da9a9a20fff4b701e58 100644 (file)
--- a/lib/Target/ARM/ARMInstrFormats.td
+++ b/lib/Target/ARM/ARMInstrFormats.td
@@ -815,7 +815,7 @@ class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin,
   let Inst{6}     = 0; // S bit
   let Inst{7}     = 1;
   let Inst{20}    = 0; // L bit
   let Inst{6}     = 0; // S bit
   let Inst{7}     = 1;
   let Inst{20}    = 0; // L bit

-  let Inst{21}    = 1; // W bit
+  let Inst{21}    = 0; // W bit

   let Inst{24}    = 0; // P bit
   let Inst{27-25} = 0b000;
 }
   let Inst{24}    = 0; // P bit
   let Inst{27-25} = 0b000;
 }

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index cd9c2ccce33e31c5b7f55cb14595f751aa0405f6..cd295d2712d53fc0d4e7fb8aa992b24672591b5c 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -1260,7 +1260,7 @@ def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
                      "strd", "\t$src1, $src2, [$base], $offset",
                      "$base = $base_wb", []>;
 
                      "strd", "\t$src1, $src2, [$base], $offset",
                      "$base = $base_wb", []>;
 

-// STRT and STRBT are for disassembly only.
+// STRT, STRBT, and STRHT are for disassembly only.

 
 def STRT : AI2stwpo<(outs GPR:$base_wb),
                     (ins GPR:$src, GPR:$base,am2offset:$offset),
 
 def STRT : AI2stwpo<(outs GPR:$base_wb),
                     (ins GPR:$src, GPR:$base,am2offset:$offset),


@@ -1278,6 +1278,14 @@ def STRBT : AI2stbpo<(outs GPR:$base_wb),
   let Inst{21} = 1; // overwrite
 }
 
   let Inst{21} = 1; // overwrite
 }
 

+def STRHT: AI3sthpo<(outs GPR:$base_wb),
+                    (ins GPR:$src, GPR:$base,am3offset:$offset),
+                    StMiscFrm, IIC_iStoreru,
+                    "strht", "\t$src, [$base], $offset", "$base = $base_wb",
+                    [/* For disassembly only; pattern left blank */]> {
+  let Inst{21} = 1; // overwrite
+}
+

 //===----------------------------------------------------------------------===//
 //  Load / store multiple Instructions.
 //
 //===----------------------------------------------------------------------===//
 //  Load / store multiple Instructions.
 //