1 //===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<5> val> {
22 def Pseudo : Format<0>;
23 def MulFrm : Format<1>;
24 def BrFrm : Format<2>;
25 def BrMiscFrm : Format<3>;
27 def DPFrm : Format<4>;
28 def DPSoRegFrm : Format<5>;
30 def LdFrm : Format<6>;
31 def StFrm : Format<7>;
32 def LdMiscFrm : Format<8>;
33 def StMiscFrm : Format<9>;
34 def LdStMulFrm : Format<10>;
36 def LdStExFrm : Format<28>;
38 def ArithMiscFrm : Format<11>;
39 def ExtFrm : Format<12>;
41 def VFPUnaryFrm : Format<13>;
42 def VFPBinaryFrm : Format<14>;
43 def VFPConv1Frm : Format<15>;
44 def VFPConv2Frm : Format<16>;
45 def VFPConv3Frm : Format<17>;
46 def VFPConv4Frm : Format<18>;
47 def VFPConv5Frm : Format<19>;
48 def VFPLdStFrm : Format<20>;
49 def VFPLdStMulFrm : Format<21>;
50 def VFPMiscFrm : Format<22>;
52 def ThumbFrm : Format<23>;
54 def NEONFrm : Format<24>;
55 def NEONGetLnFrm : Format<25>;
56 def NEONSetLnFrm : Format<26>;
57 def NEONDupFrm : Format<27>;
59 def MiscFrm : Format<29>;
60 def ThumbMiscFrm : Format<30>;
64 // the instruction has a Rn register operand.
65 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
66 // it doesn't have a Rn operand.
67 class UnaryDP { bit isUnaryDataProc = 1; }
69 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
70 // a 16-bit Thumb instruction if certain conditions are met.
71 class Xform16Bit { bit canXformTo16Bit = 1; }
73 //===----------------------------------------------------------------------===//
74 // ARM Instruction flags. These need to match ARMInstrInfo.h.
78 class AddrMode<bits<4> val> {
81 def AddrModeNone : AddrMode<0>;
82 def AddrMode1 : AddrMode<1>;
83 def AddrMode2 : AddrMode<2>;
84 def AddrMode3 : AddrMode<3>;
85 def AddrMode4 : AddrMode<4>;
86 def AddrMode5 : AddrMode<5>;
87 def AddrMode6 : AddrMode<6>;
88 def AddrModeT1_1 : AddrMode<7>;
89 def AddrModeT1_2 : AddrMode<8>;
90 def AddrModeT1_4 : AddrMode<9>;
91 def AddrModeT1_s : AddrMode<10>;
92 def AddrModeT2_i12: AddrMode<11>;
93 def AddrModeT2_i8 : AddrMode<12>;
94 def AddrModeT2_so : AddrMode<13>;
95 def AddrModeT2_pc : AddrMode<14>;
96 def AddrModeT2_i8s4 : AddrMode<15>;
99 class SizeFlagVal<bits<3> val> {
102 def SizeInvalid : SizeFlagVal<0>; // Unset.
103 def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
104 def Size8Bytes : SizeFlagVal<2>;
105 def Size4Bytes : SizeFlagVal<3>;
106 def Size2Bytes : SizeFlagVal<4>;
108 // Load / store index mode.
109 class IndexMode<bits<2> val> {
112 def IndexModeNone : IndexMode<0>;
113 def IndexModePre : IndexMode<1>;
114 def IndexModePost : IndexMode<2>;
116 // Instruction execution domain.
117 class Domain<bits<2> val> {
120 def GenericDomain : Domain<0>;
121 def VFPDomain : Domain<1>; // Instructions in VFP domain only
122 def NeonDomain : Domain<2>; // Instructions in Neon domain only
123 def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
125 //===----------------------------------------------------------------------===//
127 // ARM special operands.
130 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
131 // register whose default is 0 (no register).
132 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
133 (ops (i32 14), (i32 zero_reg))> {
134 let PrintMethod = "printPredicateOperand";
137 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
138 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
139 let PrintMethod = "printSBitModifierOperand";
142 // Same as cc_out except it defaults to setting CPSR.
143 def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
144 let PrintMethod = "printSBitModifierOperand";
147 //===----------------------------------------------------------------------===//
149 // ARM Instruction templates.
152 class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im,
153 Format f, Domain d, string cstr, InstrItinClass itin>
155 let Namespace = "ARM";
159 bits<4> AddrModeBits = AM.Value;
162 bits<3> SizeFlag = SZ.Value;
165 bits<2> IndexModeBits = IM.Value;
168 bits<5> Form = F.Value;
171 bits<2> Dom = D.Value;
174 // Attributes specific to ARM instructions...
176 bit isUnaryDataProc = 0;
177 bit canXformTo16Bit = 0;
179 let Constraints = cstr;
180 let Itinerary = itin;
187 class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im,
188 Format f, Domain d, string cstr, InstrItinClass itin>
189 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding;
191 // This Encoding-less class is used by Thumb1 to specify the encoding bits later
192 // on by adding flavors to specific instructions.
193 class InstThumb<AddrMode am, SizeFlagVal sz, IndexMode im,
194 Format f, Domain d, string cstr, InstrItinClass itin>
195 : InstTemplate<am, sz, im, f, d, cstr, itin>;
197 class PseudoInst<dag oops, dag iops, InstrItinClass itin,
198 string asm, list<dag> pattern>
199 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain,
201 let OutOperandList = oops;
202 let InOperandList = iops;
204 let Pattern = pattern;
207 // Almost all ARM instructions are predicable.
208 class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
209 IndexMode im, Format f, InstrItinClass itin,
210 string opc, string asm, string cstr,
212 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
213 let OutOperandList = oops;
214 let InOperandList = !con(iops, (ops pred:$p));
215 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
216 let Pattern = pattern;
217 list<Predicate> Predicates = [IsARM];
219 // A few are not predicable
220 class InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
221 IndexMode im, Format f, InstrItinClass itin,
222 string opc, string asm, string cstr,
224 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
225 let OutOperandList = oops;
226 let InOperandList = iops;
227 let AsmString = !strconcat(opc, asm);
228 let Pattern = pattern;
229 let isPredicable = 0;
230 list<Predicate> Predicates = [IsARM];
233 // Same as I except it can optionally modify CPSR. Note it's modeled as
234 // an input operand since by default it's a zero register. It will
235 // become an implicit def once it's "flipped".
236 class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
237 IndexMode im, Format f, InstrItinClass itin,
238 string opc, string asm, string cstr,
240 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
241 let OutOperandList = oops;
242 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
243 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm));
244 let Pattern = pattern;
245 list<Predicate> Predicates = [IsARM];
249 class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
250 IndexMode im, Format f, InstrItinClass itin,
251 string asm, string cstr, list<dag> pattern>
252 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
253 let OutOperandList = oops;
254 let InOperandList = iops;
256 let Pattern = pattern;
257 list<Predicate> Predicates = [IsARM];
260 class AI<dag oops, dag iops, Format f, InstrItinClass itin,
261 string opc, string asm, list<dag> pattern>
262 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
263 opc, asm, "", pattern>;
264 class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
265 string opc, string asm, list<dag> pattern>
266 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
267 opc, asm, "", pattern>;
268 class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
269 string asm, list<dag> pattern>
270 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
272 class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
273 string opc, string asm, list<dag> pattern>
274 : InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
275 opc, asm, "", pattern>;
277 // Ctrl flow instructions
278 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
279 string opc, string asm, list<dag> pattern>
280 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
281 opc, asm, "", pattern> {
282 let Inst{27-24} = opcod;
284 class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
285 string asm, list<dag> pattern>
286 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
288 let Inst{27-24} = opcod;
290 class ABXIx2<dag oops, dag iops, InstrItinClass itin,
291 string asm, list<dag> pattern>
292 : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, BrMiscFrm, itin,
295 // BR_JT instructions
296 class JTI<dag oops, dag iops, InstrItinClass itin,
297 string asm, list<dag> pattern>
298 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin,
302 // Atomic load/store instructions
304 class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
305 string opc, string asm, list<dag> pattern>
306 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
307 opc, asm, "", pattern> {
308 let Inst{27-23} = 0b00011;
309 let Inst{22-21} = opcod;
311 let Inst{11-0} = 0b111110011111;
313 class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
314 string opc, string asm, list<dag> pattern>
315 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
316 opc, asm, "", pattern> {
317 let Inst{27-23} = 0b00011;
318 let Inst{22-21} = opcod;
320 let Inst{11-4} = 0b11111001;
323 // addrmode1 instructions
324 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
325 string opc, string asm, list<dag> pattern>
326 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
327 opc, asm, "", pattern> {
328 let Inst{24-21} = opcod;
329 let Inst{27-26} = {0,0};
331 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
332 string opc, string asm, list<dag> pattern>
333 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
334 opc, asm, "", pattern> {
335 let Inst{24-21} = opcod;
336 let Inst{27-26} = {0,0};
338 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
339 string asm, list<dag> pattern>
340 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
342 let Inst{24-21} = opcod;
343 let Inst{27-26} = {0,0};
345 class AI1x2<dag oops, dag iops, Format f, InstrItinClass itin,
346 string opc, string asm, list<dag> pattern>
347 : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, itin,
348 opc, asm, "", pattern>;
351 // addrmode2 loads and stores
352 class AI2<dag oops, dag iops, Format f, InstrItinClass itin,
353 string opc, string asm, list<dag> pattern>
354 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
355 opc, asm, "", pattern> {
356 let Inst{27-26} = {0,1};
360 class AI2ldw<dag oops, dag iops, Format f, InstrItinClass itin,
361 string opc, string asm, list<dag> pattern>
362 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
363 opc, asm, "", pattern> {
364 let Inst{20} = 1; // L bit
365 let Inst{21} = 0; // W bit
366 let Inst{22} = 0; // B bit
367 let Inst{24} = 1; // P bit
368 let Inst{27-26} = {0,1};
370 class AXI2ldw<dag oops, dag iops, Format f, InstrItinClass itin,
371 string asm, list<dag> pattern>
372 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
374 let Inst{20} = 1; // L bit
375 let Inst{21} = 0; // W bit
376 let Inst{22} = 0; // B bit
377 let Inst{24} = 1; // P bit
378 let Inst{27-26} = {0,1};
380 class AI2ldb<dag oops, dag iops, Format f, InstrItinClass itin,
381 string opc, string asm, list<dag> pattern>
382 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
383 opc, asm, "", pattern> {
384 let Inst{20} = 1; // L bit
385 let Inst{21} = 0; // W bit
386 let Inst{22} = 1; // B bit
387 let Inst{24} = 1; // P bit
388 let Inst{27-26} = {0,1};
390 class AXI2ldb<dag oops, dag iops, Format f, InstrItinClass itin,
391 string asm, list<dag> pattern>
392 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
394 let Inst{20} = 1; // L bit
395 let Inst{21} = 0; // W bit
396 let Inst{22} = 1; // B bit
397 let Inst{24} = 1; // P bit
398 let Inst{27-26} = {0,1};
402 class AI2stw<dag oops, dag iops, Format f, InstrItinClass itin,
403 string opc, string asm, list<dag> pattern>
404 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
405 opc, asm, "", pattern> {
406 let Inst{20} = 0; // L bit
407 let Inst{21} = 0; // W bit
408 let Inst{22} = 0; // B bit
409 let Inst{24} = 1; // P bit
410 let Inst{27-26} = {0,1};
412 class AXI2stw<dag oops, dag iops, Format f, InstrItinClass itin,
413 string asm, list<dag> pattern>
414 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
416 let Inst{20} = 0; // L bit
417 let Inst{21} = 0; // W bit
418 let Inst{22} = 0; // B bit
419 let Inst{24} = 1; // P bit
420 let Inst{27-26} = {0,1};
422 class AI2stb<dag oops, dag iops, Format f, InstrItinClass itin,
423 string opc, string asm, list<dag> pattern>
424 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
425 opc, asm, "", pattern> {
426 let Inst{20} = 0; // L bit
427 let Inst{21} = 0; // W bit
428 let Inst{22} = 1; // B bit
429 let Inst{24} = 1; // P bit
430 let Inst{27-26} = {0,1};
432 class AXI2stb<dag oops, dag iops, Format f, InstrItinClass itin,
433 string asm, list<dag> pattern>
434 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
436 let Inst{20} = 0; // L bit
437 let Inst{21} = 0; // W bit
438 let Inst{22} = 1; // B bit
439 let Inst{24} = 1; // P bit
440 let Inst{27-26} = {0,1};
444 class AI2ldwpr<dag oops, dag iops, Format f, InstrItinClass itin,
445 string opc, string asm, string cstr, list<dag> pattern>
446 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
447 opc, asm, cstr, pattern> {
448 let Inst{20} = 1; // L bit
449 let Inst{21} = 1; // W bit
450 let Inst{22} = 0; // B bit
451 let Inst{24} = 1; // P bit
452 let Inst{27-26} = {0,1};
454 class AI2ldbpr<dag oops, dag iops, Format f, InstrItinClass itin,
455 string opc, string asm, string cstr, list<dag> pattern>
456 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
457 opc, asm, cstr, pattern> {
458 let Inst{20} = 1; // L bit
459 let Inst{21} = 1; // W bit
460 let Inst{22} = 1; // B bit
461 let Inst{24} = 1; // P bit
462 let Inst{27-26} = {0,1};
465 // Pre-indexed stores
466 class AI2stwpr<dag oops, dag iops, Format f, InstrItinClass itin,
467 string opc, string asm, string cstr, list<dag> pattern>
468 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
469 opc, asm, cstr, pattern> {
470 let Inst{20} = 0; // L bit
471 let Inst{21} = 1; // W bit
472 let Inst{22} = 0; // B bit
473 let Inst{24} = 1; // P bit
474 let Inst{27-26} = {0,1};
476 class AI2stbpr<dag oops, dag iops, Format f, InstrItinClass itin,
477 string opc, string asm, string cstr, list<dag> pattern>
478 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
479 opc, asm, cstr, pattern> {
480 let Inst{20} = 0; // L bit
481 let Inst{21} = 1; // W bit
482 let Inst{22} = 1; // B bit
483 let Inst{24} = 1; // P bit
484 let Inst{27-26} = {0,1};
487 // Post-indexed loads
488 class AI2ldwpo<dag oops, dag iops, Format f, InstrItinClass itin,
489 string opc, string asm, string cstr, list<dag> pattern>
490 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
491 opc, asm, cstr,pattern> {
492 let Inst{20} = 1; // L bit
493 let Inst{21} = 0; // W bit
494 let Inst{22} = 0; // B bit
495 let Inst{24} = 0; // P bit
496 let Inst{27-26} = {0,1};
498 class AI2ldbpo<dag oops, dag iops, Format f, InstrItinClass itin,
499 string opc, string asm, string cstr, list<dag> pattern>
500 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
501 opc, asm, cstr,pattern> {
502 let Inst{20} = 1; // L bit
503 let Inst{21} = 0; // W bit
504 let Inst{22} = 1; // B bit
505 let Inst{24} = 0; // P bit
506 let Inst{27-26} = {0,1};
509 // Post-indexed stores
510 class AI2stwpo<dag oops, dag iops, Format f, InstrItinClass itin,
511 string opc, string asm, string cstr, list<dag> pattern>
512 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
513 opc, asm, cstr,pattern> {
514 let Inst{20} = 0; // L bit
515 let Inst{21} = 0; // W bit
516 let Inst{22} = 0; // B bit
517 let Inst{24} = 0; // P bit
518 let Inst{27-26} = {0,1};
520 class AI2stbpo<dag oops, dag iops, Format f, InstrItinClass itin,
521 string opc, string asm, string cstr, list<dag> pattern>
522 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
523 opc, asm, cstr,pattern> {
524 let Inst{20} = 0; // L bit
525 let Inst{21} = 0; // W bit
526 let Inst{22} = 1; // B bit
527 let Inst{24} = 0; // P bit
528 let Inst{27-26} = {0,1};
531 // addrmode3 instructions
532 class AI3<dag oops, dag iops, Format f, InstrItinClass itin,
533 string opc, string asm, list<dag> pattern>
534 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
535 opc, asm, "", pattern>;
536 class AXI3<dag oops, dag iops, Format f, InstrItinClass itin,
537 string asm, list<dag> pattern>
538 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
542 class AI3ldh<dag oops, dag iops, Format f, InstrItinClass itin,
543 string opc, string asm, list<dag> pattern>
544 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
545 opc, asm, "", pattern> {
547 let Inst{5} = 1; // H bit
548 let Inst{6} = 0; // S bit
550 let Inst{20} = 1; // L bit
551 let Inst{21} = 0; // W bit
552 let Inst{24} = 1; // P bit
553 let Inst{27-25} = 0b000;
555 class AXI3ldh<dag oops, dag iops, Format f, InstrItinClass itin,
556 string asm, list<dag> pattern>
557 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
560 let Inst{5} = 1; // H bit
561 let Inst{6} = 0; // S bit
563 let Inst{20} = 1; // L bit
564 let Inst{21} = 0; // W bit
565 let Inst{24} = 1; // P bit
567 class AI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin,
568 string opc, string asm, list<dag> pattern>
569 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
570 opc, asm, "", pattern> {
572 let Inst{5} = 1; // H bit
573 let Inst{6} = 1; // S bit
575 let Inst{20} = 1; // L bit
576 let Inst{21} = 0; // W bit
577 let Inst{24} = 1; // P bit
578 let Inst{27-25} = 0b000;
580 class AXI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin,
581 string asm, list<dag> pattern>
582 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
585 let Inst{5} = 1; // H bit
586 let Inst{6} = 1; // S bit
588 let Inst{20} = 1; // L bit
589 let Inst{21} = 0; // W bit
590 let Inst{24} = 1; // P bit
592 class AI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin,
593 string opc, string asm, list<dag> pattern>
594 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
595 opc, asm, "", pattern> {
597 let Inst{5} = 0; // H bit
598 let Inst{6} = 1; // S bit
600 let Inst{20} = 1; // L bit
601 let Inst{21} = 0; // W bit
602 let Inst{24} = 1; // P bit
603 let Inst{27-25} = 0b000;
605 class AXI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin,
606 string asm, list<dag> pattern>
607 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
610 let Inst{5} = 0; // H bit
611 let Inst{6} = 1; // S bit
613 let Inst{20} = 1; // L bit
614 let Inst{21} = 0; // W bit
615 let Inst{24} = 1; // P bit
617 class AI3ldd<dag oops, dag iops, Format f, InstrItinClass itin,
618 string opc, string asm, list<dag> pattern>
619 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
620 opc, asm, "", pattern> {
622 let Inst{5} = 0; // H bit
623 let Inst{6} = 1; // S bit
625 let Inst{20} = 0; // L bit
626 let Inst{21} = 0; // W bit
627 let Inst{24} = 1; // P bit
628 let Inst{27-25} = 0b000;
632 class AI3sth<dag oops, dag iops, Format f, InstrItinClass itin,
633 string opc, string asm, list<dag> pattern>
634 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
635 opc, asm, "", pattern> {
637 let Inst{5} = 1; // H bit
638 let Inst{6} = 0; // S bit
640 let Inst{20} = 0; // L bit
641 let Inst{21} = 0; // W bit
642 let Inst{24} = 1; // P bit
643 let Inst{27-25} = 0b000;
645 class AXI3sth<dag oops, dag iops, Format f, InstrItinClass itin,
646 string asm, list<dag> pattern>
647 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
650 let Inst{5} = 1; // H bit
651 let Inst{6} = 0; // S bit
653 let Inst{20} = 0; // L bit
654 let Inst{21} = 0; // W bit
655 let Inst{24} = 1; // P bit
657 class AI3std<dag oops, dag iops, Format f, InstrItinClass itin,
658 string opc, string asm, list<dag> pattern>
659 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
660 opc, asm, "", pattern> {
662 let Inst{5} = 1; // H bit
663 let Inst{6} = 1; // S bit
665 let Inst{20} = 0; // L bit
666 let Inst{21} = 0; // W bit
667 let Inst{24} = 1; // P bit
668 let Inst{27-25} = 0b000;
672 class AI3ldhpr<dag oops, dag iops, Format f, InstrItinClass itin,
673 string opc, string asm, string cstr, list<dag> pattern>
674 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
675 opc, asm, cstr, pattern> {
677 let Inst{5} = 1; // H bit
678 let Inst{6} = 0; // S bit
680 let Inst{20} = 1; // L bit
681 let Inst{21} = 1; // W bit
682 let Inst{24} = 1; // P bit
683 let Inst{27-25} = 0b000;
685 class AI3ldshpr<dag oops, dag iops, Format f, InstrItinClass itin,
686 string opc, string asm, string cstr, list<dag> pattern>
687 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
688 opc, asm, cstr, pattern> {
690 let Inst{5} = 1; // H bit
691 let Inst{6} = 1; // S bit
693 let Inst{20} = 1; // L bit
694 let Inst{21} = 1; // W bit
695 let Inst{24} = 1; // P bit
696 let Inst{27-25} = 0b000;
698 class AI3ldsbpr<dag oops, dag iops, Format f, InstrItinClass itin,
699 string opc, string asm, string cstr, list<dag> pattern>
700 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
701 opc, asm, cstr, pattern> {
703 let Inst{5} = 0; // H bit
704 let Inst{6} = 1; // S bit
706 let Inst{20} = 1; // L bit
707 let Inst{21} = 1; // W bit
708 let Inst{24} = 1; // P bit
709 let Inst{27-25} = 0b000;
711 class AI3lddpr<dag oops, dag iops, Format f, InstrItinClass itin,
712 string opc, string asm, string cstr, list<dag> pattern>
713 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
714 opc, asm, cstr, pattern> {
716 let Inst{5} = 0; // H bit
717 let Inst{6} = 1; // S bit
719 let Inst{20} = 0; // L bit
720 let Inst{21} = 1; // W bit
721 let Inst{24} = 1; // P bit
722 let Inst{27-25} = 0b000;
726 // Pre-indexed stores
727 class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin,
728 string opc, string asm, string cstr, list<dag> pattern>
729 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
730 opc, asm, cstr, pattern> {
732 let Inst{5} = 1; // H bit
733 let Inst{6} = 0; // S bit
735 let Inst{20} = 0; // L bit
736 let Inst{21} = 1; // W bit
737 let Inst{24} = 1; // P bit
738 let Inst{27-25} = 0b000;
740 class AI3stdpr<dag oops, dag iops, Format f, InstrItinClass itin,
741 string opc, string asm, string cstr, list<dag> pattern>
742 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
743 opc, asm, cstr, pattern> {
745 let Inst{5} = 1; // H bit
746 let Inst{6} = 1; // S bit
748 let Inst{20} = 0; // L bit
749 let Inst{21} = 1; // W bit
750 let Inst{24} = 1; // P bit
751 let Inst{27-25} = 0b000;
754 // Post-indexed loads
755 class AI3ldhpo<dag oops, dag iops, Format f, InstrItinClass itin,
756 string opc, string asm, string cstr, list<dag> pattern>
757 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
758 opc, asm, cstr,pattern> {
760 let Inst{5} = 1; // H bit
761 let Inst{6} = 0; // S bit
763 let Inst{20} = 1; // L bit
764 let Inst{21} = 0; // W bit
765 let Inst{24} = 0; // P bit
766 let Inst{27-25} = 0b000;
768 class AI3ldshpo<dag oops, dag iops, Format f, InstrItinClass itin,
769 string opc, string asm, string cstr, list<dag> pattern>
770 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
771 opc, asm, cstr,pattern> {
773 let Inst{5} = 1; // H bit
774 let Inst{6} = 1; // S bit
776 let Inst{20} = 1; // L bit
777 let Inst{21} = 0; // W bit
778 let Inst{24} = 0; // P bit
779 let Inst{27-25} = 0b000;
781 class AI3ldsbpo<dag oops, dag iops, Format f, InstrItinClass itin,
782 string opc, string asm, string cstr, list<dag> pattern>
783 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
784 opc, asm, cstr,pattern> {
786 let Inst{5} = 0; // H bit
787 let Inst{6} = 1; // S bit
789 let Inst{20} = 1; // L bit
790 let Inst{21} = 0; // W bit
791 let Inst{24} = 0; // P bit
792 let Inst{27-25} = 0b000;
794 class AI3lddpo<dag oops, dag iops, Format f, InstrItinClass itin,
795 string opc, string asm, string cstr, list<dag> pattern>
796 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
797 opc, asm, cstr, pattern> {
799 let Inst{5} = 0; // H bit
800 let Inst{6} = 1; // S bit
802 let Inst{20} = 0; // L bit
803 let Inst{21} = 0; // W bit
804 let Inst{24} = 0; // P bit
805 let Inst{27-25} = 0b000;
808 // Post-indexed stores
809 class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin,
810 string opc, string asm, string cstr, list<dag> pattern>
811 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
812 opc, asm, cstr,pattern> {
814 let Inst{5} = 1; // H bit
815 let Inst{6} = 0; // S bit
817 let Inst{20} = 0; // L bit
818 let Inst{21} = 1; // W bit
819 let Inst{24} = 0; // P bit
820 let Inst{27-25} = 0b000;
822 class AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin,
823 string opc, string asm, string cstr, list<dag> pattern>
824 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
825 opc, asm, cstr, pattern> {
827 let Inst{5} = 1; // H bit
828 let Inst{6} = 1; // S bit
830 let Inst{20} = 0; // L bit
831 let Inst{21} = 0; // W bit
832 let Inst{24} = 0; // P bit
833 let Inst{27-25} = 0b000;
837 // addrmode4 instructions
838 class AXI4ld<dag oops, dag iops, Format f, InstrItinClass itin,
839 string asm, list<dag> pattern>
840 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, itin,
842 let Inst{20} = 1; // L bit
843 let Inst{22} = 0; // S bit
844 let Inst{27-25} = 0b100;
846 class AXI4st<dag oops, dag iops, Format f, InstrItinClass itin,
847 string asm, list<dag> pattern>
848 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, itin,
850 let Inst{20} = 0; // L bit
851 let Inst{22} = 0; // S bit
852 let Inst{27-25} = 0b100;
855 // Unsigned multiply, multiply-accumulate instructions.
856 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
857 string opc, string asm, list<dag> pattern>
858 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
859 opc, asm, "", pattern> {
860 let Inst{7-4} = 0b1001;
861 let Inst{20} = 0; // S bit
862 let Inst{27-21} = opcod;
864 class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
865 string opc, string asm, list<dag> pattern>
866 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
867 opc, asm, "", pattern> {
868 let Inst{7-4} = 0b1001;
869 let Inst{27-21} = opcod;
872 // Most significant word multiply
873 class AMul2I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
874 string opc, string asm, list<dag> pattern>
875 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
876 opc, asm, "", pattern> {
877 let Inst{7-4} = 0b1001;
879 let Inst{27-21} = opcod;
882 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
883 class AMulxyI<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
884 string opc, string asm, list<dag> pattern>
885 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
886 opc, asm, "", pattern> {
890 let Inst{27-21} = opcod;
893 // Extend instructions.
894 class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
895 string opc, string asm, list<dag> pattern>
896 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, itin,
897 opc, asm, "", pattern> {
898 let Inst{7-4} = 0b0111;
899 let Inst{27-20} = opcod;
902 // Misc Arithmetic instructions.
903 class AMiscA1I<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
904 string opc, string asm, list<dag> pattern>
905 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin,
906 opc, asm, "", pattern> {
907 let Inst{27-20} = opcod;
910 //===----------------------------------------------------------------------===//
912 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
913 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
914 list<Predicate> Predicates = [IsARM];
916 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
917 list<Predicate> Predicates = [IsARM, HasV5TE];
919 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
920 list<Predicate> Predicates = [IsARM, HasV6];
923 //===----------------------------------------------------------------------===//
925 // Thumb Instruction Format Definitions.
928 // TI - Thumb instruction.
930 class ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
931 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
932 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
933 let OutOperandList = oops;
934 let InOperandList = iops;
936 let Pattern = pattern;
937 list<Predicate> Predicates = [IsThumb];
940 class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
941 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
943 // Two-address instructions
944 class TIt<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
945 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst", pattern>;
947 // tBL, tBX 32-bit instructions
948 class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
949 dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
950 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>, Encoding {
951 let Inst{31-27} = opcod1;
952 let Inst{15-14} = opcod2;
953 let Inst{12} = opcod3;
956 // BR_JT instructions
957 class TJTI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
958 : ThumbI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
961 class Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
962 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
963 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
964 let OutOperandList = oops;
965 let InOperandList = iops;
967 let Pattern = pattern;
968 list<Predicate> Predicates = [IsThumb1Only];
971 class T1I<dag oops, dag iops, InstrItinClass itin,
972 string asm, list<dag> pattern>
973 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
974 class T1Ix2<dag oops, dag iops, InstrItinClass itin,
975 string asm, list<dag> pattern>
976 : Thumb1I<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
977 class T1JTI<dag oops, dag iops, InstrItinClass itin,
978 string asm, list<dag> pattern>
979 : Thumb1I<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
981 // Two-address instructions
982 class T1It<dag oops, dag iops, InstrItinClass itin,
983 string asm, list<dag> pattern>
984 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin,
985 asm, "$lhs = $dst", pattern>;
987 // Thumb1 instruction that can either be predicated or set CPSR.
988 class Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
990 string opc, string asm, string cstr, list<dag> pattern>
991 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
992 let OutOperandList = !con(oops, (ops s_cc_out:$s));
993 let InOperandList = !con(iops, (ops pred:$p));
994 let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm));
995 let Pattern = pattern;
996 list<Predicate> Predicates = [IsThumb1Only];
999 class T1sI<dag oops, dag iops, InstrItinClass itin,
1000 string opc, string asm, list<dag> pattern>
1001 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
1003 // Two-address instructions
1004 class T1sIt<dag oops, dag iops, InstrItinClass itin,
1005 string opc, string asm, list<dag> pattern>
1006 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
1007 "$lhs = $dst", pattern>;
1009 // Thumb1 instruction that can be predicated.
1010 class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1011 InstrItinClass itin,
1012 string opc, string asm, string cstr, list<dag> pattern>
1013 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1014 let OutOperandList = oops;
1015 let InOperandList = !con(iops, (ops pred:$p));
1016 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
1017 let Pattern = pattern;
1018 list<Predicate> Predicates = [IsThumb1Only];
1021 class T1pI<dag oops, dag iops, InstrItinClass itin,
1022 string opc, string asm, list<dag> pattern>
1023 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
1025 // Two-address instructions
1026 class T1pIt<dag oops, dag iops, InstrItinClass itin,
1027 string opc, string asm, list<dag> pattern>
1028 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
1029 "$lhs = $dst", pattern>;
1031 class T1pI1<dag oops, dag iops, InstrItinClass itin,
1032 string opc, string asm, list<dag> pattern>
1033 : Thumb1pI<oops, iops, AddrModeT1_1, Size2Bytes, itin, opc, asm, "", pattern>;
1034 class T1pI2<dag oops, dag iops, InstrItinClass itin,
1035 string opc, string asm, list<dag> pattern>
1036 : Thumb1pI<oops, iops, AddrModeT1_2, Size2Bytes, itin, opc, asm, "", pattern>;
1037 class T1pI4<dag oops, dag iops, InstrItinClass itin,
1038 string opc, string asm, list<dag> pattern>
1039 : Thumb1pI<oops, iops, AddrModeT1_4, Size2Bytes, itin, opc, asm, "", pattern>;
1040 class T1pIs<dag oops, dag iops,
1041 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1042 : Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>;
1044 class Encoding16 : Encoding {
1045 let Inst{31-16} = 0x0000;
1048 // A6.2 16-bit Thumb instruction encoding
1049 class T1Encoding<bits<6> opcode> : Encoding16 {
1050 let Inst{15-10} = opcode;
1053 // A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
1054 class T1General<bits<5> opcode> : Encoding16 {
1055 let Inst{15-14} = 0b00;
1056 let Inst{13-9} = opcode;
1059 // A6.2.2 Data-processing encoding.
1060 class T1DataProcessing<bits<4> opcode> : Encoding16 {
1061 let Inst{15-10} = 0b010000;
1062 let Inst{9-6} = opcode;
1065 // A6.2.3 Special data instructions and branch and exchange encoding.
1066 class T1Special<bits<4> opcode> : Encoding16 {
1067 let Inst{15-10} = 0b010001;
1068 let Inst{9-6} = opcode;
1071 // A6.2.4 Load/store single data item encoding.
1072 class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
1073 let Inst{15-12} = opA;
1074 let Inst{11-9} = opB;
1076 class T1LdSt<bits<3> opB> : T1LoadStore<0b0101, opB>;
1077 class T1LdSt4Imm<bits<3> opB> : T1LoadStore<0b0110, opB>; // Immediate, 4 bytes
1078 class T1LdSt1Imm<bits<3> opB> : T1LoadStore<0b0111, opB>; // Immediate, 1 byte
1079 class T1LdSt2Imm<bits<3> opB> : T1LoadStore<0b1000, opB>; // Immediate, 2 bytes
1080 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
1082 // A6.2.5 Miscellaneous 16-bit instructions encoding.
1083 class T1Misc<bits<7> opcode> : Encoding16 {
1084 let Inst{15-12} = 0b1011;
1085 let Inst{11-5} = opcode;
1088 // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
1089 class Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1090 InstrItinClass itin,
1091 string opc, string asm, string cstr, list<dag> pattern>
1092 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1093 let OutOperandList = oops;
1094 let InOperandList = !con(iops, (ops pred:$p));
1095 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
1096 let Pattern = pattern;
1097 list<Predicate> Predicates = [IsThumb2];
1100 // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as
1101 // an input operand since by default it's a zero register. It will
1102 // become an implicit def once it's "flipped".
1103 // FIXME: This uses unified syntax so {s} comes before {p}. We should make it
1105 class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1106 InstrItinClass itin,
1107 string opc, string asm, string cstr, list<dag> pattern>
1108 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1109 let OutOperandList = oops;
1110 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
1111 let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm));
1112 let Pattern = pattern;
1113 list<Predicate> Predicates = [IsThumb2];
1117 class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1118 InstrItinClass itin,
1119 string asm, string cstr, list<dag> pattern>
1120 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1121 let OutOperandList = oops;
1122 let InOperandList = iops;
1123 let AsmString = asm;
1124 let Pattern = pattern;
1125 list<Predicate> Predicates = [IsThumb2];
1128 class ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1129 InstrItinClass itin,
1130 string asm, string cstr, list<dag> pattern>
1131 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1132 let OutOperandList = oops;
1133 let InOperandList = iops;
1134 let AsmString = asm;
1135 let Pattern = pattern;
1136 list<Predicate> Predicates = [IsThumb1Only];
1139 class T2I<dag oops, dag iops, InstrItinClass itin,
1140 string opc, string asm, list<dag> pattern>
1141 : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1142 class T2Ii12<dag oops, dag iops, InstrItinClass itin,
1143 string opc, string asm, list<dag> pattern>
1144 : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "", pattern>;
1145 class T2Ii8<dag oops, dag iops, InstrItinClass itin,
1146 string opc, string asm, list<dag> pattern>
1147 : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, itin, opc, asm, "", pattern>;
1148 class T2Iso<dag oops, dag iops, InstrItinClass itin,
1149 string opc, string asm, list<dag> pattern>
1150 : Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, itin, opc, asm, "", pattern>;
1151 class T2Ipc<dag oops, dag iops, InstrItinClass itin,
1152 string opc, string asm, list<dag> pattern>
1153 : Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, itin, opc, asm, "", pattern>;
1154 class T2Ii8s4<bit P, bit W, bit load, dag oops, dag iops, InstrItinClass itin,
1155 string opc, string asm, list<dag> pattern>
1156 : Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, itin, opc, asm, "",
1158 let Inst{31-27} = 0b11101;
1159 let Inst{26-25} = 0b00;
1161 let Inst{23} = ?; // The U bit.
1164 let Inst{20} = load;
1167 class T2sI<dag oops, dag iops, InstrItinClass itin,
1168 string opc, string asm, list<dag> pattern>
1169 : Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1171 class T2XI<dag oops, dag iops, InstrItinClass itin,
1172 string asm, list<dag> pattern>
1173 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
1174 class T2JTI<dag oops, dag iops, InstrItinClass itin,
1175 string asm, list<dag> pattern>
1176 : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
1178 class T2Ix2<dag oops, dag iops, InstrItinClass itin,
1179 string opc, string asm, list<dag> pattern>
1180 : Thumb2I<oops, iops, AddrModeNone, Size8Bytes, itin, opc, asm, "", pattern>;
1183 // T2Iidxldst - Thumb2 indexed load / store instructions.
1184 class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre,
1186 AddrMode am, IndexMode im, InstrItinClass itin,
1187 string opc, string asm, string cstr, list<dag> pattern>
1188 : InstARM<am, Size4Bytes, im, ThumbFrm, GenericDomain, cstr, itin> {
1189 let OutOperandList = oops;
1190 let InOperandList = !con(iops, (ops pred:$p));
1191 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
1192 let Pattern = pattern;
1193 list<Predicate> Predicates = [IsThumb2];
1194 let Inst{31-27} = 0b11111;
1195 let Inst{26-25} = 0b00;
1196 let Inst{24} = signed;
1198 let Inst{22-21} = opcod;
1199 let Inst{20} = load;
1201 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1202 let Inst{10} = pre; // The P bit.
1203 let Inst{8} = 1; // The W bit.
1206 // Helper class for disassembly only
1207 // A6.3.16 & A6.3.17
1208 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
1209 class T2I_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops, dag iops,
1210 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1211 : T2I<oops, iops, itin, opc, asm, pattern> {
1212 let Inst{31-27} = 0b11111;
1213 let Inst{26-24} = 0b011;
1214 let Inst{23} = long;
1215 let Inst{22-20} = op22_20;
1216 let Inst{7-4} = op7_4;
1219 // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
1220 class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> {
1221 list<Predicate> Predicates = [IsThumb1Only, HasV5T];
1224 // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
1225 class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
1226 list<Predicate> Predicates = [IsThumb1Only];
1229 // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
1230 class T2Pat<dag pattern, dag result> : Pat<pattern, result> {
1231 list<Predicate> Predicates = [IsThumb2];
1234 //===----------------------------------------------------------------------===//
1236 //===----------------------------------------------------------------------===//
1237 // ARM VFP Instruction templates.
1240 // Almost all VFP instructions are predicable.
1241 class VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1242 IndexMode im, Format f, InstrItinClass itin,
1243 string opc, string asm, string cstr, list<dag> pattern>
1244 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1245 let OutOperandList = oops;
1246 let InOperandList = !con(iops, (ops pred:$p));
1247 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
1248 let Pattern = pattern;
1249 list<Predicate> Predicates = [HasVFP2];
1253 class VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1254 IndexMode im, Format f, InstrItinClass itin,
1255 string asm, string cstr, list<dag> pattern>
1256 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1257 let OutOperandList = oops;
1258 let InOperandList = iops;
1259 let AsmString = asm;
1260 let Pattern = pattern;
1261 list<Predicate> Predicates = [HasVFP2];
1264 class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
1265 string opc, string asm, list<dag> pattern>
1266 : VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
1267 opc, asm, "", pattern>;
1269 // ARM VFP addrmode5 loads and stores
1270 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1271 InstrItinClass itin,
1272 string opc, string asm, list<dag> pattern>
1273 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1274 VFPLdStFrm, itin, opc, asm, "", pattern> {
1275 // TODO: Mark the instructions with the appropriate subtarget info.
1276 let Inst{27-24} = opcod1;
1277 let Inst{21-20} = opcod2;
1278 let Inst{11-8} = 0b1011;
1280 // 64-bit loads & stores operate on both NEON and VFP pipelines.
1281 let Dom = VFPNeonDomain.Value;
1284 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1285 InstrItinClass itin,
1286 string opc, string asm, list<dag> pattern>
1287 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1288 VFPLdStFrm, itin, opc, asm, "", pattern> {
1289 // TODO: Mark the instructions with the appropriate subtarget info.
1290 let Inst{27-24} = opcod1;
1291 let Inst{21-20} = opcod2;
1292 let Inst{11-8} = 0b1010;
1295 // Load / store multiple
1296 class AXDI5<dag oops, dag iops, InstrItinClass itin,
1297 string asm, list<dag> pattern>
1298 : VFPXI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1299 VFPLdStMulFrm, itin, asm, "", pattern> {
1300 // TODO: Mark the instructions with the appropriate subtarget info.
1301 let Inst{27-25} = 0b110;
1302 let Inst{11-8} = 0b1011;
1304 // 64-bit loads & stores operate on both NEON and VFP pipelines.
1305 let Dom = VFPNeonDomain.Value;
1308 class AXSI5<dag oops, dag iops, InstrItinClass itin,
1309 string asm, list<dag> pattern>
1310 : VFPXI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1311 VFPLdStMulFrm, itin, asm, "", pattern> {
1312 // TODO: Mark the instructions with the appropriate subtarget info.
1313 let Inst{27-25} = 0b110;
1314 let Inst{11-8} = 0b1010;
1317 // Double precision, unary
1318 class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1319 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1320 string asm, list<dag> pattern>
1321 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1322 let Inst{27-23} = opcod1;
1323 let Inst{21-20} = opcod2;
1324 let Inst{19-16} = opcod3;
1325 let Inst{11-8} = 0b1011;
1326 let Inst{7-6} = opcod4;
1327 let Inst{4} = opcod5;
1330 // Double precision, binary
1331 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1332 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1333 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1334 let Inst{27-23} = opcod1;
1335 let Inst{21-20} = opcod2;
1336 let Inst{11-8} = 0b1011;
1341 // Single precision, unary
1342 class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1343 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1344 string asm, list<dag> pattern>
1345 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1346 let Inst{27-23} = opcod1;
1347 let Inst{21-20} = opcod2;
1348 let Inst{19-16} = opcod3;
1349 let Inst{11-8} = 0b1010;
1350 let Inst{7-6} = opcod4;
1351 let Inst{4} = opcod5;
1354 // Single precision unary, if no NEON
1355 // Same as ASuI except not available if NEON is enabled
1356 class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1357 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1358 string asm, list<dag> pattern>
1359 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm,
1361 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1364 // Single precision, binary
1365 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1366 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1367 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1368 let Inst{27-23} = opcod1;
1369 let Inst{21-20} = opcod2;
1370 let Inst{11-8} = 0b1010;
1375 // Single precision binary, if no NEON
1376 // Same as ASbI except not available if NEON is enabled
1377 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1378 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1379 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
1380 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1383 // VFP conversion instructions
1384 class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1385 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1387 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> {
1388 let Inst{27-23} = opcod1;
1389 let Inst{21-20} = opcod2;
1390 let Inst{19-16} = opcod3;
1391 let Inst{11-8} = opcod4;
1396 // VFP conversion between floating-point and fixed-point
1397 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
1398 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1400 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
1401 // size (fixed-point number): sx == 0 ? 16 : 32
1402 let Inst{7} = op5; // sx
1405 // VFP conversion instructions, if no NEON
1406 class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1407 dag oops, dag iops, InstrItinClass itin,
1408 string opc, string asm, list<dag> pattern>
1409 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1411 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1414 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
1415 InstrItinClass itin,
1416 string opc, string asm, list<dag> pattern>
1417 : VFPAI<oops, iops, f, itin, opc, asm, pattern> {
1418 let Inst{27-20} = opcod1;
1419 let Inst{11-8} = opcod2;
1423 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1424 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1425 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
1427 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1428 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1429 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
1431 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1432 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1433 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>;
1435 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1436 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1437 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>;
1439 //===----------------------------------------------------------------------===//
1441 //===----------------------------------------------------------------------===//
1442 // ARM NEON Instruction templates.
1445 class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, InstrItinClass itin,
1446 string opc, string dt, string asm, string cstr, list<dag> pattern>
1447 : InstARM<am, Size4Bytes, im, NEONFrm, NeonDomain, cstr, itin> {
1448 let OutOperandList = oops;
1449 let InOperandList = !con(iops, (ops pred:$p));
1450 let AsmString = !strconcat(
1451 !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
1452 !strconcat("\t", asm));
1453 let Pattern = pattern;
1454 list<Predicate> Predicates = [HasNEON];
1457 // Same as NeonI except it does not have a "data type" specifier.
1458 class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, InstrItinClass itin,
1459 string opc, string asm, string cstr, list<dag> pattern>
1460 : InstARM<am, Size4Bytes, im, NEONFrm, NeonDomain, cstr, itin> {
1461 let OutOperandList = oops;
1462 let InOperandList = !con(iops, (ops pred:$p));
1463 let AsmString = !strconcat(!strconcat(opc, "${p}"), !strconcat("\t", asm));
1464 let Pattern = pattern;
1465 list<Predicate> Predicates = [HasNEON];
1468 class NI<dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1470 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, asm, "",
1474 class NI4<dag oops, dag iops, InstrItinClass itin, string opc,
1475 string asm, list<dag> pattern>
1476 : NeonXI<oops, iops, AddrMode4, IndexModeNone, itin, opc, asm, "",
1480 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1481 dag oops, dag iops, InstrItinClass itin,
1482 string opc, string dt, string asm, string cstr, list<dag> pattern>
1483 : NeonI<oops, iops, AddrMode6, IndexModeNone, itin, opc, dt, asm, cstr,
1485 let Inst{31-24} = 0b11110100;
1486 let Inst{23} = op23;
1487 let Inst{21-20} = op21_20;
1488 let Inst{11-8} = op11_8;
1489 let Inst{7-4} = op7_4;
1492 class NDataI<dag oops, dag iops, InstrItinClass itin,
1493 string opc, string dt, string asm, string cstr, list<dag> pattern>
1494 : NeonI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, dt, asm,
1496 let Inst{31-25} = 0b1111001;
1499 class NDataXI<dag oops, dag iops, InstrItinClass itin,
1500 string opc, string asm, string cstr, list<dag> pattern>
1501 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, asm,
1503 let Inst{31-25} = 0b1111001;
1506 // NEON "one register and a modified immediate" format.
1507 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
1509 dag oops, dag iops, InstrItinClass itin,
1510 string opc, string dt, string asm, string cstr, list<dag> pattern>
1511 : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> {
1512 let Inst{23} = op23;
1513 let Inst{21-19} = op21_19;
1514 let Inst{11-8} = op11_8;
1521 // NEON 2 vector register format.
1522 class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1523 bits<5> op11_7, bit op6, bit op4,
1524 dag oops, dag iops, InstrItinClass itin,
1525 string opc, string dt, string asm, string cstr, list<dag> pattern>
1526 : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> {
1527 let Inst{24-23} = op24_23;
1528 let Inst{21-20} = op21_20;
1529 let Inst{19-18} = op19_18;
1530 let Inst{17-16} = op17_16;
1531 let Inst{11-7} = op11_7;
1536 // Same as N2V except it doesn't have a datatype suffix.
1537 class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1538 bits<5> op11_7, bit op6, bit op4,
1539 dag oops, dag iops, InstrItinClass itin,
1540 string opc, string asm, string cstr, list<dag> pattern>
1541 : NDataXI<oops, iops, itin, opc, asm, cstr, pattern> {
1542 let Inst{24-23} = op24_23;
1543 let Inst{21-20} = op21_20;
1544 let Inst{19-18} = op19_18;
1545 let Inst{17-16} = op17_16;
1546 let Inst{11-7} = op11_7;
1551 // NEON 2 vector register with immediate.
1552 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1553 dag oops, dag iops, InstrItinClass itin,
1554 string opc, string dt, string asm, string cstr, list<dag> pattern>
1555 : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> {
1556 let Inst{24} = op24;
1557 let Inst{23} = op23;
1558 let Inst{11-8} = op11_8;
1564 // NEON 3 vector register format.
1565 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1566 dag oops, dag iops, InstrItinClass itin,
1567 string opc, string dt, string asm, string cstr, list<dag> pattern>
1568 : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> {
1569 let Inst{24} = op24;
1570 let Inst{23} = op23;
1571 let Inst{21-20} = op21_20;
1572 let Inst{11-8} = op11_8;
1577 // Same as N3VX except it doesn't have a data type suffix.
1578 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1579 dag oops, dag iops, InstrItinClass itin,
1580 string opc, string asm, string cstr, list<dag> pattern>
1581 : NDataXI<oops, iops, itin, opc, asm, cstr, pattern> {
1582 let Inst{24} = op24;
1583 let Inst{23} = op23;
1584 let Inst{21-20} = op21_20;
1585 let Inst{11-8} = op11_8;
1590 // NEON VMOVs between scalar and core registers.
1591 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1592 dag oops, dag iops, Format f, InstrItinClass itin,
1593 string opc, string dt, string asm, list<dag> pattern>
1594 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, GenericDomain,
1596 let Inst{27-20} = opcod1;
1597 let Inst{11-8} = opcod2;
1598 let Inst{6-5} = opcod3;
1601 let OutOperandList = oops;
1602 let InOperandList = !con(iops, (ops pred:$p));
1603 let AsmString = !strconcat(
1604 !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
1605 !strconcat("\t", asm));
1606 let Pattern = pattern;
1607 list<Predicate> Predicates = [HasNEON];
1609 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1610 dag oops, dag iops, InstrItinClass itin,
1611 string opc, string dt, string asm, list<dag> pattern>
1612 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONGetLnFrm, itin,
1613 opc, dt, asm, pattern>;
1614 class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1615 dag oops, dag iops, InstrItinClass itin,
1616 string opc, string dt, string asm, list<dag> pattern>
1617 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONSetLnFrm, itin,
1618 opc, dt, asm, pattern>;
1619 class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1620 dag oops, dag iops, InstrItinClass itin,
1621 string opc, string dt, string asm, list<dag> pattern>
1622 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONDupFrm, itin,
1623 opc, dt, asm, pattern>;
1625 // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
1626 // for single-precision FP.
1627 class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
1628 list<Predicate> Predicates = [HasNEON,UseNEONForFP];