1 //===- InstCombineSimplifyDemanded.cpp ------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains logic for simplifying instructions based on information
11 // about how they are used.
13 //===----------------------------------------------------------------------===//
16 #include "InstCombine.h"
17 #include "llvm/Target/TargetData.h"
18 #include "llvm/IntrinsicInst.h"
23 /// ShrinkDemandedConstant - Check to see if the specified operand of the
24 /// specified instruction is a constant integer. If so, check to see if there
25 /// are any bits set in the constant that are not demanded. If so, shrink the
26 /// constant and return true.
27 static bool ShrinkDemandedConstant(Instruction *I, unsigned OpNo,
29 assert(I && "No instruction?");
30 assert(OpNo < I->getNumOperands() && "Operand index too large");
32 // If the operand is not a constant integer, nothing to do.
33 ConstantInt *OpC = dyn_cast<ConstantInt>(I->getOperand(OpNo));
34 if (!OpC) return false;
36 // If there are no bits set that aren't demanded, nothing to do.
37 Demanded = Demanded.zextOrTrunc(OpC->getValue().getBitWidth());
38 if ((~Demanded & OpC->getValue()) == 0)
41 // This instruction is producing bits that are not demanded. Shrink the RHS.
42 Demanded &= OpC->getValue();
43 if (I->getOpcode() == Instruction::Add) {
44 // However, if the instruction is an add then the constant may be negated
45 // when the opcode is changed to sub. Check if the transformation is really
46 // shrinking the constant.
47 if (Demanded.abs().getActiveBits() > OpC->getValue().abs().getActiveBits())
50 I->setOperand(OpNo, ConstantInt::get(OpC->getType(), Demanded));
56 /// SimplifyDemandedInstructionBits - Inst is an integer instruction that
57 /// SimplifyDemandedBits knows about. See if the instruction has any
58 /// properties that allow us to simplify its operands.
59 bool InstCombiner::SimplifyDemandedInstructionBits(Instruction &Inst) {
60 unsigned BitWidth = Inst.getType()->getScalarSizeInBits();
61 APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0);
62 APInt DemandedMask(APInt::getAllOnesValue(BitWidth));
64 Value *V = SimplifyDemandedUseBits(&Inst, DemandedMask,
65 KnownZero, KnownOne, 0);
66 if (V == 0) return false;
67 if (V == &Inst) return true;
68 ReplaceInstUsesWith(Inst, V);
72 /// SimplifyDemandedBits - This form of SimplifyDemandedBits simplifies the
73 /// specified instruction operand if possible, updating it in place. It returns
74 /// true if it made any change and false otherwise.
75 bool InstCombiner::SimplifyDemandedBits(Use &U, APInt DemandedMask,
76 APInt &KnownZero, APInt &KnownOne,
78 Value *NewVal = SimplifyDemandedUseBits(U.get(), DemandedMask,
79 KnownZero, KnownOne, Depth);
80 if (NewVal == 0) return false;
86 /// SimplifyDemandedUseBits - This function attempts to replace V with a simpler
87 /// value based on the demanded bits. When this function is called, it is known
88 /// that only the bits set in DemandedMask of the result of V are ever used
89 /// downstream. Consequently, depending on the mask and V, it may be possible
90 /// to replace V with a constant or one of its operands. In such cases, this
91 /// function does the replacement and returns true. In all other cases, it
92 /// returns false after analyzing the expression and setting KnownOne and known
93 /// to be one in the expression. KnownZero contains all the bits that are known
94 /// to be zero in the expression. These are provided to potentially allow the
95 /// caller (which might recursively be SimplifyDemandedBits itself) to simplify
96 /// the expression. KnownOne and KnownZero always follow the invariant that
97 /// KnownOne & KnownZero == 0. That is, a bit can't be both 1 and 0. Note that
98 /// the bits in KnownOne and KnownZero may only be accurate for those bits set
99 /// in DemandedMask. Note also that the bitwidth of V, DemandedMask, KnownZero
100 /// and KnownOne must all be the same.
102 /// This returns null if it did not change anything and it permits no
103 /// simplification. This returns V itself if it did some simplification of V's
104 /// operands based on the information about what bits are demanded. This returns
105 /// some other non-null value if it found out that V is equal to another value
106 /// in the context where the specified bits are demanded, but not for all users.
107 Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
108 APInt &KnownZero, APInt &KnownOne,
110 assert(V != 0 && "Null pointer of Value???");
111 assert(Depth <= 6 && "Limit Search Depth");
112 uint32_t BitWidth = DemandedMask.getBitWidth();
113 Type *VTy = V->getType();
114 assert((TD || !VTy->isPointerTy()) &&
115 "SimplifyDemandedBits needs to know bit widths!");
116 assert((!TD || TD->getTypeSizeInBits(VTy->getScalarType()) == BitWidth) &&
117 (!VTy->isIntOrIntVectorTy() ||
118 VTy->getScalarSizeInBits() == BitWidth) &&
119 KnownZero.getBitWidth() == BitWidth &&
120 KnownOne.getBitWidth() == BitWidth &&
121 "Value *V, DemandedMask, KnownZero and KnownOne "
122 "must have same BitWidth");
123 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
124 // We know all of the bits for a constant!
125 KnownOne = CI->getValue() & DemandedMask;
126 KnownZero = ~KnownOne & DemandedMask;
129 if (isa<ConstantPointerNull>(V)) {
130 // We know all of the bits for a constant!
131 KnownOne.clearAllBits();
132 KnownZero = DemandedMask;
136 KnownZero.clearAllBits();
137 KnownOne.clearAllBits();
138 if (DemandedMask == 0) { // Not demanding any bits from V.
139 if (isa<UndefValue>(V))
141 return UndefValue::get(VTy);
144 if (Depth == 6) // Limit search depth.
147 APInt LHSKnownZero(BitWidth, 0), LHSKnownOne(BitWidth, 0);
148 APInt RHSKnownZero(BitWidth, 0), RHSKnownOne(BitWidth, 0);
150 Instruction *I = dyn_cast<Instruction>(V);
152 ComputeMaskedBits(V, KnownZero, KnownOne, Depth);
153 return 0; // Only analyze instructions.
156 // If there are multiple uses of this value and we aren't at the root, then
157 // we can't do any simplifications of the operands, because DemandedMask
158 // only reflects the bits demanded by *one* of the users.
159 if (Depth != 0 && !I->hasOneUse()) {
160 // Despite the fact that we can't simplify this instruction in all User's
161 // context, we can at least compute the knownzero/knownone bits, and we can
162 // do simplifications that apply to *just* the one user if we know that
163 // this instruction has a simpler value in that context.
164 if (I->getOpcode() == Instruction::And) {
165 // If either the LHS or the RHS are Zero, the result is zero.
166 ComputeMaskedBits(I->getOperand(1), RHSKnownZero, RHSKnownOne, Depth+1);
167 ComputeMaskedBits(I->getOperand(0), LHSKnownZero, LHSKnownOne, Depth+1);
169 // If all of the demanded bits are known 1 on one side, return the other.
170 // These bits cannot contribute to the result of the 'and' in this
172 if ((DemandedMask & ~LHSKnownZero & RHSKnownOne) ==
173 (DemandedMask & ~LHSKnownZero))
174 return I->getOperand(0);
175 if ((DemandedMask & ~RHSKnownZero & LHSKnownOne) ==
176 (DemandedMask & ~RHSKnownZero))
177 return I->getOperand(1);
179 // If all of the demanded bits in the inputs are known zeros, return zero.
180 if ((DemandedMask & (RHSKnownZero|LHSKnownZero)) == DemandedMask)
181 return Constant::getNullValue(VTy);
183 } else if (I->getOpcode() == Instruction::Or) {
184 // We can simplify (X|Y) -> X or Y in the user's context if we know that
185 // only bits from X or Y are demanded.
187 // If either the LHS or the RHS are One, the result is One.
188 ComputeMaskedBits(I->getOperand(1), RHSKnownZero, RHSKnownOne, Depth+1);
189 ComputeMaskedBits(I->getOperand(0), LHSKnownZero, LHSKnownOne, Depth+1);
191 // If all of the demanded bits are known zero on one side, return the
192 // other. These bits cannot contribute to the result of the 'or' in this
194 if ((DemandedMask & ~LHSKnownOne & RHSKnownZero) ==
195 (DemandedMask & ~LHSKnownOne))
196 return I->getOperand(0);
197 if ((DemandedMask & ~RHSKnownOne & LHSKnownZero) ==
198 (DemandedMask & ~RHSKnownOne))
199 return I->getOperand(1);
201 // If all of the potentially set bits on one side are known to be set on
202 // the other side, just use the 'other' side.
203 if ((DemandedMask & (~RHSKnownZero) & LHSKnownOne) ==
204 (DemandedMask & (~RHSKnownZero)))
205 return I->getOperand(0);
206 if ((DemandedMask & (~LHSKnownZero) & RHSKnownOne) ==
207 (DemandedMask & (~LHSKnownZero)))
208 return I->getOperand(1);
211 // Compute the KnownZero/KnownOne bits to simplify things downstream.
212 ComputeMaskedBits(I, KnownZero, KnownOne, Depth);
216 // If this is the root being simplified, allow it to have multiple uses,
217 // just set the DemandedMask to all bits so that we can try to simplify the
218 // operands. This allows visitTruncInst (for example) to simplify the
219 // operand of a trunc without duplicating all the logic below.
220 if (Depth == 0 && !V->hasOneUse())
221 DemandedMask = APInt::getAllOnesValue(BitWidth);
223 switch (I->getOpcode()) {
225 ComputeMaskedBits(I, KnownZero, KnownOne, Depth);
227 case Instruction::And:
228 // If either the LHS or the RHS are Zero, the result is zero.
229 if (SimplifyDemandedBits(I->getOperandUse(1), DemandedMask,
230 RHSKnownZero, RHSKnownOne, Depth+1) ||
231 SimplifyDemandedBits(I->getOperandUse(0), DemandedMask & ~RHSKnownZero,
232 LHSKnownZero, LHSKnownOne, Depth+1))
234 assert(!(RHSKnownZero & RHSKnownOne) && "Bits known to be one AND zero?");
235 assert(!(LHSKnownZero & LHSKnownOne) && "Bits known to be one AND zero?");
237 // If all of the demanded bits are known 1 on one side, return the other.
238 // These bits cannot contribute to the result of the 'and'.
239 if ((DemandedMask & ~LHSKnownZero & RHSKnownOne) ==
240 (DemandedMask & ~LHSKnownZero))
241 return I->getOperand(0);
242 if ((DemandedMask & ~RHSKnownZero & LHSKnownOne) ==
243 (DemandedMask & ~RHSKnownZero))
244 return I->getOperand(1);
246 // If all of the demanded bits in the inputs are known zeros, return zero.
247 if ((DemandedMask & (RHSKnownZero|LHSKnownZero)) == DemandedMask)
248 return Constant::getNullValue(VTy);
250 // If the RHS is a constant, see if we can simplify it.
251 if (ShrinkDemandedConstant(I, 1, DemandedMask & ~LHSKnownZero))
254 // Output known-1 bits are only known if set in both the LHS & RHS.
255 KnownOne = RHSKnownOne & LHSKnownOne;
256 // Output known-0 are known to be clear if zero in either the LHS | RHS.
257 KnownZero = RHSKnownZero | LHSKnownZero;
259 case Instruction::Or:
260 // If either the LHS or the RHS are One, the result is One.
261 if (SimplifyDemandedBits(I->getOperandUse(1), DemandedMask,
262 RHSKnownZero, RHSKnownOne, Depth+1) ||
263 SimplifyDemandedBits(I->getOperandUse(0), DemandedMask & ~RHSKnownOne,
264 LHSKnownZero, LHSKnownOne, Depth+1))
266 assert(!(RHSKnownZero & RHSKnownOne) && "Bits known to be one AND zero?");
267 assert(!(LHSKnownZero & LHSKnownOne) && "Bits known to be one AND zero?");
269 // If all of the demanded bits are known zero on one side, return the other.
270 // These bits cannot contribute to the result of the 'or'.
271 if ((DemandedMask & ~LHSKnownOne & RHSKnownZero) ==
272 (DemandedMask & ~LHSKnownOne))
273 return I->getOperand(0);
274 if ((DemandedMask & ~RHSKnownOne & LHSKnownZero) ==
275 (DemandedMask & ~RHSKnownOne))
276 return I->getOperand(1);
278 // If all of the potentially set bits on one side are known to be set on
279 // the other side, just use the 'other' side.
280 if ((DemandedMask & (~RHSKnownZero) & LHSKnownOne) ==
281 (DemandedMask & (~RHSKnownZero)))
282 return I->getOperand(0);
283 if ((DemandedMask & (~LHSKnownZero) & RHSKnownOne) ==
284 (DemandedMask & (~LHSKnownZero)))
285 return I->getOperand(1);
287 // If the RHS is a constant, see if we can simplify it.
288 if (ShrinkDemandedConstant(I, 1, DemandedMask))
291 // Output known-0 bits are only known if clear in both the LHS & RHS.
292 KnownZero = RHSKnownZero & LHSKnownZero;
293 // Output known-1 are known to be set if set in either the LHS | RHS.
294 KnownOne = RHSKnownOne | LHSKnownOne;
296 case Instruction::Xor: {
297 if (SimplifyDemandedBits(I->getOperandUse(1), DemandedMask,
298 RHSKnownZero, RHSKnownOne, Depth+1) ||
299 SimplifyDemandedBits(I->getOperandUse(0), DemandedMask,
300 LHSKnownZero, LHSKnownOne, Depth+1))
302 assert(!(RHSKnownZero & RHSKnownOne) && "Bits known to be one AND zero?");
303 assert(!(LHSKnownZero & LHSKnownOne) && "Bits known to be one AND zero?");
305 // If all of the demanded bits are known zero on one side, return the other.
306 // These bits cannot contribute to the result of the 'xor'.
307 if ((DemandedMask & RHSKnownZero) == DemandedMask)
308 return I->getOperand(0);
309 if ((DemandedMask & LHSKnownZero) == DemandedMask)
310 return I->getOperand(1);
312 // If all of the demanded bits are known to be zero on one side or the
313 // other, turn this into an *inclusive* or.
314 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
315 if ((DemandedMask & ~RHSKnownZero & ~LHSKnownZero) == 0) {
317 BinaryOperator::CreateOr(I->getOperand(0), I->getOperand(1),
319 return InsertNewInstWith(Or, *I);
322 // If all of the demanded bits on one side are known, and all of the set
323 // bits on that side are also known to be set on the other side, turn this
324 // into an AND, as we know the bits will be cleared.
325 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
326 if ((DemandedMask & (RHSKnownZero|RHSKnownOne)) == DemandedMask) {
328 if ((RHSKnownOne & LHSKnownOne) == RHSKnownOne) {
329 Constant *AndC = Constant::getIntegerValue(VTy,
330 ~RHSKnownOne & DemandedMask);
331 Instruction *And = BinaryOperator::CreateAnd(I->getOperand(0), AndC);
332 return InsertNewInstWith(And, *I);
336 // If the RHS is a constant, see if we can simplify it.
337 // FIXME: for XOR, we prefer to force bits to 1 if they will make a -1.
338 if (ShrinkDemandedConstant(I, 1, DemandedMask))
341 // If our LHS is an 'and' and if it has one use, and if any of the bits we
342 // are flipping are known to be set, then the xor is just resetting those
343 // bits to zero. We can just knock out bits from the 'and' and the 'xor',
344 // simplifying both of them.
345 if (Instruction *LHSInst = dyn_cast<Instruction>(I->getOperand(0)))
346 if (LHSInst->getOpcode() == Instruction::And && LHSInst->hasOneUse() &&
347 isa<ConstantInt>(I->getOperand(1)) &&
348 isa<ConstantInt>(LHSInst->getOperand(1)) &&
349 (LHSKnownOne & RHSKnownOne & DemandedMask) != 0) {
350 ConstantInt *AndRHS = cast<ConstantInt>(LHSInst->getOperand(1));
351 ConstantInt *XorRHS = cast<ConstantInt>(I->getOperand(1));
352 APInt NewMask = ~(LHSKnownOne & RHSKnownOne & DemandedMask);
355 ConstantInt::get(I->getType(), NewMask & AndRHS->getValue());
356 Instruction *NewAnd = BinaryOperator::CreateAnd(I->getOperand(0), AndC);
357 InsertNewInstWith(NewAnd, *I);
360 ConstantInt::get(I->getType(), NewMask & XorRHS->getValue());
361 Instruction *NewXor = BinaryOperator::CreateXor(NewAnd, XorC);
362 return InsertNewInstWith(NewXor, *I);
365 // Output known-0 bits are known if clear or set in both the LHS & RHS.
366 KnownZero= (RHSKnownZero & LHSKnownZero) | (RHSKnownOne & LHSKnownOne);
367 // Output known-1 are known to be set if set in only one of the LHS, RHS.
368 KnownOne = (RHSKnownZero & LHSKnownOne) | (RHSKnownOne & LHSKnownZero);
371 case Instruction::Select:
372 if (SimplifyDemandedBits(I->getOperandUse(2), DemandedMask,
373 RHSKnownZero, RHSKnownOne, Depth+1) ||
374 SimplifyDemandedBits(I->getOperandUse(1), DemandedMask,
375 LHSKnownZero, LHSKnownOne, Depth+1))
377 assert(!(RHSKnownZero & RHSKnownOne) && "Bits known to be one AND zero?");
378 assert(!(LHSKnownZero & LHSKnownOne) && "Bits known to be one AND zero?");
380 // If the operands are constants, see if we can simplify them.
381 if (ShrinkDemandedConstant(I, 1, DemandedMask) ||
382 ShrinkDemandedConstant(I, 2, DemandedMask))
385 // Only known if known in both the LHS and RHS.
386 KnownOne = RHSKnownOne & LHSKnownOne;
387 KnownZero = RHSKnownZero & LHSKnownZero;
389 case Instruction::Trunc: {
390 unsigned truncBf = I->getOperand(0)->getType()->getScalarSizeInBits();
391 DemandedMask = DemandedMask.zext(truncBf);
392 KnownZero = KnownZero.zext(truncBf);
393 KnownOne = KnownOne.zext(truncBf);
394 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMask,
395 KnownZero, KnownOne, Depth+1))
397 DemandedMask = DemandedMask.trunc(BitWidth);
398 KnownZero = KnownZero.trunc(BitWidth);
399 KnownOne = KnownOne.trunc(BitWidth);
400 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
403 case Instruction::BitCast:
404 if (!I->getOperand(0)->getType()->isIntOrIntVectorTy())
405 return 0; // vector->int or fp->int?
407 if (VectorType *DstVTy = dyn_cast<VectorType>(I->getType())) {
408 if (VectorType *SrcVTy =
409 dyn_cast<VectorType>(I->getOperand(0)->getType())) {
410 if (DstVTy->getNumElements() != SrcVTy->getNumElements())
411 // Don't touch a bitcast between vectors of different element counts.
414 // Don't touch a scalar-to-vector bitcast.
416 } else if (I->getOperand(0)->getType()->isVectorTy())
417 // Don't touch a vector-to-scalar bitcast.
420 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMask,
421 KnownZero, KnownOne, Depth+1))
423 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
425 case Instruction::ZExt: {
426 // Compute the bits in the result that are not present in the input.
427 unsigned SrcBitWidth =I->getOperand(0)->getType()->getScalarSizeInBits();
429 DemandedMask = DemandedMask.trunc(SrcBitWidth);
430 KnownZero = KnownZero.trunc(SrcBitWidth);
431 KnownOne = KnownOne.trunc(SrcBitWidth);
432 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMask,
433 KnownZero, KnownOne, Depth+1))
435 DemandedMask = DemandedMask.zext(BitWidth);
436 KnownZero = KnownZero.zext(BitWidth);
437 KnownOne = KnownOne.zext(BitWidth);
438 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
439 // The top bits are known to be zero.
440 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - SrcBitWidth);
443 case Instruction::SExt: {
444 // Compute the bits in the result that are not present in the input.
445 unsigned SrcBitWidth =I->getOperand(0)->getType()->getScalarSizeInBits();
447 APInt InputDemandedBits = DemandedMask &
448 APInt::getLowBitsSet(BitWidth, SrcBitWidth);
450 APInt NewBits(APInt::getHighBitsSet(BitWidth, BitWidth - SrcBitWidth));
451 // If any of the sign extended bits are demanded, we know that the sign
453 if ((NewBits & DemandedMask) != 0)
454 InputDemandedBits.setBit(SrcBitWidth-1);
456 InputDemandedBits = InputDemandedBits.trunc(SrcBitWidth);
457 KnownZero = KnownZero.trunc(SrcBitWidth);
458 KnownOne = KnownOne.trunc(SrcBitWidth);
459 if (SimplifyDemandedBits(I->getOperandUse(0), InputDemandedBits,
460 KnownZero, KnownOne, Depth+1))
462 InputDemandedBits = InputDemandedBits.zext(BitWidth);
463 KnownZero = KnownZero.zext(BitWidth);
464 KnownOne = KnownOne.zext(BitWidth);
465 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
467 // If the sign bit of the input is known set or clear, then we know the
468 // top bits of the result.
470 // If the input sign bit is known zero, or if the NewBits are not demanded
471 // convert this into a zero extension.
472 if (KnownZero[SrcBitWidth-1] || (NewBits & ~DemandedMask) == NewBits) {
473 // Convert to ZExt cast
474 CastInst *NewCast = new ZExtInst(I->getOperand(0), VTy, I->getName());
475 return InsertNewInstWith(NewCast, *I);
476 } else if (KnownOne[SrcBitWidth-1]) { // Input sign bit known set
481 case Instruction::Add: {
482 // Figure out what the input bits are. If the top bits of the and result
483 // are not demanded, then the add doesn't demand them from its input
485 unsigned NLZ = DemandedMask.countLeadingZeros();
487 // If there is a constant on the RHS, there are a variety of xformations
489 if (ConstantInt *RHS = dyn_cast<ConstantInt>(I->getOperand(1))) {
490 // If null, this should be simplified elsewhere. Some of the xforms here
491 // won't work if the RHS is zero.
495 // If the top bit of the output is demanded, demand everything from the
496 // input. Otherwise, we demand all the input bits except NLZ top bits.
497 APInt InDemandedBits(APInt::getLowBitsSet(BitWidth, BitWidth - NLZ));
499 // Find information about known zero/one bits in the input.
500 if (SimplifyDemandedBits(I->getOperandUse(0), InDemandedBits,
501 LHSKnownZero, LHSKnownOne, Depth+1))
504 // If the RHS of the add has bits set that can't affect the input, reduce
506 if (ShrinkDemandedConstant(I, 1, InDemandedBits))
509 // Avoid excess work.
510 if (LHSKnownZero == 0 && LHSKnownOne == 0)
513 // Turn it into OR if input bits are zero.
514 if ((LHSKnownZero & RHS->getValue()) == RHS->getValue()) {
516 BinaryOperator::CreateOr(I->getOperand(0), I->getOperand(1),
518 return InsertNewInstWith(Or, *I);
521 // We can say something about the output known-zero and known-one bits,
522 // depending on potential carries from the input constant and the
523 // unknowns. For example if the LHS is known to have at most the 0x0F0F0
524 // bits set and the RHS constant is 0x01001, then we know we have a known
525 // one mask of 0x00001 and a known zero mask of 0xE0F0E.
527 // To compute this, we first compute the potential carry bits. These are
528 // the bits which may be modified. I'm not aware of a better way to do
530 const APInt &RHSVal = RHS->getValue();
531 APInt CarryBits((~LHSKnownZero + RHSVal) ^ (~LHSKnownZero ^ RHSVal));
533 // Now that we know which bits have carries, compute the known-1/0 sets.
535 // Bits are known one if they are known zero in one operand and one in the
536 // other, and there is no input carry.
537 KnownOne = ((LHSKnownZero & RHSVal) |
538 (LHSKnownOne & ~RHSVal)) & ~CarryBits;
540 // Bits are known zero if they are known zero in both operands and there
541 // is no input carry.
542 KnownZero = LHSKnownZero & ~RHSVal & ~CarryBits;
544 // If the high-bits of this ADD are not demanded, then it does not demand
545 // the high bits of its LHS or RHS.
546 if (DemandedMask[BitWidth-1] == 0) {
547 // Right fill the mask of bits for this ADD to demand the most
548 // significant bit and all those below it.
549 APInt DemandedFromOps(APInt::getLowBitsSet(BitWidth, BitWidth-NLZ));
550 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedFromOps,
551 LHSKnownZero, LHSKnownOne, Depth+1) ||
552 SimplifyDemandedBits(I->getOperandUse(1), DemandedFromOps,
553 LHSKnownZero, LHSKnownOne, Depth+1))
559 case Instruction::Sub:
560 // If the high-bits of this SUB are not demanded, then it does not demand
561 // the high bits of its LHS or RHS.
562 if (DemandedMask[BitWidth-1] == 0) {
563 // Right fill the mask of bits for this SUB to demand the most
564 // significant bit and all those below it.
565 uint32_t NLZ = DemandedMask.countLeadingZeros();
566 APInt DemandedFromOps(APInt::getLowBitsSet(BitWidth, BitWidth-NLZ));
567 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedFromOps,
568 LHSKnownZero, LHSKnownOne, Depth+1) ||
569 SimplifyDemandedBits(I->getOperandUse(1), DemandedFromOps,
570 LHSKnownZero, LHSKnownOne, Depth+1))
574 // Otherwise just hand the sub off to ComputeMaskedBits to fill in
575 // the known zeros and ones.
576 ComputeMaskedBits(V, KnownZero, KnownOne, Depth);
578 // Turn this into a xor if LHS is 2^n-1 and the remaining bits are known
580 if (ConstantInt *C0 = dyn_cast<ConstantInt>(I->getOperand(0))) {
581 APInt I0 = C0->getValue();
582 if ((I0 + 1).isPowerOf2() && (I0 | KnownZero).isAllOnesValue()) {
583 Instruction *Xor = BinaryOperator::CreateXor(I->getOperand(1), C0);
584 return InsertNewInstWith(Xor, *I);
588 case Instruction::Shl:
589 if (ConstantInt *SA = dyn_cast<ConstantInt>(I->getOperand(1))) {
590 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
591 APInt DemandedMaskIn(DemandedMask.lshr(ShiftAmt));
593 // If the shift is NUW/NSW, then it does demand the high bits.
594 ShlOperator *IOp = cast<ShlOperator>(I);
595 if (IOp->hasNoSignedWrap())
596 DemandedMaskIn |= APInt::getHighBitsSet(BitWidth, ShiftAmt+1);
597 else if (IOp->hasNoUnsignedWrap())
598 DemandedMaskIn |= APInt::getHighBitsSet(BitWidth, ShiftAmt);
600 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMaskIn,
601 KnownZero, KnownOne, Depth+1))
603 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
604 KnownZero <<= ShiftAmt;
605 KnownOne <<= ShiftAmt;
606 // low bits known zero.
608 KnownZero |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
611 case Instruction::LShr:
612 // For a logical shift right
613 if (ConstantInt *SA = dyn_cast<ConstantInt>(I->getOperand(1))) {
614 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
616 // Unsigned shift right.
617 APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));
619 // If the shift is exact, then it does demand the low bits (and knows that
621 if (cast<LShrOperator>(I)->isExact())
622 DemandedMaskIn |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
624 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMaskIn,
625 KnownZero, KnownOne, Depth+1))
627 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
628 KnownZero = APIntOps::lshr(KnownZero, ShiftAmt);
629 KnownOne = APIntOps::lshr(KnownOne, ShiftAmt);
631 // Compute the new bits that are at the top now.
632 APInt HighBits(APInt::getHighBitsSet(BitWidth, ShiftAmt));
633 KnownZero |= HighBits; // high bits known zero.
637 case Instruction::AShr:
638 // If this is an arithmetic shift right and only the low-bit is set, we can
639 // always convert this into a logical shr, even if the shift amount is
640 // variable. The low bit of the shift cannot be an input sign bit unless
641 // the shift amount is >= the size of the datatype, which is undefined.
642 if (DemandedMask == 1) {
643 // Perform the logical shift right.
644 Instruction *NewVal = BinaryOperator::CreateLShr(
645 I->getOperand(0), I->getOperand(1), I->getName());
646 return InsertNewInstWith(NewVal, *I);
649 // If the sign bit is the only bit demanded by this ashr, then there is no
650 // need to do it, the shift doesn't change the high bit.
651 if (DemandedMask.isSignBit())
652 return I->getOperand(0);
654 if (ConstantInt *SA = dyn_cast<ConstantInt>(I->getOperand(1))) {
655 uint32_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
657 // Signed shift right.
658 APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));
659 // If any of the "high bits" are demanded, we should set the sign bit as
661 if (DemandedMask.countLeadingZeros() <= ShiftAmt)
662 DemandedMaskIn.setBit(BitWidth-1);
664 // If the shift is exact, then it does demand the low bits (and knows that
666 if (cast<AShrOperator>(I)->isExact())
667 DemandedMaskIn |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
669 if (SimplifyDemandedBits(I->getOperandUse(0), DemandedMaskIn,
670 KnownZero, KnownOne, Depth+1))
672 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
673 // Compute the new bits that are at the top now.
674 APInt HighBits(APInt::getHighBitsSet(BitWidth, ShiftAmt));
675 KnownZero = APIntOps::lshr(KnownZero, ShiftAmt);
676 KnownOne = APIntOps::lshr(KnownOne, ShiftAmt);
678 // Handle the sign bits.
679 APInt SignBit(APInt::getSignBit(BitWidth));
680 // Adjust to where it is now in the mask.
681 SignBit = APIntOps::lshr(SignBit, ShiftAmt);
683 // If the input sign bit is known to be zero, or if none of the top bits
684 // are demanded, turn this into an unsigned shift right.
685 if (BitWidth <= ShiftAmt || KnownZero[BitWidth-ShiftAmt-1] ||
686 (HighBits & ~DemandedMask) == HighBits) {
687 // Perform the logical shift right.
688 BinaryOperator *NewVal = BinaryOperator::CreateLShr(I->getOperand(0),
690 NewVal->setIsExact(cast<BinaryOperator>(I)->isExact());
691 return InsertNewInstWith(NewVal, *I);
692 } else if ((KnownOne & SignBit) != 0) { // New bits are known one.
693 KnownOne |= HighBits;
697 case Instruction::SRem:
698 if (ConstantInt *Rem = dyn_cast<ConstantInt>(I->getOperand(1))) {
699 // X % -1 demands all the bits because we don't want to introduce
700 // INT_MIN % -1 (== undef) by accident.
701 if (Rem->isAllOnesValue())
703 APInt RA = Rem->getValue().abs();
704 if (RA.isPowerOf2()) {
705 if (DemandedMask.ult(RA)) // srem won't affect demanded bits
706 return I->getOperand(0);
708 APInt LowBits = RA - 1;
709 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth);
710 if (SimplifyDemandedBits(I->getOperandUse(0), Mask2,
711 LHSKnownZero, LHSKnownOne, Depth+1))
714 // The low bits of LHS are unchanged by the srem.
715 KnownZero = LHSKnownZero & LowBits;
716 KnownOne = LHSKnownOne & LowBits;
718 // If LHS is non-negative or has all low bits zero, then the upper bits
720 if (LHSKnownZero[BitWidth-1] || ((LHSKnownZero & LowBits) == LowBits))
721 KnownZero |= ~LowBits;
723 // If LHS is negative and not all low bits are zero, then the upper bits
725 if (LHSKnownOne[BitWidth-1] && ((LHSKnownOne & LowBits) != 0))
726 KnownOne |= ~LowBits;
728 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
732 // The sign bit is the LHS's sign bit, except when the result of the
733 // remainder is zero.
734 if (DemandedMask.isNegative() && KnownZero.isNonNegative()) {
735 APInt LHSKnownZero(BitWidth, 0), LHSKnownOne(BitWidth, 0);
736 ComputeMaskedBits(I->getOperand(0), LHSKnownZero, LHSKnownOne, Depth+1);
737 // If it's known zero, our sign bit is also zero.
738 if (LHSKnownZero.isNegative())
739 KnownZero |= LHSKnownZero;
742 case Instruction::URem: {
743 APInt KnownZero2(BitWidth, 0), KnownOne2(BitWidth, 0);
744 APInt AllOnes = APInt::getAllOnesValue(BitWidth);
745 if (SimplifyDemandedBits(I->getOperandUse(0), AllOnes,
746 KnownZero2, KnownOne2, Depth+1) ||
747 SimplifyDemandedBits(I->getOperandUse(1), AllOnes,
748 KnownZero2, KnownOne2, Depth+1))
751 unsigned Leaders = KnownZero2.countLeadingOnes();
752 Leaders = std::max(Leaders,
753 KnownZero2.countLeadingOnes());
754 KnownZero = APInt::getHighBitsSet(BitWidth, Leaders) & DemandedMask;
757 case Instruction::Call:
758 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
759 switch (II->getIntrinsicID()) {
761 case Intrinsic::bswap: {
762 // If the only bits demanded come from one byte of the bswap result,
763 // just shift the input byte into position to eliminate the bswap.
764 unsigned NLZ = DemandedMask.countLeadingZeros();
765 unsigned NTZ = DemandedMask.countTrailingZeros();
767 // Round NTZ down to the next byte. If we have 11 trailing zeros, then
768 // we need all the bits down to bit 8. Likewise, round NLZ. If we
769 // have 14 leading zeros, round to 8.
772 // If we need exactly one byte, we can do this transformation.
773 if (BitWidth-NLZ-NTZ == 8) {
774 unsigned ResultBit = NTZ;
775 unsigned InputBit = BitWidth-NTZ-8;
777 // Replace this with either a left or right shift to get the byte into
780 if (InputBit > ResultBit)
781 NewVal = BinaryOperator::CreateLShr(II->getArgOperand(0),
782 ConstantInt::get(I->getType(), InputBit-ResultBit));
784 NewVal = BinaryOperator::CreateShl(II->getArgOperand(0),
785 ConstantInt::get(I->getType(), ResultBit-InputBit));
787 return InsertNewInstWith(NewVal, *I);
790 // TODO: Could compute known zero/one bits based on the input.
793 case Intrinsic::x86_sse42_crc32_64_8:
794 case Intrinsic::x86_sse42_crc32_64_64:
795 KnownZero = APInt::getHighBitsSet(64, 32);
799 ComputeMaskedBits(V, KnownZero, KnownOne, Depth);
803 // If the client is only demanding bits that we know, return the known
805 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask)
806 return Constant::getIntegerValue(VTy, KnownOne);
811 /// SimplifyDemandedVectorElts - The specified value produces a vector with
812 /// any number of elements. DemandedElts contains the set of elements that are
813 /// actually used by the caller. This method analyzes which elements of the
814 /// operand are undef and returns that information in UndefElts.
816 /// If the information about demanded elements can be used to simplify the
817 /// operation, the operation is simplified, then the resultant value is
818 /// returned. This returns null if no change was made.
819 Value *InstCombiner::SimplifyDemandedVectorElts(Value *V, APInt DemandedElts,
822 unsigned VWidth = cast<VectorType>(V->getType())->getNumElements();
823 APInt EltMask(APInt::getAllOnesValue(VWidth));
824 assert((DemandedElts & ~EltMask) == 0 && "Invalid DemandedElts!");
826 if (isa<UndefValue>(V)) {
827 // If the entire vector is undefined, just return this info.
832 if (DemandedElts == 0) { // If nothing is demanded, provide undef.
834 return UndefValue::get(V->getType());
839 // Handle ConstantAggregateZero, ConstantVector, ConstantDataSequential.
840 if (Constant *C = dyn_cast<Constant>(V)) {
841 // Check if this is identity. If so, return 0 since we are not simplifying
843 if (DemandedElts.isAllOnesValue())
846 Type *EltTy = cast<VectorType>(V->getType())->getElementType();
847 Constant *Undef = UndefValue::get(EltTy);
849 SmallVector<Constant*, 16> Elts;
850 for (unsigned i = 0; i != VWidth; ++i) {
851 if (!DemandedElts[i]) { // If not demanded, set to undef.
852 Elts.push_back(Undef);
857 Constant *Elt = C->getAggregateElement(i);
858 if (Elt == 0) return 0;
860 if (isa<UndefValue>(Elt)) { // Already undef.
861 Elts.push_back(Undef);
863 } else { // Otherwise, defined.
868 // If we changed the constant, return it.
869 Constant *NewCV = ConstantVector::get(Elts);
870 return NewCV != C ? NewCV : 0;
873 // Limit search depth.
877 // If multiple users are using the root value, proceed with
878 // simplification conservatively assuming that all elements
880 if (!V->hasOneUse()) {
881 // Quit if we find multiple users of a non-root value though.
882 // They'll be handled when it's their turn to be visited by
883 // the main instcombine process.
885 // TODO: Just compute the UndefElts information recursively.
888 // Conservatively assume that all elements are needed.
889 DemandedElts = EltMask;
892 Instruction *I = dyn_cast<Instruction>(V);
893 if (!I) return 0; // Only analyze instructions.
895 bool MadeChange = false;
896 APInt UndefElts2(VWidth, 0);
898 switch (I->getOpcode()) {
901 case Instruction::InsertElement: {
902 // If this is a variable index, we don't know which element it overwrites.
903 // demand exactly the same input as we produce.
904 ConstantInt *Idx = dyn_cast<ConstantInt>(I->getOperand(2));
906 // Note that we can't propagate undef elt info, because we don't know
907 // which elt is getting updated.
908 TmpV = SimplifyDemandedVectorElts(I->getOperand(0), DemandedElts,
909 UndefElts2, Depth+1);
910 if (TmpV) { I->setOperand(0, TmpV); MadeChange = true; }
914 // If this is inserting an element that isn't demanded, remove this
916 unsigned IdxNo = Idx->getZExtValue();
917 if (IdxNo >= VWidth || !DemandedElts[IdxNo]) {
919 return I->getOperand(0);
922 // Otherwise, the element inserted overwrites whatever was there, so the
923 // input demanded set is simpler than the output set.
924 APInt DemandedElts2 = DemandedElts;
925 DemandedElts2.clearBit(IdxNo);
926 TmpV = SimplifyDemandedVectorElts(I->getOperand(0), DemandedElts2,
928 if (TmpV) { I->setOperand(0, TmpV); MadeChange = true; }
930 // The inserted element is defined.
931 UndefElts.clearBit(IdxNo);
934 case Instruction::ShuffleVector: {
935 ShuffleVectorInst *Shuffle = cast<ShuffleVectorInst>(I);
937 cast<VectorType>(Shuffle->getOperand(0)->getType())->getNumElements();
938 APInt LeftDemanded(LHSVWidth, 0), RightDemanded(LHSVWidth, 0);
939 for (unsigned i = 0; i < VWidth; i++) {
940 if (DemandedElts[i]) {
941 unsigned MaskVal = Shuffle->getMaskValue(i);
942 if (MaskVal != -1u) {
943 assert(MaskVal < LHSVWidth * 2 &&
944 "shufflevector mask index out of range!");
945 if (MaskVal < LHSVWidth)
946 LeftDemanded.setBit(MaskVal);
948 RightDemanded.setBit(MaskVal - LHSVWidth);
953 APInt UndefElts4(LHSVWidth, 0);
954 TmpV = SimplifyDemandedVectorElts(I->getOperand(0), LeftDemanded,
955 UndefElts4, Depth+1);
956 if (TmpV) { I->setOperand(0, TmpV); MadeChange = true; }
958 APInt UndefElts3(LHSVWidth, 0);
959 TmpV = SimplifyDemandedVectorElts(I->getOperand(1), RightDemanded,
960 UndefElts3, Depth+1);
961 if (TmpV) { I->setOperand(1, TmpV); MadeChange = true; }
963 bool NewUndefElts = false;
964 for (unsigned i = 0; i < VWidth; i++) {
965 unsigned MaskVal = Shuffle->getMaskValue(i);
966 if (MaskVal == -1u) {
968 } else if (!DemandedElts[i]) {
971 } else if (MaskVal < LHSVWidth) {
972 if (UndefElts4[MaskVal]) {
977 if (UndefElts3[MaskVal - LHSVWidth]) {
985 // Add additional discovered undefs.
986 SmallVector<Constant*, 16> Elts;
987 for (unsigned i = 0; i < VWidth; ++i) {
989 Elts.push_back(UndefValue::get(Type::getInt32Ty(I->getContext())));
991 Elts.push_back(ConstantInt::get(Type::getInt32Ty(I->getContext()),
992 Shuffle->getMaskValue(i)));
994 I->setOperand(2, ConstantVector::get(Elts));
999 case Instruction::BitCast: {
1000 // Vector->vector casts only.
1001 VectorType *VTy = dyn_cast<VectorType>(I->getOperand(0)->getType());
1003 unsigned InVWidth = VTy->getNumElements();
1004 APInt InputDemandedElts(InVWidth, 0);
1007 if (VWidth == InVWidth) {
1008 // If we are converting from <4 x i32> -> <4 x f32>, we demand the same
1009 // elements as are demanded of us.
1011 InputDemandedElts = DemandedElts;
1012 } else if (VWidth > InVWidth) {
1016 // If there are more elements in the result than there are in the source,
1017 // then an input element is live if any of the corresponding output
1018 // elements are live.
1019 Ratio = VWidth/InVWidth;
1020 for (unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx) {
1021 if (DemandedElts[OutIdx])
1022 InputDemandedElts.setBit(OutIdx/Ratio);
1028 // If there are more elements in the source than there are in the result,
1029 // then an input element is live if the corresponding output element is
1031 Ratio = InVWidth/VWidth;
1032 for (unsigned InIdx = 0; InIdx != InVWidth; ++InIdx)
1033 if (DemandedElts[InIdx/Ratio])
1034 InputDemandedElts.setBit(InIdx);
1037 // div/rem demand all inputs, because they don't want divide by zero.
1038 TmpV = SimplifyDemandedVectorElts(I->getOperand(0), InputDemandedElts,
1039 UndefElts2, Depth+1);
1041 I->setOperand(0, TmpV);
1045 UndefElts = UndefElts2;
1046 if (VWidth > InVWidth) {
1047 llvm_unreachable("Unimp");
1048 // If there are more elements in the result than there are in the source,
1049 // then an output element is undef if the corresponding input element is
1051 for (unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx)
1052 if (UndefElts2[OutIdx/Ratio])
1053 UndefElts.setBit(OutIdx);
1054 } else if (VWidth < InVWidth) {
1055 llvm_unreachable("Unimp");
1056 // If there are more elements in the source than there are in the result,
1057 // then a result element is undef if all of the corresponding input
1058 // elements are undef.
1059 UndefElts = ~0ULL >> (64-VWidth); // Start out all undef.
1060 for (unsigned InIdx = 0; InIdx != InVWidth; ++InIdx)
1061 if (!UndefElts2[InIdx]) // Not undef?
1062 UndefElts.clearBit(InIdx/Ratio); // Clear undef bit.
1066 case Instruction::And:
1067 case Instruction::Or:
1068 case Instruction::Xor:
1069 case Instruction::Add:
1070 case Instruction::Sub:
1071 case Instruction::Mul:
1072 // div/rem demand all inputs, because they don't want divide by zero.
1073 TmpV = SimplifyDemandedVectorElts(I->getOperand(0), DemandedElts,
1074 UndefElts, Depth+1);
1075 if (TmpV) { I->setOperand(0, TmpV); MadeChange = true; }
1076 TmpV = SimplifyDemandedVectorElts(I->getOperand(1), DemandedElts,
1077 UndefElts2, Depth+1);
1078 if (TmpV) { I->setOperand(1, TmpV); MadeChange = true; }
1080 // Output elements are undefined if both are undefined. Consider things
1081 // like undef&0. The result is known zero, not undef.
1082 UndefElts &= UndefElts2;
1085 case Instruction::Call: {
1086 IntrinsicInst *II = dyn_cast<IntrinsicInst>(I);
1088 switch (II->getIntrinsicID()) {
1091 // Binary vector operations that work column-wise. A dest element is a
1092 // function of the corresponding input elements from the two inputs.
1093 case Intrinsic::x86_sse_sub_ss:
1094 case Intrinsic::x86_sse_mul_ss:
1095 case Intrinsic::x86_sse_min_ss:
1096 case Intrinsic::x86_sse_max_ss:
1097 case Intrinsic::x86_sse2_sub_sd:
1098 case Intrinsic::x86_sse2_mul_sd:
1099 case Intrinsic::x86_sse2_min_sd:
1100 case Intrinsic::x86_sse2_max_sd:
1101 TmpV = SimplifyDemandedVectorElts(II->getArgOperand(0), DemandedElts,
1102 UndefElts, Depth+1);
1103 if (TmpV) { II->setArgOperand(0, TmpV); MadeChange = true; }
1104 TmpV = SimplifyDemandedVectorElts(II->getArgOperand(1), DemandedElts,
1105 UndefElts2, Depth+1);
1106 if (TmpV) { II->setArgOperand(1, TmpV); MadeChange = true; }
1108 // If only the low elt is demanded and this is a scalarizable intrinsic,
1109 // scalarize it now.
1110 if (DemandedElts == 1) {
1111 switch (II->getIntrinsicID()) {
1113 case Intrinsic::x86_sse_sub_ss:
1114 case Intrinsic::x86_sse_mul_ss:
1115 case Intrinsic::x86_sse2_sub_sd:
1116 case Intrinsic::x86_sse2_mul_sd:
1117 // TODO: Lower MIN/MAX/ABS/etc
1118 Value *LHS = II->getArgOperand(0);
1119 Value *RHS = II->getArgOperand(1);
1120 // Extract the element as scalars.
1121 LHS = InsertNewInstWith(ExtractElementInst::Create(LHS,
1122 ConstantInt::get(Type::getInt32Ty(I->getContext()), 0U)), *II);
1123 RHS = InsertNewInstWith(ExtractElementInst::Create(RHS,
1124 ConstantInt::get(Type::getInt32Ty(I->getContext()), 0U)), *II);
1126 switch (II->getIntrinsicID()) {
1127 default: llvm_unreachable("Case stmts out of sync!");
1128 case Intrinsic::x86_sse_sub_ss:
1129 case Intrinsic::x86_sse2_sub_sd:
1130 TmpV = InsertNewInstWith(BinaryOperator::CreateFSub(LHS, RHS,
1131 II->getName()), *II);
1133 case Intrinsic::x86_sse_mul_ss:
1134 case Intrinsic::x86_sse2_mul_sd:
1135 TmpV = InsertNewInstWith(BinaryOperator::CreateFMul(LHS, RHS,
1136 II->getName()), *II);
1141 InsertElementInst::Create(
1142 UndefValue::get(II->getType()), TmpV,
1143 ConstantInt::get(Type::getInt32Ty(I->getContext()), 0U, false),
1145 InsertNewInstWith(New, *II);
1150 // Output elements are undefined if both are undefined. Consider things
1151 // like undef&0. The result is known zero, not undef.
1152 UndefElts &= UndefElts2;
1158 return MadeChange ? I : 0;