1 //===- SparcV8RegisterInfo.cpp - SparcV8 Register Information ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SparcV8 implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "SparcV8RegisterInfo.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/Type.h"
20 #include "llvm/ADT/STLExtras.h"
24 SparcV8RegisterInfo::SparcV8RegisterInfo()
25 : SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
26 V8::ADJCALLSTACKUP) {}
28 static const TargetRegisterClass *getClass(unsigned SrcReg) {
29 if (V8::IntRegsRegisterClass->contains(SrcReg))
30 return V8::IntRegsRegisterClass;
31 else if (V8::FPRegsRegisterClass->contains(SrcReg))
32 return V8::FPRegsRegisterClass;
33 else if (V8::DFPRegsRegisterClass->contains(SrcReg))
34 return V8::DFPRegsRegisterClass;
36 std::cerr << "Error: register of unknown class found: " << SrcReg << "\n";
41 void SparcV8RegisterInfo::
42 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
43 unsigned SrcReg, int FrameIdx,
44 const TargetRegisterClass *rc) const {
45 const TargetRegisterClass *RC = getClass(SrcReg);
47 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
48 if (RC == V8::IntRegsRegisterClass)
49 BuildMI (MBB, I, V8::ST, 3).addFrameIndex (FrameIdx).addSImm (0)
51 else if (RC == V8::FPRegsRegisterClass)
52 BuildMI (MBB, I, V8::STFri, 3).addFrameIndex (FrameIdx).addSImm (0)
54 else if (RC == V8::DFPRegsRegisterClass)
55 BuildMI (MBB, I, V8::STDFri, 3).addFrameIndex (FrameIdx).addSImm (0)
58 assert (0 && "Can't store this register to stack slot");
61 void SparcV8RegisterInfo::
62 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
63 unsigned DestReg, int FrameIdx,
64 const TargetRegisterClass *rc) const {
65 const TargetRegisterClass *RC = getClass(DestReg);
66 if (RC == V8::IntRegsRegisterClass)
67 BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
68 else if (RC == V8::FPRegsRegisterClass)
69 BuildMI (MBB, I, V8::LDFri, 2, DestReg).addFrameIndex (FrameIdx)
71 else if (RC == V8::DFPRegsRegisterClass)
72 BuildMI (MBB, I, V8::LDDFri, 2, DestReg).addFrameIndex (FrameIdx)
75 assert(0 && "Can't load this register from stack slot");
78 void SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
79 MachineBasicBlock::iterator I,
80 unsigned DestReg, unsigned SrcReg,
81 const TargetRegisterClass *RC) const {
82 if (RC == V8::IntRegsRegisterClass)
83 BuildMI (MBB, I, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg);
84 else if (RC == V8::FPRegsRegisterClass)
85 BuildMI (MBB, I, V8::FMOVS, 1, DestReg).addReg (SrcReg);
86 else if (RC == V8::DFPRegsRegisterClass)
87 BuildMI (MBB, I, V8::FpMOVD, 1, DestReg).addReg (SrcReg);
89 assert (0 && "Can't copy this register");
92 void SparcV8RegisterInfo::
93 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
94 MachineBasicBlock::iterator I) const {
95 MachineInstr &MI = *I;
96 int size = MI.getOperand (0).getImmedValue ();
97 if (MI.getOpcode () == V8::ADJCALLSTACKDOWN)
99 BuildMI (MBB, I, V8::ADDri, 2, V8::SP).addReg (V8::SP).addSImm (size);
104 SparcV8RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
106 MachineInstr &MI = *II;
107 while (!MI.getOperand(i).isFrameIndex()) {
109 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
112 int FrameIndex = MI.getOperand(i).getFrameIndex();
114 // Replace frame index with a frame pointer reference
115 MI.SetMachineOperandReg (i, V8::FP);
117 // Addressable stack objects are accessed using neg. offsets from %fp
118 MachineFunction &MF = *MI.getParent()->getParent();
119 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
120 MI.getOperand(i+1).getImmedValue();
122 MI.SetMachineOperandConst (i+1, MachineOperand::MO_SignExtendedImmed, Offset);
125 void SparcV8RegisterInfo::
126 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
128 void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
129 MachineBasicBlock &MBB = MF.front();
130 MachineFrameInfo *MFI = MF.getFrameInfo();
132 // Get the number of bytes to allocate from the FrameInfo
133 int NumBytes = (int) MFI->getStackSize();
135 // Emit the correct save instruction based on the number of bytes in
136 // the frame. Minimum stack frame size according to V8 ABI is:
137 // 16 words for register window spill
138 // 1 word for address of returned aggregate-value
139 // + 6 words for passing parameters on the stack
141 // 23 words * 4 bytes per word = 92 bytes
143 // Round up to next doubleword boundary -- a double-word boundary
144 // is required by the ABI.
145 NumBytes = (NumBytes + 7) & ~7;
146 BuildMI(MBB, MBB.begin(), V8::SAVEri, 2,
147 V8::SP).addImm(-NumBytes).addReg(V8::SP);
150 void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
151 MachineBasicBlock &MBB) const {
152 MachineBasicBlock::iterator MBBI = prior(MBB.end());
153 assert(MBBI->getOpcode() == V8::RETL &&
154 "Can only put epilog before 'retl' instruction!");
155 BuildMI(MBB, MBBI, V8::RESTORErr, 2, V8::G0).addReg(V8::G0).addReg(V8::G0);
158 #include "SparcV8GenRegisterInfo.inc"
160 const TargetRegisterClass*
161 SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const {
162 switch (Ty->getTypeID()) {
163 case Type::FloatTyID: return V8::FPRegsRegisterClass;
164 case Type::DoubleTyID: return V8::DFPRegsRegisterClass;
166 case Type::ULongTyID: assert(0 && "Long values do not fit in registers!");
167 default: assert(0 && "Invalid type to getClass!");
169 case Type::SByteTyID:
170 case Type::UByteTyID:
171 case Type::ShortTyID:
172 case Type::UShortTyID:
175 case Type::PointerTyID: return V8::IntRegsRegisterClass;