Pass extra regclasses into spilling code
authorChris Lattner <sabre@nondot.org>
Fri, 30 Sep 2005 01:29:42 +0000 (01:29 +0000)
committerChris Lattner <sabre@nondot.org>
Fri, 30 Sep 2005 01:29:42 +0000 (01:29 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23537 91177308-0d34-0410-b5e6-96231b3b80d8

12 files changed:
lib/Target/Alpha/AlphaRegisterInfo.cpp
lib/Target/Alpha/AlphaRegisterInfo.h
lib/Target/Skeleton/SkeletonRegisterInfo.cpp
lib/Target/Skeleton/SkeletonRegisterInfo.h
lib/Target/Sparc/SparcRegisterInfo.cpp
lib/Target/Sparc/SparcRegisterInfo.h
lib/Target/SparcV8/SparcV8RegisterInfo.cpp
lib/Target/SparcV8/SparcV8RegisterInfo.h
lib/Target/SparcV9/SparcV9RegisterInfo.cpp
lib/Target/SparcV9/SparcV9RegisterInfo.h
lib/Target/X86/X86RegisterInfo.cpp
lib/Target/X86/X86RegisterInfo.h

index b6c93531c99bfde32665ee4e07171508cc789c56..ac7d3f146f824a8d739f6daa2694397b527a8ec5 100644 (file)
@@ -75,7 +75,8 @@ static const TargetRegisterClass *getClass(unsigned SrcReg) {
 void
 AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                        MachineBasicBlock::iterator MI,
-                                       unsigned SrcReg, int FrameIdx) const {
+                                       unsigned SrcReg, int FrameIdx,
+                                       const TargetRegisterClass *RC) const {
   //std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to " << FrameIdx << "\n";
   //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
   if (EnableAlphaLSMark)
@@ -92,7 +93,8 @@ AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
 void
 AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
                                         MachineBasicBlock::iterator MI,
-                                        unsigned DestReg, int FrameIdx) const{
+                                        unsigned DestReg, int FrameIdx,
+                                        const TargetRegisterClass *RC) const {
   //std::cerr << "Trying to load " << getPrettyName(DestReg) << " to " << FrameIdx << "\n";
   if (EnableAlphaLSMark)
     BuildMI(MBB, MI, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(2)
index d755432321beaf2049a7ad6c0f28f893debce7b2..0d8c24a50e757d1365f2b6dc3589f1d9aa09669a 100644 (file)
@@ -27,11 +27,13 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
   /// Code Generation virtual methods...
   void storeRegToStackSlot(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MBBI,
-                           unsigned SrcReg, int FrameIndex) const;
+                           unsigned SrcReg, int FrameIndex,
+                           const TargetRegisterClass *RC) const;
 
   void loadRegFromStackSlot(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MBBI,
-                            unsigned DestReg, int FrameIndex) const;
+                            unsigned DestReg, int FrameIndex,
+                            const TargetRegisterClass *RC) const;
 
   void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
                     unsigned DestReg, unsigned SrcReg,
index b77487fd3298c960f70def42b22165b8fb6dff5d..3114c8bc963425ce9753d6cb9d425526c7ba4728 100644 (file)
@@ -22,13 +22,15 @@ SkeletonRegisterInfo::SkeletonRegisterInfo()
 
 void SkeletonRegisterInfo::
 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
-                    unsigned SrcReg, int FrameIdx) const {
+                    unsigned SrcReg, int FrameIdx,
+                    const TargetRegisterClass *RC) const {
   abort();
 }
 
 void SkeletonRegisterInfo::
 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
-                     unsigned DestReg, int FrameIdx) const {
+                     unsigned DestReg, int FrameIdx,
+                     const TargetRegisterClass *RC) const {
   abort();
 }
 
index b4ce91e21578f49674428671754844efc26d8d59..58787a2197843a413ba9dd70596078cb6229d997 100644 (file)
@@ -1,4 +1,4 @@
-//===- SkeletonRegisterInfo.h - Skeleton Register Information Impl -*- C++ -*-==//
+//===- SkeletonRegisterInfo.h - Skeleton Register Info Impl ------*- C++ -*-==//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -24,11 +24,13 @@ namespace llvm {
 
     void storeRegToStackSlot(MachineBasicBlock &MBB,
                              MachineBasicBlock::iterator MBBI,
-                             unsigned SrcReg, int FrameIndex) const;
+                             unsigned SrcReg, int FrameIndex,
+                             const TargetRegisterClass *RC) const;
 
     void loadRegFromStackSlot(MachineBasicBlock &MBB,
                               MachineBasicBlock::iterator MBBI,
-                              unsigned DestReg, int FrameIndex) const;
+                              unsigned DestReg, int FrameIndex,
+                              const TargetRegisterClass *RC) const;
 
     void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
                       unsigned DestReg, unsigned SrcReg,
index de3fc8052f67ecab93fc18e215a8d91bb4aea082..af8605a682cded1e41db97eb3b81ba051c32913c 100644 (file)
@@ -40,7 +40,8 @@ static const TargetRegisterClass *getClass(unsigned SrcReg) {
 
 void SparcV8RegisterInfo::
 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
-                    unsigned SrcReg, int FrameIdx) const {
+                    unsigned SrcReg, int FrameIdx,
+                    const TargetRegisterClass *rc) const {
   const TargetRegisterClass *RC = getClass(SrcReg);
 
   // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
@@ -59,7 +60,8 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
 
 void SparcV8RegisterInfo::
 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
-                     unsigned DestReg, int FrameIdx) const {
+                     unsigned DestReg, int FrameIdx,
+                     const TargetRegisterClass *rc) const {
   const TargetRegisterClass *RC = getClass(DestReg);
   if (RC == V8::IntRegsRegisterClass)
     BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
index 851bd8038a201cb217064c44e34b1d600ff47279..09ce548a8be4a44daa5878d045005235249a12eb 100644 (file)
@@ -28,11 +28,13 @@ struct SparcV8RegisterInfo : public SparcV8GenRegisterInfo {
   /// Code Generation virtual methods...
   void storeRegToStackSlot(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MBBI,
-                           unsigned SrcReg, int FrameIndex) const;
+                           unsigned SrcReg, int FrameIndex,
+                           const TargetRegisterClass *RC) const;
 
   void loadRegFromStackSlot(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MBBI,
-                            unsigned DestReg, int FrameIndex) const;
+                            unsigned DestReg, int FrameIndex,
+                            const TargetRegisterClass *RC) const;
 
   void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
                     unsigned DestReg, unsigned SrcReg,
index de3fc8052f67ecab93fc18e215a8d91bb4aea082..af8605a682cded1e41db97eb3b81ba051c32913c 100644 (file)
@@ -40,7 +40,8 @@ static const TargetRegisterClass *getClass(unsigned SrcReg) {
 
 void SparcV8RegisterInfo::
 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
-                    unsigned SrcReg, int FrameIdx) const {
+                    unsigned SrcReg, int FrameIdx,
+                    const TargetRegisterClass *rc) const {
   const TargetRegisterClass *RC = getClass(SrcReg);
 
   // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
@@ -59,7 +60,8 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
 
 void SparcV8RegisterInfo::
 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
-                     unsigned DestReg, int FrameIdx) const {
+                     unsigned DestReg, int FrameIdx,
+                     const TargetRegisterClass *rc) const {
   const TargetRegisterClass *RC = getClass(DestReg);
   if (RC == V8::IntRegsRegisterClass)
     BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
index 851bd8038a201cb217064c44e34b1d600ff47279..09ce548a8be4a44daa5878d045005235249a12eb 100644 (file)
@@ -28,11 +28,13 @@ struct SparcV8RegisterInfo : public SparcV8GenRegisterInfo {
   /// Code Generation virtual methods...
   void storeRegToStackSlot(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MBBI,
-                           unsigned SrcReg, int FrameIndex) const;
+                           unsigned SrcReg, int FrameIndex,
+                           const TargetRegisterClass *RC) const;
 
   void loadRegFromStackSlot(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MBBI,
-                            unsigned DestReg, int FrameIndex) const;
+                            unsigned DestReg, int FrameIndex,
+                            const TargetRegisterClass *RC) const;
 
   void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
                     unsigned DestReg, unsigned SrcReg,
index 0e3428a88e88fc672f6eb9ae975c20a74c5936fe..2bbe7bd42173d9fadfe7746421138f2bee244db4 100644 (file)
@@ -278,13 +278,15 @@ SparcV9RegisterInfo::SparcV9RegisterInfo ()
 
 void SparcV9RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                          MachineBasicBlock::iterator MI,
-                                         unsigned SrcReg, int FrameIndex) const{
+                                         unsigned SrcReg, int FrameIndex,
+                                         const TargetRegisterClass *RC) const {
   abort ();
 }
 
 void SparcV9RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
                                           MachineBasicBlock::iterator MI,
-                                          unsigned DestReg, int FrameIndex) const {
+                                          unsigned DestReg, int FrameIndex,
+                                          const TargetRegisterClass *RC) const {
   abort ();
 }
 
index 07e7910ff4e2c77e4ae2321bfdc980cd9a51dc43..ed810236a8ce3e54fd85eb16d5caba72c0a3d5af 100644 (file)
@@ -27,10 +27,12 @@ struct SparcV9RegisterInfo : public MRegisterInfo {
   // The rest of these are stubs... for now.
   void storeRegToStackSlot(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MI,
-                           unsigned SrcReg, int FrameIndex) const;
+                           unsigned SrcReg, int FrameIndex,
+                           const TargetRegisterClass *RC) const;
   void loadRegFromStackSlot(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MI,
-                            unsigned DestReg, int FrameIndex) const;
+                            unsigned DestReg, int FrameIndex,
+                            const TargetRegisterClass *RC) const;
   void copyRegToReg(MachineBasicBlock &MBB,
                     MachineBasicBlock::iterator MI,
                     unsigned DestReg, unsigned SrcReg,
index 7b8d188b2c3ec619e1873a99ca6911d99505eef1..9fd60fd5185fe52090d148bb11df04ba1d2b02f0 100644 (file)
@@ -58,7 +58,8 @@ static unsigned getIdx(unsigned SpillSize) {
 
 void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                           MachineBasicBlock::iterator MI,
-                                          unsigned SrcReg, int FrameIdx) const {
+                                          unsigned SrcReg, int FrameIdx,
+                                          const TargetRegisterClass *RC) const {
   static const unsigned Opcode[] =
     { X86::MOV8mr, X86::MOV16mr, X86::MOV32mr, X86::FST64m, X86::FSTP80m,
       X86::MOVAPDmr };
@@ -70,7 +71,8 @@ void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
 
 void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
                                            MachineBasicBlock::iterator MI,
-                                           unsigned DestReg, int FrameIdx)const{
+                                           unsigned DestReg, int FrameIdx,
+                                           const TargetRegisterClass *RC) const{
   static const unsigned Opcode[] =
     { X86::MOV8rm, X86::MOV16rm, X86::MOV32rm, X86::FLD64m, X86::FLD80m,
       X86::MOVAPDrm };
index a84be1711b30746079ff658fe96db9bfc17338cd..c6644e767b5b5c1f0e057786870ba40ff566a0a8 100644 (file)
@@ -28,11 +28,13 @@ struct X86RegisterInfo : public X86GenRegisterInfo {
   /// Code Generation virtual methods...
   void storeRegToStackSlot(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MI,
-                           unsigned SrcReg, int FrameIndex) const;
+                           unsigned SrcReg, int FrameIndex,
+                           const TargetRegisterClass *RC) const;
 
   void loadRegFromStackSlot(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MI,
-                            unsigned DestReg, int FrameIndex) const;
+                            unsigned DestReg, int FrameIndex,
+                            const TargetRegisterClass *RC) const;
 
   void copyRegToReg(MachineBasicBlock &MBB,
                     MachineBasicBlock::iterator MI,