MachineBasicBlock::iterator I = MBB->begin();
for (unsigned i = 0, e = RegsToSave.size(); i != e; ++i) {
// Insert the spill to the stack frame.
- RegInfo->storeRegToStackSlot(*MBB, I, RegsToSave[i], StackSlots[i]);
+ RegInfo->storeRegToStackSlot(*MBB, I, RegsToSave[i], StackSlots[i],
+ 0 /*FIXME*/);
}
// Add code to restore the callee-save registers in each exiting block.
// Restore all registers immediately before the return and any terminators
// that preceed it.
for (unsigned i = 0, e = RegsToSave.size(); i != e; ++i) {
- RegInfo->loadRegFromStackSlot(*MBB, I, RegsToSave[i], StackSlots[i]);
+ RegInfo->loadRegFromStackSlot(*MBB, I, RegsToSave[i], StackSlots[i],
+ 0 /*FIXME*/);
assert(I != MBB->begin() &&
"loadRegFromStackSlot didn't insert any code!");
// Insert in reverse order. loadRegFromStackSlot can insert multiple
const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg);
int FrameIndex = getStackSpaceFor(VirtReg, RC);
DEBUG(std::cerr << " to stack slot #" << FrameIndex);
- RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex);
+ RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex, RC);
++NumStores; // Update statistics
}
<< RegInfo->getName(PhysReg) << "\n");
// Add move instruction(s)
- RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex);
+ RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
++NumLoads; // Update statistics
PhysRegsEverUsed[PhysReg] = true;
// Add move instruction(s)
++NumLoads;
- RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx);
+ RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
return PhysReg;
}
// Add move instruction(s)
++NumStores;
- RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx);
+ RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx, RC);
}
unsigned PhysReg = VRM.getPhys(VirtReg);
if (VRM.hasStackSlot(VirtReg)) {
int StackSlot = VRM.getStackSlot(VirtReg);
+ const TargetRegisterClass* RC =
+ MF.getSSARegMap()->getRegClass(VirtReg);
if (MO.isUse() &&
std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
== LoadedRegs.end()) {
- MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot);
+ MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
LoadedRegs.push_back(VirtReg);
++NumLoads;
DEBUG(std::cerr << '\t' << *prior(MII));
}
if (MO.isDef()) {
- MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot);
+ MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
++NumStores;
}
}
// Otherwise, reload it and remember that we have it.
PhysReg = VRM.getPhys(VirtReg);
+ const TargetRegisterClass* RC =
+ MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
RecheckRegister:
// Note that, if we reused a register for a previous operand, the
// was used. This isn't good because it means we have
// to undo a previous reuse.
MRI->loadRegFromStackSlot(MBB, &MI, Op.AssignedPhysReg,
- Op.StackSlot);
+ Op.StackSlot, RC);
ClobberPhysReg(Op.AssignedPhysReg, SpillSlotsAvailable,
PhysRegsAvailable);
}
ContinueReload:
PhysRegsUsed[PhysReg] = true;
- MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot);
+ MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
// This invalidates PhysReg.
ClobberPhysReg(PhysReg, SpillSlotsAvailable, PhysRegsAvailable);
if (!TakenCareOf) {
// The only vregs left are stack slot definitions.
int StackSlot = VRM.getStackSlot(VirtReg);
+ const TargetRegisterClass *RC =
+ MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
unsigned PhysReg;
// If this is a def&use operand, and we used a different physreg for
PhysReg = MO.getReg();
PhysRegsUsed[PhysReg] = true;
- MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot);
+ MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
DEBUG(std::cerr << "Store:\t" << *next(MII));
MI.SetMachineOperandReg(i, PhysReg);