1 //===---- IA64ISelDAGToDAG.cpp - IA64 pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for IA64,
11 // converting a legalized dag to an IA64 dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "ia64-codegen"
17 #include "IA64TargetMachine.h"
18 #include "IA64ISelLowering.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/Constants.h"
25 #include "llvm/GlobalValue.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/MathExtras.h"
34 //===--------------------------------------------------------------------===//
35 /// IA64DAGToDAGISel - IA64 specific code to select IA64 machine
36 /// instructions for SelectionDAG operations.
38 class IA64DAGToDAGISel : public SelectionDAGISel {
39 IA64TargetLowering IA64Lowering;
40 unsigned GlobalBaseReg;
42 IA64DAGToDAGISel(IA64TargetMachine &TM)
43 : SelectionDAGISel(IA64Lowering), IA64Lowering(*TM.getTargetLowering()) {}
45 virtual bool runOnFunction(Function &Fn) {
46 // Make sure we re-emit a set of the global base reg if necessary
48 return SelectionDAGISel::runOnFunction(Fn);
51 /// getI64Imm - Return a target constant with the specified value, of type
53 inline SDOperand getI64Imm(uint64_t Imm) {
54 return CurDAG->getTargetConstant(Imm, MVT::i64);
57 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
58 /// base register. Return the virtual register that holds this value.
59 // SDOperand getGlobalBaseReg(); TODO: hmm
61 // Select - Convert the specified operand from a target-independent to a
62 // target-specific node if it hasn't already been changed.
63 SDNode *Select(SDOperand N);
65 SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
66 unsigned OCHi, unsigned OCLo,
67 bool IsArithmetic = false,
69 SDNode *SelectBitfieldInsert(SDNode *N);
71 /// SelectCC - Select a comparison of the specified values with the
72 /// specified condition code, returning the CR# of the expression.
73 SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
75 /// SelectAddr - Given the specified address, return the two operands for a
76 /// load/store instruction, and return true if it should be an indexed [r+r]
78 bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
80 /// InstructionSelectBasicBlock - This callback is invoked by
81 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
82 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
84 virtual const char *getPassName() const {
85 return "IA64 (Itanium) DAG->DAG Instruction Selector";
88 // Include the pieces autogenerated from the target description.
89 #include "IA64GenDAGISel.inc"
92 SDNode *SelectDIV(SDOperand Op);
96 /// InstructionSelectBasicBlock - This callback is invoked by
97 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
98 void IA64DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
101 // Select target instructions for the DAG.
102 DAG.setRoot(SelectRoot(DAG.getRoot()));
103 DAG.RemoveDeadNodes();
105 // Emit machine code to BB.
106 ScheduleAndEmitDAG(DAG);
109 SDNode *IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
111 SDOperand Chain = N->getOperand(0);
112 SDOperand Tmp1 = N->getOperand(0);
113 SDOperand Tmp2 = N->getOperand(1);
114 AddToISelQueue(Chain);
116 AddToISelQueue(Tmp1);
117 AddToISelQueue(Tmp2);
121 if(MVT::isFloatingPoint(Tmp1.getValueType()))
124 bool isModulus=false; // is it a division or a modulus?
127 switch(N->getOpcode()) {
129 case ISD::SDIV: isModulus=false; isSigned=true; break;
130 case ISD::UDIV: isModulus=false; isSigned=false; break;
132 case ISD::SREM: isModulus=true; isSigned=true; break;
133 case ISD::UREM: isModulus=true; isSigned=false; break;
136 // TODO: check for integer divides by powers of 2 (or other simple patterns?)
138 SDOperand TmpPR, TmpPR2;
139 SDOperand TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8;
140 SDOperand TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15;
143 // we'll need copies of F0 and F1
144 SDOperand F0 = CurDAG->getRegister(IA64::F0, MVT::f64);
145 SDOperand F1 = CurDAG->getRegister(IA64::F1, MVT::f64);
147 // OK, emit some code:
150 // first, load the inputs into FP regs.
152 SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1), 0);
153 Chain = TmpF1.getValue(1);
155 SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2), 0);
156 Chain = TmpF2.getValue(1);
158 // next, convert the inputs to FP
161 SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1), 0);
162 Chain = TmpF3.getValue(1);
164 SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2), 0);
165 Chain = TmpF4.getValue(1);
166 } else { // is unsigned
168 SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1), 0);
169 Chain = TmpF3.getValue(1);
171 SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2), 0);
172 Chain = TmpF4.getValue(1);
175 } else { // this is an FP divide/remainder, so we 'leak' some temp
176 // regs and assign TmpF3=Tmp1, TmpF4=Tmp2
181 // we start by computing an approximate reciprocal (good to 9 bits?)
182 // note, this instruction writes _both_ TmpF5 (answer) and TmpPR (predicate)
184 TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS0, MVT::f64, MVT::i1,
187 TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1,
190 TmpPR = TmpF5.getValue(1);
191 Chain = TmpF5.getValue(2);
194 if(isModulus) { // for remainders, it'll be handy to have
195 // copies of -input_b
196 minusB = SDOperand(CurDAG->getTargetNode(IA64::SUB, MVT::i64,
197 CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2), 0);
198 Chain = minusB.getValue(1);
201 SDOperand TmpE0, TmpY1, TmpE1, TmpY2;
203 SDOperand OpsE0[] = { TmpF4, TmpF5, F1, TmpPR };
204 TmpE0 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
206 Chain = TmpE0.getValue(1);
207 SDOperand OpsY1[] = { TmpF5, TmpE0, TmpF5, TmpPR };
208 TmpY1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
210 Chain = TmpY1.getValue(1);
211 SDOperand OpsE1[] = { TmpE0, TmpE0, F0, TmpPR };
212 TmpE1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
214 Chain = TmpE1.getValue(1);
215 SDOperand OpsY2[] = { TmpY1, TmpE1, TmpY1, TmpPR };
216 TmpY2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
218 Chain = TmpY2.getValue(1);
220 if(isFP) { // if this is an FP divide, we finish up here and exit early
222 assert(0 && "Sorry, try another FORTRAN compiler.");
224 SDOperand TmpE2, TmpY3, TmpQ0, TmpR0;
226 SDOperand OpsE2[] = { TmpE1, TmpE1, F0, TmpPR };
227 TmpE2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
229 Chain = TmpE2.getValue(1);
230 SDOperand OpsY3[] = { TmpY2, TmpE2, TmpY2, TmpPR };
231 TmpY3 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
233 Chain = TmpY3.getValue(1);
234 SDOperand OpsQ0[] = { Tmp1, TmpY3, F0, TmpPR };
236 SDOperand(CurDAG->getTargetNode(IA64::CFMADS1, MVT::f64, // double prec!
238 Chain = TmpQ0.getValue(1);
239 SDOperand OpsR0[] = { Tmp2, TmpQ0, Tmp1, TmpPR };
241 SDOperand(CurDAG->getTargetNode(IA64::CFNMADS1, MVT::f64, // double prec!
243 Chain = TmpR0.getValue(1);
245 // we want Result to have the same target register as the frcpa, so
246 // we two-address hack it. See the comment "for this to work..." on
247 // page 48 of Intel application note #245415
248 SDOperand Ops[] = { TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR };
249 Result = CurDAG->getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg!
251 Chain = SDOperand(Result, 1);
252 return Result; // XXX: early exit!
253 } else { // this is *not* an FP divide, so there's a bit left to do:
255 SDOperand TmpQ2, TmpR2, TmpQ3, TmpQ;
257 SDOperand OpsQ2[] = { TmpF3, TmpY2, F0, TmpPR };
258 TmpQ2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
260 Chain = TmpQ2.getValue(1);
261 SDOperand OpsR2[] = { TmpF4, TmpQ2, TmpF3, TmpPR };
262 TmpR2 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
264 Chain = TmpR2.getValue(1);
266 // we want TmpQ3 to have the same target register as the frcpa? maybe we
267 // should two-address hack it. See the comment "for this to work..." on page
268 // 48 of Intel application note #245415
269 SDOperand OpsQ3[] = { TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR };
270 TmpQ3 = SDOperand(CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64,
272 Chain = TmpQ3.getValue(1);
274 // STORY: without these two-address instructions (TCFMAS1 and TCFMADS0)
275 // the FPSWA won't be able to help out in the case of large/tiny
276 // arguments. Other fun bugs may also appear, e.g. 0/x = x, not 0.
279 TmpQ = SDOperand(CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1,
280 MVT::f64, TmpQ3), 0);
282 TmpQ = SDOperand(CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1,
283 MVT::f64, TmpQ3), 0);
285 Chain = TmpQ.getValue(1);
289 SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, minusB), 0);
290 Chain = FPminusB.getValue(1);
291 SDOperand Remainder =
292 SDOperand(CurDAG->getTargetNode(IA64::XMAL, MVT::f64,
293 TmpQ, FPminusB, TmpF1), 0);
294 Chain = Remainder.getValue(1);
295 Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, Remainder);
296 Chain = SDOperand(Result, 1);
297 } else { // just an integer divide
298 Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, TmpQ);
299 Chain = SDOperand(Result, 1);
303 } // wasn't an FP divide
306 // Select - Convert the specified operand from a target-independent to a
307 // target-specific node if it hasn't already been changed.
308 SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
310 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
311 N->getOpcode() < IA64ISD::FIRST_NUMBER)
312 return NULL; // Already selected.
314 switch (N->getOpcode()) {
317 case IA64ISD::BRCALL: { // XXX: this is also a hack!
318 SDOperand Chain = N->getOperand(0);
319 SDOperand InFlag; // Null incoming flag value.
321 AddToISelQueue(Chain);
322 if(N->getNumOperands()==3) { // we have an incoming chain, callee and flag
323 InFlag = N->getOperand(2);
324 AddToISelQueue(InFlag);
328 SDOperand CallOperand;
330 // if we can call directly, do so
331 if (GlobalAddressSDNode *GASD =
332 dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
333 CallOpcode = IA64::BRCALL_IPREL_GA;
334 CallOperand = CurDAG->getTargetGlobalAddress(GASD->getGlobal(), MVT::i64);
335 } else if (isa<ExternalSymbolSDNode>(N->getOperand(1))) {
336 // FIXME: we currently NEED this case for correctness, to avoid
337 // "non-pic code with imm reloc.n against dynamic symbol" errors
338 CallOpcode = IA64::BRCALL_IPREL_ES;
339 CallOperand = N->getOperand(1);
341 // otherwise we need to load the function descriptor,
342 // load the branch target (function)'s entry point and GP,
343 // branch (call) then restore the GP
344 SDOperand FnDescriptor = N->getOperand(1);
345 AddToISelQueue(FnDescriptor);
347 // load the branch target's entry point [mem] and
349 SDOperand targetEntryPoint=
350 SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, FnDescriptor), 0);
351 Chain = targetEntryPoint.getValue(1);
352 SDOperand targetGPAddr=
353 SDOperand(CurDAG->getTargetNode(IA64::ADDS, MVT::i64,
355 CurDAG->getConstant(8, MVT::i64)), 0);
356 Chain = targetGPAddr.getValue(1);
358 SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, targetGPAddr), 0);
359 Chain = targetGP.getValue(1);
361 Chain = CurDAG->getCopyToReg(Chain, IA64::r1, targetGP, InFlag);
362 InFlag = Chain.getValue(1);
363 Chain = CurDAG->getCopyToReg(Chain, IA64::B6, targetEntryPoint, InFlag); // FLAG these?
364 InFlag = Chain.getValue(1);
366 CallOperand = CurDAG->getRegister(IA64::B6, MVT::i64);
367 CallOpcode = IA64::BRCALL_INDIRECT;
370 // Finally, once everything is setup, emit the call itself
372 Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
373 CallOperand, InFlag), 0);
374 else // there might be no arguments
375 Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
376 CallOperand, Chain), 0);
377 InFlag = Chain.getValue(1);
379 std::vector<SDOperand> CallResults;
381 CallResults.push_back(Chain);
382 CallResults.push_back(InFlag);
384 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
385 ReplaceUses(Op.getValue(i), CallResults[i]);
389 case IA64ISD::GETFD: {
390 SDOperand Input = N->getOperand(0);
391 AddToISelQueue(Input);
392 return CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input);
400 return SelectDIV(Op);
402 case ISD::TargetConstantFP: {
403 SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
406 ConstantFPSDNode* N2 = cast<ConstantFPSDNode>(N);
407 if (N2->getValueAPF().isPosZero()) {
408 V = CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64);
409 } else if (N2->isExactlyValue(N2->getValueType(0) == MVT::f32 ?
410 APFloat(+1.0f) : APFloat(+1.0))) {
411 V = CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64);
413 assert(0 && "Unexpected FP constant!");
415 ReplaceUses(SDOperand(N, 0), V);
419 case ISD::FrameIndex: { // TODO: reduce creepyness
420 int FI = cast<FrameIndexSDNode>(N)->getIndex();
422 return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
423 CurDAG->getTargetFrameIndex(FI, MVT::i64));
425 return CurDAG->getTargetNode(IA64::MOV, MVT::i64,
426 CurDAG->getTargetFrameIndex(FI, MVT::i64));
429 case ISD::ConstantPool: { // TODO: nuke the constant pool
430 // (ia64 doesn't need one)
431 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N);
432 Constant *C = CP->getConstVal();
433 SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64,
435 return CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
436 CurDAG->getRegister(IA64::r1, MVT::i64), CPI);
439 case ISD::GlobalAddress: {
440 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
441 SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
443 SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
444 CurDAG->getRegister(IA64::r1,
446 return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
450 case ISD::ExternalSymbol: {
451 SDOperand EA = CurDAG->getTargetExternalSymbol(
452 cast<ExternalSymbolSDNode>(N)->getSymbol(),
454 SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, MVT::i64,
455 CurDAG->getRegister(IA64::r1,
458 return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
462 case ISD::LOAD: { // FIXME: load -1, not 1, for bools?
463 LoadSDNode *LD = cast<LoadSDNode>(N);
464 SDOperand Chain = LD->getChain();
465 SDOperand Address = LD->getBasePtr();
466 AddToISelQueue(Chain);
467 AddToISelQueue(Address);
469 MVT::ValueType TypeBeingLoaded = LD->getMemoryVT();
471 switch (TypeBeingLoaded) {
476 assert(0 && "Cannot load this type!");
477 case MVT::i1: { // this is a bool
478 Opc = IA64::LD1; // first we load a byte, then compare for != 0
479 if(N->getValueType(0) == MVT::i1) { // XXX: early exit!
480 return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
481 SDOperand(CurDAG->getTargetNode(Opc, MVT::i64, Address), 0),
482 CurDAG->getRegister(IA64::r0, MVT::i64),
485 /* otherwise, we want to load a bool into something bigger: LD1
486 will do that for us, so we just fall through */
488 case MVT::i8: Opc = IA64::LD1; break;
489 case MVT::i16: Opc = IA64::LD2; break;
490 case MVT::i32: Opc = IA64::LD4; break;
491 case MVT::i64: Opc = IA64::LD8; break;
493 case MVT::f32: Opc = IA64::LDF4; break;
494 case MVT::f64: Opc = IA64::LDF8; break;
497 // TODO: comment this
498 return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
503 StoreSDNode *ST = cast<StoreSDNode>(N);
504 SDOperand Address = ST->getBasePtr();
505 SDOperand Chain = ST->getChain();
506 AddToISelQueue(Address);
507 AddToISelQueue(Chain);
510 if (ISD::isNON_TRUNCStore(N)) {
511 switch (N->getOperand(1).getValueType()) {
512 default: assert(0 && "unknown type in store");
513 case MVT::i1: { // this is a bool
514 Opc = IA64::ST1; // we store either 0 or 1 as a byte
516 SDOperand Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64);
517 Chain = Initial.getValue(1);
518 // then load 1 into the same reg iff the predicate to store is 1
519 SDOperand Tmp = ST->getValue();
522 SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
523 CurDAG->getTargetConstant(1, MVT::i64),
525 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
527 case MVT::i64: Opc = IA64::ST8; break;
528 case MVT::f64: Opc = IA64::STF8; break;
530 } else { // Truncating store
531 switch(ST->getMemoryVT()) {
532 default: assert(0 && "unknown type in truncstore");
533 case MVT::i8: Opc = IA64::ST1; break;
534 case MVT::i16: Opc = IA64::ST2; break;
535 case MVT::i32: Opc = IA64::ST4; break;
536 case MVT::f32: Opc = IA64::STF4; break;
540 SDOperand N1 = N->getOperand(1);
541 SDOperand N2 = N->getOperand(2);
544 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain);
548 SDOperand Chain = N->getOperand(0);
549 SDOperand CC = N->getOperand(1);
550 AddToISelQueue(Chain);
552 MachineBasicBlock *Dest =
553 cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
554 //FIXME - we do NOT need long branches all the time
555 return CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC,
556 CurDAG->getBasicBlock(Dest), Chain);
559 case ISD::CALLSEQ_START:
560 case ISD::CALLSEQ_END: {
561 int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
562 unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
563 IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
564 SDOperand N0 = N->getOperand(0);
566 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0);
570 // FIXME: we don't need long branches all the time!
571 SDOperand N0 = N->getOperand(0);
573 return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
574 N->getOperand(1), N0);
577 return SelectCode(Op);
581 /// createIA64DAGToDAGInstructionSelector - This pass converts a legalized DAG
582 /// into an IA64-specific DAG, ready for instruction scheduling.
585 *llvm::createIA64DAGToDAGInstructionSelector(IA64TargetMachine &TM) {
586 return new IA64DAGToDAGISel(TM);