Factor the addressing mode and the load/store VT out of LoadSDNode
authorDan Gohman <gohman@apple.com>
Wed, 30 Jan 2008 00:15:11 +0000 (00:15 +0000)
committerDan Gohman <gohman@apple.com>
Wed, 30 Jan 2008 00:15:11 +0000 (00:15 +0000)
commitb625f2f8960de32bc973092aaee8ac62863006fe
tree36b78c2f63db36a86a3b15aaddd4fd421b8d0edb
parent0d9e976ad2c5479f3d67f8cb09a5908cfc29985c
Factor the addressing mode and the load/store VT out of LoadSDNode
and StoreSDNode into their common base class LSBaseSDNode. Member
functions getLoadedVT and getStoredVT are replaced with the common
getMemoryVT to simplify code that will handle both loads and stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46538 91177308-0d34-0410-b5e6-96231b3b80d8
15 files changed:
include/llvm/CodeGen/SelectionDAGNodes.h
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp
lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
lib/CodeGen/SelectionDAG/TargetLowering.cpp
lib/Target/ARM/ARMISelDAGToDAG.cpp
lib/Target/ARM/ARMISelLowering.cpp
lib/Target/CellSPU/SPUISelLowering.cpp
lib/Target/IA64/IA64ISelDAGToDAG.cpp
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
lib/Target/PowerPC/PPCISelLowering.cpp
lib/Target/TargetSelectionDAG.td