1 //===- AlphaRegisterInfo.cpp - Alpha Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Alpha implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "AlphaRegisterInfo.h"
17 #include "llvm/Constants.h"
18 #include "llvm/Type.h"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineLocation.h"
25 #include "llvm/Target/TargetFrameInfo.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/ADT/BitVector.h"
32 #include "llvm/ADT/STLExtras.h"
37 static const int IMM_LOW = -32768;
38 static const int IMM_HIGH = 32767;
39 static const int IMM_MULT = 65536;
41 static long getUpper16(long l)
43 long y = l / IMM_MULT;
44 if (l % IMM_MULT > IMM_HIGH)
49 static long getLower16(long l)
51 long h = getUpper16(l);
52 return l - h * IMM_MULT;
55 AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
56 : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
61 MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI,
62 SmallVectorImpl<unsigned> &Ops,
63 int FrameIndex) const {
64 if (Ops.size() != 1) return NULL;
66 // Make sure this is a reg-reg copy.
67 unsigned Opc = MI->getOpcode();
69 MachineInstr *NewMI = NULL;
76 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
77 if (Ops[0] == 0) { // move -> store
78 unsigned InReg = MI->getOperand(1).getReg();
79 Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
80 ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
81 NewMI = BuildMI(TII.get(Opc)).addReg(InReg).addFrameIndex(FrameIndex)
83 } else { // load -> move
84 unsigned OutReg = MI->getOperand(0).getReg();
85 Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
86 ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
87 NewMI = BuildMI(TII.get(Opc), OutReg).addFrameIndex(FrameIndex)
94 NewMI->copyKillDeadInfo(MI);
98 void AlphaRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
99 MachineBasicBlock::iterator I,
101 const MachineInstr *Orig) const {
102 MachineInstr *MI = Orig->clone();
103 MI->getOperand(0).setReg(DestReg);
107 const unsigned* AlphaRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
109 static const unsigned CalleeSavedRegs[] = {
110 Alpha::R9, Alpha::R10,
111 Alpha::R11, Alpha::R12,
112 Alpha::R13, Alpha::R14,
113 Alpha::F2, Alpha::F3,
114 Alpha::F4, Alpha::F5,
115 Alpha::F6, Alpha::F7,
116 Alpha::F8, Alpha::F9, 0
118 return CalleeSavedRegs;
121 const TargetRegisterClass* const*
122 AlphaRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
123 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
124 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
125 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
126 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
127 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
128 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
129 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
130 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass, 0
132 return CalleeSavedRegClasses;
135 BitVector AlphaRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
136 BitVector Reserved(getNumRegs());
137 Reserved.set(Alpha::R15);
138 Reserved.set(Alpha::R30);
139 Reserved.set(Alpha::R31);
143 //===----------------------------------------------------------------------===//
144 // Stack Frame Processing methods
145 //===----------------------------------------------------------------------===//
147 // hasFP - Return true if the specified function should have a dedicated frame
148 // pointer register. This is true if the function has variable sized allocas or
149 // if frame pointer elimination is disabled.
151 bool AlphaRegisterInfo::hasFP(const MachineFunction &MF) const {
152 MachineFrameInfo *MFI = MF.getFrameInfo();
153 return MFI->hasVarSizedObjects();
156 void AlphaRegisterInfo::
157 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
158 MachineBasicBlock::iterator I) const {
160 // If we have a frame pointer, turn the adjcallstackup instruction into a
161 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
163 MachineInstr *Old = I;
164 uint64_t Amount = Old->getOperand(0).getImm();
166 // We need to keep the stack aligned properly. To do this, we round the
167 // amount of space needed for the outgoing arguments up to the next
168 // alignment boundary.
169 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
170 Amount = (Amount+Align-1)/Align*Align;
173 if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) {
174 New=BuildMI(TII.get(Alpha::LDA), Alpha::R30)
175 .addImm(-Amount).addReg(Alpha::R30);
177 assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP);
178 New=BuildMI(TII.get(Alpha::LDA), Alpha::R30)
179 .addImm(Amount).addReg(Alpha::R30);
182 // Replace the pseudo instruction with a new instruction...
190 //Alpha has a slightly funny stack:
193 //fixed locals (and spills, callee saved, etc)
198 void AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
199 int SPAdj, RegScavenger *RS) const {
200 assert(SPAdj == 0 && "Unexpected");
203 MachineInstr &MI = *II;
204 MachineBasicBlock &MBB = *MI.getParent();
205 MachineFunction &MF = *MBB.getParent();
208 while (!MI.getOperand(i).isFrameIndex()) {
210 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
213 int FrameIndex = MI.getOperand(i).getIndex();
215 // Add the base register of R30 (SP) or R15 (FP).
216 MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30, false);
218 // Now add the frame object offset to the offset from the virtual frame index.
219 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
221 DOUT << "FI: " << FrameIndex << " Offset: " << Offset << "\n";
223 Offset += MF.getFrameInfo()->getStackSize();
225 DOUT << "Corrected Offset " << Offset
226 << " for stack size: " << MF.getFrameInfo()->getStackSize() << "\n";
228 if (Offset > IMM_HIGH || Offset < IMM_LOW) {
229 DOUT << "Unconditionally using R28 for evil purposes Offset: "
231 //so in this case, we need to use a temporary register, and move the
232 //original inst off the SP/FP
234 MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false);
235 MI.getOperand(i).ChangeToImmediate(getLower16(Offset));
237 MachineInstr* nMI=BuildMI(TII.get(Alpha::LDAH), Alpha::R28)
238 .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30);
241 MI.getOperand(i).ChangeToImmediate(Offset);
246 void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const {
247 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
248 MachineBasicBlock::iterator MBBI = MBB.begin();
249 MachineFrameInfo *MFI = MF.getFrameInfo();
252 static int curgpdist = 0;
255 BuildMI(MBB, MBBI, TII.get(Alpha::LDAHg), Alpha::R29)
256 .addGlobalAddress(const_cast<Function*>(MF.getFunction()))
257 .addReg(Alpha::R27).addImm(++curgpdist);
258 BuildMI(MBB, MBBI, TII.get(Alpha::LDAg), Alpha::R29)
259 .addGlobalAddress(const_cast<Function*>(MF.getFunction()))
260 .addReg(Alpha::R29).addImm(curgpdist);
262 //evil const_cast until MO stuff setup to handle const
263 BuildMI(MBB, MBBI, TII.get(Alpha::ALTENT))
264 .addGlobalAddress(const_cast<Function*>(MF.getFunction()));
266 // Get the number of bytes to allocate from the FrameInfo
267 long NumBytes = MFI->getStackSize();
270 NumBytes += 8; //reserve space for the old FP
272 // Do we need to allocate space on the stack?
273 if (NumBytes == 0) return;
275 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
276 NumBytes = (NumBytes+Align-1)/Align*Align;
278 // Update frame info to pretend that this is part of the stack...
279 MFI->setStackSize(NumBytes);
281 // adjust stack pointer: r30 -= numbytes
282 NumBytes = -NumBytes;
283 if (NumBytes >= IMM_LOW) {
284 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
286 } else if (getUpper16(NumBytes) >= IMM_LOW) {
287 BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30).addImm(getUpper16(NumBytes))
289 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(getLower16(NumBytes))
292 cerr << "Too big a stack frame at " << NumBytes << "\n";
296 //now if we need to, save the old FP and set the new
299 BuildMI(MBB, MBBI, TII.get(Alpha::STQ))
300 .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30);
301 //this must be the last instr in the prolog
302 BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R15)
303 .addReg(Alpha::R30).addReg(Alpha::R30);
308 void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF,
309 MachineBasicBlock &MBB) const {
310 const MachineFrameInfo *MFI = MF.getFrameInfo();
311 MachineBasicBlock::iterator MBBI = prior(MBB.end());
312 assert(MBBI->getOpcode() == Alpha::RETDAG ||
313 MBBI->getOpcode() == Alpha::RETDAGp
314 && "Can only insert epilog into returning blocks");
318 // Get the number of bytes allocated from the FrameInfo...
319 long NumBytes = MFI->getStackSize();
321 //now if we need to, restore the old FP
324 //copy the FP into the SP (discards allocas)
325 BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15)
328 BuildMI(MBB, MBBI, TII.get(Alpha::LDQ), Alpha::R15).addImm(0).addReg(Alpha::R15);
333 if (NumBytes <= IMM_HIGH) {
334 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
336 } else if (getUpper16(NumBytes) <= IMM_HIGH) {
337 BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30)
338 .addImm(getUpper16(NumBytes)).addReg(Alpha::R30);
339 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30)
340 .addImm(getLower16(NumBytes)).addReg(Alpha::R30);
342 cerr << "Too big a stack frame at " << NumBytes << "\n";
348 unsigned AlphaRegisterInfo::getRARegister() const {
349 assert(0 && "What is the return address register");
353 unsigned AlphaRegisterInfo::getFrameRegister(MachineFunction &MF) const {
354 return hasFP(MF) ? Alpha::R15 : Alpha::R30;
357 unsigned AlphaRegisterInfo::getEHExceptionRegister() const {
358 assert(0 && "What is the exception register");
362 unsigned AlphaRegisterInfo::getEHHandlerRegister() const {
363 assert(0 && "What is the exception handler register");
367 int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
368 assert(0 && "What is the dwarf register number");
372 #include "AlphaGenRegisterInfo.inc"
374 std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
376 std::string s(RegisterDescriptors[reg].Name);