return false;
}
- virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned SrcReg, bool isKill, int FrameIndex,
- const TargetRegisterClass *RC) const = 0;
-
- virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const = 0;
-
- virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned DestReg, int FrameIndex,
- const TargetRegisterClass *RC) const = 0;
-
- virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const =0;
-
/// getCrossCopyRegClass - Returns a legal register class to copy a register
/// in the specified class to or from. Returns NULL if it is possible to copy
/// between a two registers of the specified class.
class TargetRegisterClass;
class LiveVariables;
+template<class T> class SmallVectorImpl;
+
//---------------------------------------------------------------------------
// Data types used to define information about a single machine instruction
//---------------------------------------------------------------------------
assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
}
+ virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned SrcReg, bool isKill, int FrameIndex,
+ const TargetRegisterClass *RC) const {
+ assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
+ }
+
+ virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const {
+ assert(0 && "Target didn't implement TargetInstrInfo::storeRegToAddr!");
+ }
+
+ virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned DestReg, int FrameIndex,
+ const TargetRegisterClass *RC) const {
+ assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
+ }
+
+ virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const {
+ assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!");
+ }
+
/// BlockHasNoFallThrough - Return true if the specified block does not
/// fall-through into its successor block. This is primarily used when a
/// branch is unanalyzable. It is useful for things like unconditional
return;
const MRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
-
+ const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
+
// Now that we have a stack slot for each register to be saved, insert spill
// code into the entry block.
MachineBasicBlock *MBB = Fn.begin();
MBB->addLiveIn(CSI[i].getReg());
// Insert the spill to the stack frame.
- RegInfo->storeRegToStackSlot(*MBB, I, CSI[i].getReg(), true,
+ TII.storeRegToStackSlot(*MBB, I, CSI[i].getReg(), true,
CSI[i].getFrameIdx(), CSI[i].getRegClass());
}
}
// Add code to restore the callee-save registers in each exiting block.
- const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
for (MachineFunction::iterator FI = Fn.begin(), E = Fn.end(); FI != E; ++FI)
// If last instruction is a return instruction, add an epilogue.
if (!FI->empty() && TII.isReturn(FI->back().getOpcode())) {
// that preceed it.
if (!RegInfo->restoreCalleeSavedRegisters(*MBB, I, CSI)) {
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
- RegInfo->loadRegFromStackSlot(*MBB, I, CSI[i].getReg(),
+ TII.loadRegFromStackSlot(*MBB, I, CSI[i].getReg(),
CSI[i].getFrameIdx(),
CSI[i].getRegClass());
assert(I != MBB->begin() &&
" the intended one.");
DOUT << " Spilling register " << RegInfo->getName(PhysReg)
<< " containing %reg" << VirtReg;
+
+ const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
+
if (!isVirtRegModified(VirtReg))
DOUT << " which has not been modified, so no store necessary!";
const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
int FrameIndex = getStackSpaceFor(VirtReg, RC);
DOUT << " to stack slot #" << FrameIndex;
- RegInfo->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIndex, RC);
+ TII->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIndex, RC);
++NumStores; // Update statistics
}
<< RegInfo->getName(PhysReg) << "\n";
// Add move instruction(s)
- RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
+ const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
+ TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
++NumLoads; // Update statistics
MF->getRegInfo().setPhysRegUsed(PhysReg);
" the intended one.");
DOUT << " Spilling register " << MRI->getName(PhysReg)
<< " containing %reg" << VirtReg;
+
+ const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
+
if (!isVirtRegModified(VirtReg))
DOUT << " which has not been modified, so no store necessary!";
const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
int FrameIndex = getStackSpaceFor(VirtReg, RC);
DOUT << " to stack slot #" << FrameIndex;
- MRI->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIndex, RC);
+ TII->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIndex, RC);
++NumStores; // Update statistics
}
<< MRI->getName(PhysReg) << "\n";
// Add move instruction(s)
- MRI->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
+ const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
+ TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
++NumLoads; // Update statistics
MF->getRegInfo().setPhysRegUsed(PhysReg);
// Add move instruction(s)
++NumLoads;
- MRI->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
+ const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
+ TII->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
return PhysReg;
}
MachineBasicBlock::iterator I,
unsigned VirtReg, unsigned PhysReg) {
const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(VirtReg);
+ const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
+
int FrameIdx = getStackSpaceFor(VirtReg, RC);
// Add move instruction(s)
++NumStores;
- MRI->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIdx, RC);
+ TII->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIdx, RC);
}
if (!ScavengedReg)
return;
- RegInfo->loadRegFromStackSlot(*MBB, MBBI, ScavengedReg,
+ TII->loadRegFromStackSlot(*MBB, MBBI, ScavengedReg,
ScavengingFrameIndex, ScavengedRC);
MachineBasicBlock::iterator II = prior(MBBI);
RegInfo->eliminateFrameIndex(II, 0, this);
if (ScavengedReg != 0) {
// First restore previously scavenged register.
- RegInfo->loadRegFromStackSlot(*MBB, I, ScavengedReg,
+ TII->loadRegFromStackSlot(*MBB, I, ScavengedReg,
ScavengingFrameIndex, ScavengedRC);
MachineBasicBlock::iterator II = prior(I);
RegInfo->eliminateFrameIndex(II, SPAdj, this);
}
- RegInfo->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC);
+ TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC);
MachineBasicBlock::iterator II = prior(I);
RegInfo->eliminateFrameIndex(II, SPAdj, this);
ScavengedReg = SReg;
DOUT << "********** REWRITE MACHINE CODE **********\n";
DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
const TargetMachine &TM = MF.getTarget();
- const MRegisterInfo &MRI = *TM.getRegisterInfo();
+ const TargetInstrInfo &TII = *TM.getInstrInfo();
+
// LoadedRegs - Keep track of which vregs are loaded, so that we only load
// each vreg once (in the case where a spilled vreg is used by multiple
if (MO.isUse() &&
std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
== LoadedRegs.end()) {
- MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
+ TII.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
LoadedRegs.push_back(VirtReg);
++NumLoads;
DOUT << '\t' << *prior(MII);
}
if (MO.isDef()) {
- MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, true,
+ TII.storeRegToStackSlot(MBB, next(MII), PhysReg, true,
StackSlot, RC);
++NumStores;
}
BitVector &RegKills,
std::vector<MachineOperand*> &KillOps,
VirtRegMap &VRM) {
+ const TargetInstrInfo* TII = MI->getParent()->getParent()->getTarget()
+ .getInstrInfo();
+
if (Reuses.empty()) return PhysReg; // This is most often empty.
for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) {
VRM.getReMaterializedMI(NewOp.VirtReg));
++NumReMats;
} else {
- MRI->loadRegFromStackSlot(*MBB, MI, NewPhysReg,
+ TII->loadRegFromStackSlot(*MBB, MI, NewPhysReg,
NewOp.StackSlotOrReMat, AliasRC);
// Any stores to this stack slot are not dead anymore.
MaybeDeadStores[NewOp.StackSlotOrReMat] = NULL;
BitVector &RegKills,
std::vector<MachineOperand*> &KillOps,
VirtRegMap &VRM) {
- MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, true, StackSlot, RC);
+ TII->storeRegToStackSlot(MBB, next(MII), PhysReg, true, StackSlot, RC);
DOUT << "Store:\t" << *next(MII);
// If there is a dead store to this stack slot, nuke it now.
++NumReMats;
} else {
const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
- MRI->loadRegFromStackSlot(MBB, &MI, Phys, VRM.getStackSlot(VirtReg),
+ TII->loadRegFromStackSlot(MBB, &MI, Phys, VRM.getStackSlot(VirtReg),
RC);
++NumLoads;
}
const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
unsigned Phys = VRM.getPhys(VirtReg);
int StackSlot = VRM.getStackSlot(VirtReg);
- MRI->storeRegToStackSlot(MBB, next(MII), Phys, isKill, StackSlot, RC);
+ TII->storeRegToStackSlot(MBB, next(MII), Phys, isKill, StackSlot, RC);
MachineInstr *StoreMI = next(MII);
DOUT << "Store:\t" << StoreMI;
VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
++NumReMats;
} else {
const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
- MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC);
+ TII->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC);
++NumLoads;
}
// This invalidates PhysReg.
abort();
}
+static const MachineInstrBuilder &ARMInstrAddOperand(MachineInstrBuilder &MIB,
+ MachineOperand &MO) {
+ if (MO.isRegister())
+ MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
+ else if (MO.isImmediate())
+ MIB = MIB.addImm(MO.getImm());
+ else if (MO.isFrameIndex())
+ MIB = MIB.addFrameIndex(MO.getIndex());
+ else
+ assert(0 && "Unknown operand for ARMInstrAddOperand!");
+
+ return MIB;
+}
+
+void ARMInstrInfo::
+storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+ unsigned SrcReg, bool isKill, int FI,
+ const TargetRegisterClass *RC) const {
+ if (RC == ARM::GPRRegisterClass) {
+ MachineFunction &MF = *MBB.getParent();
+ ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
+ if (AFI->isThumbFunction())
+ BuildMI(MBB, I, get(ARM::tSpill)).addReg(SrcReg, false, false, isKill)
+ .addFrameIndex(FI).addImm(0);
+ else
+ AddDefaultPred(BuildMI(MBB, I, get(ARM::STR))
+ .addReg(SrcReg, false, false, isKill)
+ .addFrameIndex(FI).addReg(0).addImm(0));
+ } else if (RC == ARM::DPRRegisterClass) {
+ AddDefaultPred(BuildMI(MBB, I, get(ARM::FSTD))
+ .addReg(SrcReg, false, false, isKill)
+ .addFrameIndex(FI).addImm(0));
+ } else {
+ assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
+ AddDefaultPred(BuildMI(MBB, I, get(ARM::FSTS))
+ .addReg(SrcReg, false, false, isKill)
+ .addFrameIndex(FI).addImm(0));
+ }
+}
+
+void ARMInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
+ bool isKill,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const {
+ unsigned Opc = 0;
+ if (RC == ARM::GPRRegisterClass) {
+ ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
+ if (AFI->isThumbFunction()) {
+ Opc = Addr[0].isFrameIndex() ? ARM::tSpill : ARM::tSTR;
+ MachineInstrBuilder MIB =
+ BuildMI(get(Opc)).addReg(SrcReg, false, false, isKill);
+ for (unsigned i = 0, e = Addr.size(); i != e; ++i)
+ MIB = ARMInstrAddOperand(MIB, Addr[i]);
+ NewMIs.push_back(MIB);
+ return;
+ }
+ Opc = ARM::STR;
+ } else if (RC == ARM::DPRRegisterClass) {
+ Opc = ARM::FSTD;
+ } else {
+ assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
+ Opc = ARM::FSTS;
+ }
+
+ MachineInstrBuilder MIB =
+ BuildMI(get(Opc)).addReg(SrcReg, false, false, isKill);
+ for (unsigned i = 0, e = Addr.size(); i != e; ++i)
+ MIB = ARMInstrAddOperand(MIB, Addr[i]);
+ AddDefaultPred(MIB);
+ NewMIs.push_back(MIB);
+ return;
+}
+
+void ARMInstrInfo::
+loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+ unsigned DestReg, int FI,
+ const TargetRegisterClass *RC) const {
+ if (RC == ARM::GPRRegisterClass) {
+ MachineFunction &MF = *MBB.getParent();
+ ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
+ if (AFI->isThumbFunction())
+ BuildMI(MBB, I, get(ARM::tRestore), DestReg)
+ .addFrameIndex(FI).addImm(0);
+ else
+ AddDefaultPred(BuildMI(MBB, I, get(ARM::LDR), DestReg)
+ .addFrameIndex(FI).addReg(0).addImm(0));
+ } else if (RC == ARM::DPRRegisterClass) {
+ AddDefaultPred(BuildMI(MBB, I, get(ARM::FLDD), DestReg)
+ .addFrameIndex(FI).addImm(0));
+ } else {
+ assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
+ AddDefaultPred(BuildMI(MBB, I, get(ARM::FLDS), DestReg)
+ .addFrameIndex(FI).addImm(0));
+ }
+}
+
+void ARMInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const {
+ unsigned Opc = 0;
+ if (RC == ARM::GPRRegisterClass) {
+ ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
+ if (AFI->isThumbFunction()) {
+ Opc = Addr[0].isFrameIndex() ? ARM::tRestore : ARM::tLDR;
+ MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
+ for (unsigned i = 0, e = Addr.size(); i != e; ++i)
+ MIB = ARMInstrAddOperand(MIB, Addr[i]);
+ NewMIs.push_back(MIB);
+ return;
+ }
+ Opc = ARM::LDR;
+ } else if (RC == ARM::DPRRegisterClass) {
+ Opc = ARM::FLDD;
+ } else {
+ assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
+ Opc = ARM::FLDS;
+ }
+
+ MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
+ for (unsigned i = 0, e = Addr.size(); i != e; ++i)
+ MIB = ARMInstrAddOperand(MIB, Addr[i]);
+ AddDefaultPred(MIB);
+ NewMIs.push_back(MIB);
+ return;
+}
+
bool ARMInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
if (MBB.empty()) return false;
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const;
+ virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ unsigned SrcReg, bool isKill, int FrameIndex,
+ const TargetRegisterClass *RC) const;
+
+ virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const;
+
+ virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ unsigned DestReg, int FrameIndex,
+ const TargetRegisterClass *RC) const;
+
+ virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const;
virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
return MIB.addReg(0);
}
-static const MachineInstrBuilder &ARMInstrAddOperand(MachineInstrBuilder &MIB,
- MachineOperand &MO) {
- if (MO.isRegister())
- MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
- else if (MO.isImmediate())
- MIB = MIB.addImm(MO.getImm());
- else if (MO.isFrameIndex())
- MIB = MIB.addFrameIndex(MO.getIndex());
- else
- assert(0 && "Unknown operand for ARMInstrAddOperand!");
-
- return MIB;
-}
-
-void ARMRegisterInfo::
-storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
- unsigned SrcReg, bool isKill, int FI,
- const TargetRegisterClass *RC) const {
- if (RC == ARM::GPRRegisterClass) {
- MachineFunction &MF = *MBB.getParent();
- ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
- if (AFI->isThumbFunction())
- BuildMI(MBB, I, TII.get(ARM::tSpill)).addReg(SrcReg, false, false, isKill)
- .addFrameIndex(FI).addImm(0);
- else
- AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::STR))
- .addReg(SrcReg, false, false, isKill)
- .addFrameIndex(FI).addReg(0).addImm(0));
- } else if (RC == ARM::DPRRegisterClass) {
- AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::FSTD))
- .addReg(SrcReg, false, false, isKill)
- .addFrameIndex(FI).addImm(0));
- } else {
- assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
- AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::FSTS))
- .addReg(SrcReg, false, false, isKill)
- .addFrameIndex(FI).addImm(0));
- }
-}
-
-void ARMRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
- bool isKill,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const {
- unsigned Opc = 0;
- if (RC == ARM::GPRRegisterClass) {
- ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
- if (AFI->isThumbFunction()) {
- Opc = Addr[0].isFrameIndex() ? ARM::tSpill : ARM::tSTR;
- MachineInstrBuilder MIB =
- BuildMI(TII.get(Opc)).addReg(SrcReg, false, false, isKill);
- for (unsigned i = 0, e = Addr.size(); i != e; ++i)
- MIB = ARMInstrAddOperand(MIB, Addr[i]);
- NewMIs.push_back(MIB);
- return;
- }
- Opc = ARM::STR;
- } else if (RC == ARM::DPRRegisterClass) {
- Opc = ARM::FSTD;
- } else {
- assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
- Opc = ARM::FSTS;
- }
-
- MachineInstrBuilder MIB =
- BuildMI(TII.get(Opc)).addReg(SrcReg, false, false, isKill);
- for (unsigned i = 0, e = Addr.size(); i != e; ++i)
- MIB = ARMInstrAddOperand(MIB, Addr[i]);
- AddDefaultPred(MIB);
- NewMIs.push_back(MIB);
- return;
-}
-
-void ARMRegisterInfo::
-loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
- unsigned DestReg, int FI,
- const TargetRegisterClass *RC) const {
- if (RC == ARM::GPRRegisterClass) {
- MachineFunction &MF = *MBB.getParent();
- ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
- if (AFI->isThumbFunction())
- BuildMI(MBB, I, TII.get(ARM::tRestore), DestReg)
- .addFrameIndex(FI).addImm(0);
- else
- AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::LDR), DestReg)
- .addFrameIndex(FI).addReg(0).addImm(0));
- } else if (RC == ARM::DPRRegisterClass) {
- AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::FLDD), DestReg)
- .addFrameIndex(FI).addImm(0));
- } else {
- assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
- AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::FLDS), DestReg)
- .addFrameIndex(FI).addImm(0));
- }
-}
-
-void ARMRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const {
- unsigned Opc = 0;
- if (RC == ARM::GPRRegisterClass) {
- ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
- if (AFI->isThumbFunction()) {
- Opc = Addr[0].isFrameIndex() ? ARM::tRestore : ARM::tLDR;
- MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
- for (unsigned i = 0, e = Addr.size(); i != e; ++i)
- MIB = ARMInstrAddOperand(MIB, Addr[i]);
- NewMIs.push_back(MIB);
- return;
- }
- Opc = ARM::LDR;
- } else if (RC == ARM::DPRRegisterClass) {
- Opc = ARM::FLDD;
- } else {
- assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
- Opc = ARM::FLDS;
- }
-
- MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
- for (unsigned i = 0, e = Addr.size(); i != e; ++i)
- MIB = ARMInstrAddOperand(MIB, Addr[i]);
- AddDefaultPred(MIB);
- NewMIs.push_back(MIB);
- return;
-}
-
/// emitLoadConstPool - Emits a load from constpool to materialize the
/// specified immediate.
static void emitLoadConstPool(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI) const;
- void storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- unsigned SrcReg, bool isKill, int FrameIndex,
- const TargetRegisterClass *RC) const;
-
- void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const;
-
- void loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- unsigned DestReg, int FrameIndex,
- const TargetRegisterClass *RC) const;
-
- void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const;
-
- void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- unsigned DestReg, unsigned SrcReg,
- const TargetRegisterClass *DestRC,
- const TargetRegisterClass *SrcRC) const;
-
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
unsigned DestReg, const MachineInstr *Orig) const;
}
}
+void
+AlphaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned SrcReg, bool isKill, int FrameIdx,
+ const TargetRegisterClass *RC) const {
+ //cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
+ // << FrameIdx << "\n";
+ //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
+ if (RC == Alpha::F4RCRegisterClass)
+ BuildMI(MBB, MI, get(Alpha::STS))
+ .addReg(SrcReg, false, false, isKill)
+ .addFrameIndex(FrameIdx).addReg(Alpha::F31);
+ else if (RC == Alpha::F8RCRegisterClass)
+ BuildMI(MBB, MI, get(Alpha::STT))
+ .addReg(SrcReg, false, false, isKill)
+ .addFrameIndex(FrameIdx).addReg(Alpha::F31);
+ else if (RC == Alpha::GPRCRegisterClass)
+ BuildMI(MBB, MI, get(Alpha::STQ))
+ .addReg(SrcReg, false, false, isKill)
+ .addFrameIndex(FrameIdx).addReg(Alpha::F31);
+ else
+ abort();
+}
+
+void AlphaInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
+ bool isKill,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const {
+ unsigned Opc = 0;
+ if (RC == Alpha::F4RCRegisterClass)
+ Opc = Alpha::STS;
+ else if (RC == Alpha::F8RCRegisterClass)
+ Opc = Alpha::STT;
+ else if (RC == Alpha::GPRCRegisterClass)
+ Opc = Alpha::STQ;
+ else
+ abort();
+ MachineInstrBuilder MIB =
+ BuildMI(get(Opc)).addReg(SrcReg, false, false, isKill);
+ for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
+ MachineOperand &MO = Addr[i];
+ if (MO.isRegister())
+ MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
+ else
+ MIB.addImm(MO.getImm());
+ }
+ NewMIs.push_back(MIB);
+}
+
+void
+AlphaInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned DestReg, int FrameIdx,
+ const TargetRegisterClass *RC) const {
+ //cerr << "Trying to load " << getPrettyName(DestReg) << " to "
+ // << FrameIdx << "\n";
+ if (RC == Alpha::F4RCRegisterClass)
+ BuildMI(MBB, MI, get(Alpha::LDS), DestReg)
+ .addFrameIndex(FrameIdx).addReg(Alpha::F31);
+ else if (RC == Alpha::F8RCRegisterClass)
+ BuildMI(MBB, MI, get(Alpha::LDT), DestReg)
+ .addFrameIndex(FrameIdx).addReg(Alpha::F31);
+ else if (RC == Alpha::GPRCRegisterClass)
+ BuildMI(MBB, MI, get(Alpha::LDQ), DestReg)
+ .addFrameIndex(FrameIdx).addReg(Alpha::F31);
+ else
+ abort();
+}
+
+void AlphaInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const {
+ unsigned Opc = 0;
+ if (RC == Alpha::F4RCRegisterClass)
+ Opc = Alpha::LDS;
+ else if (RC == Alpha::F8RCRegisterClass)
+ Opc = Alpha::LDT;
+ else if (RC == Alpha::GPRCRegisterClass)
+ Opc = Alpha::LDQ;
+ else
+ abort();
+ MachineInstrBuilder MIB =
+ BuildMI(get(Opc), DestReg);
+ for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
+ MachineOperand &MO = Addr[i];
+ if (MO.isRegister())
+ MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
+ else
+ MIB.addImm(MO.getImm());
+ }
+ NewMIs.push_back(MIB);
+}
+
static unsigned AlphaRevCondCode(unsigned Opcode) {
switch (Opcode) {
case Alpha::BEQ: return Alpha::BNE;
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const;
+ virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ unsigned SrcReg, bool isKill, int FrameIndex,
+ const TargetRegisterClass *RC) const;
+
+ virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const;
+
+ virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ unsigned DestReg, int FrameIndex,
+ const TargetRegisterClass *RC) const;
+
+ virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const;
bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
std::vector<MachineOperand> &Cond) const;
{
}
-void
-AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned SrcReg, bool isKill, int FrameIdx,
- const TargetRegisterClass *RC) const {
- //cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
- // << FrameIdx << "\n";
- //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
- if (RC == Alpha::F4RCRegisterClass)
- BuildMI(MBB, MI, TII.get(Alpha::STS))
- .addReg(SrcReg, false, false, isKill)
- .addFrameIndex(FrameIdx).addReg(Alpha::F31);
- else if (RC == Alpha::F8RCRegisterClass)
- BuildMI(MBB, MI, TII.get(Alpha::STT))
- .addReg(SrcReg, false, false, isKill)
- .addFrameIndex(FrameIdx).addReg(Alpha::F31);
- else if (RC == Alpha::GPRCRegisterClass)
- BuildMI(MBB, MI, TII.get(Alpha::STQ))
- .addReg(SrcReg, false, false, isKill)
- .addFrameIndex(FrameIdx).addReg(Alpha::F31);
- else
- abort();
-}
-
-void AlphaRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
- bool isKill,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const {
- unsigned Opc = 0;
- if (RC == Alpha::F4RCRegisterClass)
- Opc = Alpha::STS;
- else if (RC == Alpha::F8RCRegisterClass)
- Opc = Alpha::STT;
- else if (RC == Alpha::GPRCRegisterClass)
- Opc = Alpha::STQ;
- else
- abort();
- MachineInstrBuilder MIB =
- BuildMI(TII.get(Opc)).addReg(SrcReg, false, false, isKill);
- for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
- MachineOperand &MO = Addr[i];
- if (MO.isRegister())
- MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
- else
- MIB.addImm(MO.getImm());
- }
- NewMIs.push_back(MIB);
-}
-
-void
-AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned DestReg, int FrameIdx,
- const TargetRegisterClass *RC) const {
- //cerr << "Trying to load " << getPrettyName(DestReg) << " to "
- // << FrameIdx << "\n";
- if (RC == Alpha::F4RCRegisterClass)
- BuildMI(MBB, MI, TII.get(Alpha::LDS), DestReg)
- .addFrameIndex(FrameIdx).addReg(Alpha::F31);
- else if (RC == Alpha::F8RCRegisterClass)
- BuildMI(MBB, MI, TII.get(Alpha::LDT), DestReg)
- .addFrameIndex(FrameIdx).addReg(Alpha::F31);
- else if (RC == Alpha::GPRCRegisterClass)
- BuildMI(MBB, MI, TII.get(Alpha::LDQ), DestReg)
- .addFrameIndex(FrameIdx).addReg(Alpha::F31);
- else
- abort();
-}
-
-void AlphaRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const {
- unsigned Opc = 0;
- if (RC == Alpha::F4RCRegisterClass)
- Opc = Alpha::LDS;
- else if (RC == Alpha::F8RCRegisterClass)
- Opc = Alpha::LDT;
- else if (RC == Alpha::GPRCRegisterClass)
- Opc = Alpha::LDQ;
- else
- abort();
- MachineInstrBuilder MIB =
- BuildMI(TII.get(Opc), DestReg);
- for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
- MachineOperand &MO = Addr[i];
- if (MO.isRegister())
- MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
- else
- MIB.addImm(MO.getImm());
- }
- NewMIs.push_back(MIB);
-}
-
MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI,
SmallVectorImpl<unsigned> &Ops,
int FrameIndex) const {
AlphaRegisterInfo(const TargetInstrInfo &tii);
/// Code Generation virtual methods...
- void storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- unsigned SrcReg, bool isKill, int FrameIndex,
- const TargetRegisterClass *RC) const;
-
- void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const;
-
- void loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- unsigned DestReg, int FrameIndex,
- const TargetRegisterClass *RC) const;
-
- void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const;
-
MachineInstr* foldMemoryOperand(MachineInstr* MI,
SmallVectorImpl<unsigned> &Ops,
int FrameIndex) const;
return 0;
}
- void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- unsigned DestReg, unsigned SrcReg,
- const TargetRegisterClass *DestRC,
- const TargetRegisterClass *SrcRC) const;
-
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
unsigned DestReg, const MachineInstr *Orig) const;
#include "SPURegisterNames.h"
#include "SPUInstrInfo.h"
+#include "SPUInstrBuilder.h"
#include "SPUTargetMachine.h"
#include "SPUGenInstrInfo.inc"
#include "llvm/CodeGen/MachineInstrBuilder.h"
const TargetRegisterClass *SrcRC) const
{
if (DestRC != SrcRC) {
- cerr << "SPURegisterInfo::copyRegToReg(): DestRC != SrcRC not supported!\n";
+ cerr << "SPUInstrInfo::copyRegToReg(): DestRC != SrcRC not supported!\n";
abort();
}
abort();
}
}
+
+void
+SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned SrcReg, bool isKill, int FrameIdx,
+ const TargetRegisterClass *RC) const
+{
+ MachineOpCode opc;
+ if (RC == SPU::GPRCRegisterClass) {
+ opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
+ ? SPU::STQDr128
+ : SPU::STQXr128;
+ } else if (RC == SPU::R64CRegisterClass) {
+ opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
+ ? SPU::STQDr64
+ : SPU::STQXr64;
+ } else if (RC == SPU::R64FPRegisterClass) {
+ opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
+ ? SPU::STQDr64
+ : SPU::STQXr64;
+ } else if (RC == SPU::R32CRegisterClass) {
+ opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
+ ? SPU::STQDr32
+ : SPU::STQXr32;
+ } else if (RC == SPU::R32FPRegisterClass) {
+ opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
+ ? SPU::STQDr32
+ : SPU::STQXr32;
+ } else if (RC == SPU::R16CRegisterClass) {
+ opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) ?
+ SPU::STQDr16
+ : SPU::STQXr16;
+ } else {
+ assert(0 && "Unknown regclass!");
+ abort();
+ }
+
+ addFrameReference(BuildMI(MBB, MI, get(opc))
+ .addReg(SrcReg, false, false, isKill), FrameIdx);
+}
+
+void SPUInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
+ bool isKill,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const {
+ cerr << "storeRegToAddr() invoked!\n";
+ abort();
+
+ if (Addr[0].isFrameIndex()) {
+ /* do what storeRegToStackSlot does here */
+ } else {
+ unsigned Opc = 0;
+ if (RC == SPU::GPRCRegisterClass) {
+ /* Opc = PPC::STW; */
+ } else if (RC == SPU::R16CRegisterClass) {
+ /* Opc = PPC::STD; */
+ } else if (RC == SPU::R32CRegisterClass) {
+ /* Opc = PPC::STFD; */
+ } else if (RC == SPU::R32FPRegisterClass) {
+ /* Opc = PPC::STFD; */
+ } else if (RC == SPU::R64FPRegisterClass) {
+ /* Opc = PPC::STFS; */
+ } else if (RC == SPU::VECREGRegisterClass) {
+ /* Opc = PPC::STVX; */
+ } else {
+ assert(0 && "Unknown regclass!");
+ abort();
+ }
+ MachineInstrBuilder MIB = BuildMI(get(Opc))
+ .addReg(SrcReg, false, false, isKill);
+ for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
+ MachineOperand &MO = Addr[i];
+ if (MO.isRegister())
+ MIB.addReg(MO.getReg());
+ else if (MO.isImmediate())
+ MIB.addImm(MO.getImm());
+ else
+ MIB.addFrameIndex(MO.getIndex());
+ }
+ NewMIs.push_back(MIB);
+ }
+}
+
+void
+SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned DestReg, int FrameIdx,
+ const TargetRegisterClass *RC) const
+{
+ MachineOpCode opc;
+ if (RC == SPU::GPRCRegisterClass) {
+ opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
+ ? SPU::LQDr128
+ : SPU::LQXr128;
+ } else if (RC == SPU::R64CRegisterClass) {
+ opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
+ ? SPU::LQDr64
+ : SPU::LQXr64;
+ } else if (RC == SPU::R64FPRegisterClass) {
+ opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
+ ? SPU::LQDr64
+ : SPU::LQXr64;
+ } else if (RC == SPU::R32CRegisterClass) {
+ opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
+ ? SPU::LQDr32
+ : SPU::LQXr32;
+ } else if (RC == SPU::R32FPRegisterClass) {
+ opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
+ ? SPU::LQDr32
+ : SPU::LQXr32;
+ } else if (RC == SPU::R16CRegisterClass) {
+ opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
+ ? SPU::LQDr16
+ : SPU::LQXr16;
+ } else {
+ assert(0 && "Unknown regclass in loadRegFromStackSlot!");
+ abort();
+ }
+
+ addFrameReference(BuildMI(MBB, MI, get(opc)).addReg(DestReg), FrameIdx);
+}
+
+/*!
+ \note We are really pessimistic here about what kind of a load we're doing.
+ */
+void SPUInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs)
+ const {
+ cerr << "loadRegToAddr() invoked!\n";
+ abort();
+
+ if (Addr[0].isFrameIndex()) {
+ /* do what loadRegFromStackSlot does here... */
+ } else {
+ unsigned Opc = 0;
+ if (RC == SPU::R8CRegisterClass) {
+ /* do brilliance here */
+ } else if (RC == SPU::R16CRegisterClass) {
+ /* Opc = PPC::LWZ; */
+ } else if (RC == SPU::R32CRegisterClass) {
+ /* Opc = PPC::LD; */
+ } else if (RC == SPU::R32FPRegisterClass) {
+ /* Opc = PPC::LFD; */
+ } else if (RC == SPU::R64FPRegisterClass) {
+ /* Opc = PPC::LFS; */
+ } else if (RC == SPU::VECREGRegisterClass) {
+ /* Opc = PPC::LVX; */
+ } else if (RC == SPU::GPRCRegisterClass) {
+ /* Opc = something else! */
+ } else {
+ assert(0 && "Unknown regclass!");
+ abort();
+ }
+ MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
+ for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
+ MachineOperand &MO = Addr[i];
+ if (MO.isRegister())
+ MIB.addReg(MO.getReg());
+ else if (MO.isImmediate())
+ MIB.addImm(MO.getImm());
+ else
+ MIB.addFrameIndex(MO.getIndex());
+ }
+ NewMIs.push_back(MIB);
+ }
+}
+
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const;
+
+ //! Store a register to a stack slot, based on its register class.
+ virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ unsigned SrcReg, bool isKill, int FrameIndex,
+ const TargetRegisterClass *RC) const;
+
+ //! Store a register to an address, based on its register class
+ virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const;
+
+ //! Load a register from a stack slot, based on its register class.
+ virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ unsigned DestReg, int FrameIndex,
+ const TargetRegisterClass *RC) const;
+
+ //! Loqad a register from an address, based on its register class
+ virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const;
};
}
{
}
-void
-SPURegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned SrcReg, bool isKill, int FrameIdx,
- const TargetRegisterClass *RC) const
-{
- MachineOpCode opc;
- if (RC == SPU::GPRCRegisterClass) {
- opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
- ? SPU::STQDr128
- : SPU::STQXr128;
- } else if (RC == SPU::R64CRegisterClass) {
- opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
- ? SPU::STQDr64
- : SPU::STQXr64;
- } else if (RC == SPU::R64FPRegisterClass) {
- opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
- ? SPU::STQDr64
- : SPU::STQXr64;
- } else if (RC == SPU::R32CRegisterClass) {
- opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
- ? SPU::STQDr32
- : SPU::STQXr32;
- } else if (RC == SPU::R32FPRegisterClass) {
- opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
- ? SPU::STQDr32
- : SPU::STQXr32;
- } else if (RC == SPU::R16CRegisterClass) {
- opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) ?
- SPU::STQDr16
- : SPU::STQXr16;
- } else {
- assert(0 && "Unknown regclass!");
- abort();
- }
-
- addFrameReference(BuildMI(MBB, MI, TII.get(opc))
- .addReg(SrcReg, false, false, isKill), FrameIdx);
-}
-
-void SPURegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
- bool isKill,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const {
- cerr << "storeRegToAddr() invoked!\n";
- abort();
-
- if (Addr[0].isFrameIndex()) {
- /* do what storeRegToStackSlot does here */
- } else {
- unsigned Opc = 0;
- if (RC == SPU::GPRCRegisterClass) {
- /* Opc = PPC::STW; */
- } else if (RC == SPU::R16CRegisterClass) {
- /* Opc = PPC::STD; */
- } else if (RC == SPU::R32CRegisterClass) {
- /* Opc = PPC::STFD; */
- } else if (RC == SPU::R32FPRegisterClass) {
- /* Opc = PPC::STFD; */
- } else if (RC == SPU::R64FPRegisterClass) {
- /* Opc = PPC::STFS; */
- } else if (RC == SPU::VECREGRegisterClass) {
- /* Opc = PPC::STVX; */
- } else {
- assert(0 && "Unknown regclass!");
- abort();
- }
- MachineInstrBuilder MIB = BuildMI(TII.get(Opc))
- .addReg(SrcReg, false, false, isKill);
- for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
- MachineOperand &MO = Addr[i];
- if (MO.isRegister())
- MIB.addReg(MO.getReg());
- else if (MO.isImmediate())
- MIB.addImm(MO.getImm());
- else
- MIB.addFrameIndex(MO.getIndex());
- }
- NewMIs.push_back(MIB);
- }
-}
-
-void
-SPURegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned DestReg, int FrameIdx,
- const TargetRegisterClass *RC) const
-{
- MachineOpCode opc;
- if (RC == SPU::GPRCRegisterClass) {
- opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
- ? SPU::LQDr128
- : SPU::LQXr128;
- } else if (RC == SPU::R64CRegisterClass) {
- opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
- ? SPU::LQDr64
- : SPU::LQXr64;
- } else if (RC == SPU::R64FPRegisterClass) {
- opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
- ? SPU::LQDr64
- : SPU::LQXr64;
- } else if (RC == SPU::R32CRegisterClass) {
- opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
- ? SPU::LQDr32
- : SPU::LQXr32;
- } else if (RC == SPU::R32FPRegisterClass) {
- opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
- ? SPU::LQDr32
- : SPU::LQXr32;
- } else if (RC == SPU::R16CRegisterClass) {
- opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
- ? SPU::LQDr16
- : SPU::LQXr16;
- } else {
- assert(0 && "Unknown regclass in loadRegFromStackSlot!");
- abort();
- }
-
- addFrameReference(BuildMI(MBB, MI, TII.get(opc)).addReg(DestReg), FrameIdx);
-}
-
-/*!
- \note We are really pessimistic here about what kind of a load we're doing.
- */
-void SPURegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs)
- const {
- cerr << "loadRegToAddr() invoked!\n";
- abort();
-
- if (Addr[0].isFrameIndex()) {
- /* do what loadRegFromStackSlot does here... */
- } else {
- unsigned Opc = 0;
- if (RC == SPU::R8CRegisterClass) {
- /* do brilliance here */
- } else if (RC == SPU::R16CRegisterClass) {
- /* Opc = PPC::LWZ; */
- } else if (RC == SPU::R32CRegisterClass) {
- /* Opc = PPC::LD; */
- } else if (RC == SPU::R32FPRegisterClass) {
- /* Opc = PPC::LFD; */
- } else if (RC == SPU::R64FPRegisterClass) {
- /* Opc = PPC::LFS; */
- } else if (RC == SPU::VECREGRegisterClass) {
- /* Opc = PPC::LVX; */
- } else if (RC == SPU::GPRCRegisterClass) {
- /* Opc = something else! */
- } else {
- assert(0 && "Unknown regclass!");
- abort();
- }
- MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
- for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
- MachineOperand &MO = Addr[i];
- if (MO.isRegister())
- MIB.addReg(MO.getReg());
- else if (MO.isImmediate())
- MIB.addImm(MO.getImm());
- else
- MIB.addFrameIndex(MO.getIndex());
- }
- NewMIs.push_back(MIB);
- }
-}
-
void SPURegisterInfo::reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg,
*/
static unsigned getRegisterNumbering(unsigned RegEnum);
- //! Store a register to a stack slot, based on its register class.
- void storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- unsigned SrcReg, bool isKill, int FrameIndex,
- const TargetRegisterClass *RC) const;
-
- //! Store a register to an address, based on its register class
- void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const;
-
- //! Load a register from a stack slot, based on its register class.
- void loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- unsigned DestReg, int FrameIndex,
- const TargetRegisterClass *RC) const;
-
- //! Loqad a register from an address, based on its register class
- virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const;
-
- //! Copy a register to another
- void copyRegToReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned DestReg, unsigned SrcReg,
- const TargetRegisterClass *DestRC,
- const TargetRegisterClass *SrcRC) const;
-
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
unsigned DestReg, const MachineInstr *Orig) const;
else // otherwise, MOV works (for both gen. regs and FP regs)
BuildMI(MBB, MI, get(IA64::MOV), DestReg).addReg(SrcReg);
}
+
+void IA64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned SrcReg, bool isKill,
+ int FrameIdx,
+ const TargetRegisterClass *RC) const{
+
+ if (RC == IA64::FPRegisterClass) {
+ BuildMI(MBB, MI, get(IA64::STF_SPILL)).addFrameIndex(FrameIdx)
+ .addReg(SrcReg, false, false, isKill);
+ } else if (RC == IA64::GRRegisterClass) {
+ BuildMI(MBB, MI, get(IA64::ST8)).addFrameIndex(FrameIdx)
+ .addReg(SrcReg, false, false, isKill);
+ } else if (RC == IA64::PRRegisterClass) {
+ /* we use IA64::r2 as a temporary register for doing this hackery. */
+ // first we load 0:
+ BuildMI(MBB, MI, get(IA64::MOV), IA64::r2).addReg(IA64::r0);
+ // then conditionally add 1:
+ BuildMI(MBB, MI, get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2)
+ .addImm(1).addReg(SrcReg, false, false, isKill);
+ // and then store it to the stack
+ BuildMI(MBB, MI, get(IA64::ST8)).addFrameIndex(FrameIdx).addReg(IA64::r2);
+ } else assert(0 &&
+ "sorry, I don't know how to store this sort of reg in the stack\n");
+}
+
+void IA64InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
+ bool isKill,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const {
+ unsigned Opc = 0;
+ if (RC == IA64::FPRegisterClass) {
+ Opc = IA64::STF8;
+ } else if (RC == IA64::GRRegisterClass) {
+ Opc = IA64::ST8;
+ } else if (RC == IA64::PRRegisterClass) {
+ Opc = IA64::ST1;
+ } else {
+ assert(0 &&
+ "sorry, I don't know how to store this sort of reg\n");
+ }
+
+ MachineInstrBuilder MIB = BuildMI(get(Opc));
+ for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
+ MachineOperand &MO = Addr[i];
+ if (MO.isRegister())
+ MIB.addReg(MO.getReg());
+ else if (MO.isImmediate())
+ MIB.addImm(MO.getImm());
+ else
+ MIB.addFrameIndex(MO.getIndex());
+ }
+ MIB.addReg(SrcReg, false, false, isKill);
+ NewMIs.push_back(MIB);
+ return;
+
+}
+
+void IA64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned DestReg, int FrameIdx,
+ const TargetRegisterClass *RC)const{
+
+ if (RC == IA64::FPRegisterClass) {
+ BuildMI(MBB, MI, get(IA64::LDF_FILL), DestReg).addFrameIndex(FrameIdx);
+ } else if (RC == IA64::GRRegisterClass) {
+ BuildMI(MBB, MI, get(IA64::LD8), DestReg).addFrameIndex(FrameIdx);
+ } else if (RC == IA64::PRRegisterClass) {
+ // first we load a byte from the stack into r2, our 'predicate hackery'
+ // scratch reg
+ BuildMI(MBB, MI, get(IA64::LD8), IA64::r2).addFrameIndex(FrameIdx);
+ // then we compare it to zero. If it _is_ zero, compare-not-equal to
+ // r0 gives us 0, which is what we want, so that's nice.
+ BuildMI(MBB, MI, get(IA64::CMPNE), DestReg).addReg(IA64::r2).addReg(IA64::r0);
+ } else assert(0 &&
+ "sorry, I don't know how to load this sort of reg from the stack\n");
+}
+
+void IA64InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const {
+ unsigned Opc = 0;
+ if (RC == IA64::FPRegisterClass) {
+ Opc = IA64::LDF8;
+ } else if (RC == IA64::GRRegisterClass) {
+ Opc = IA64::LD8;
+ } else if (RC == IA64::PRRegisterClass) {
+ Opc = IA64::LD1;
+ } else {
+ assert(0 &&
+ "sorry, I don't know how to store this sort of reg\n");
+ }
+
+ MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
+ for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
+ MachineOperand &MO = Addr[i];
+ if (MO.isRegister())
+ MIB.addReg(MO.getReg());
+ else if (MO.isImmediate())
+ MIB.addImm(MO.getImm());
+ else
+ MIB.addFrameIndex(MO.getIndex());
+ }
+ NewMIs.push_back(MIB);
+ return;
+}
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const;
+ virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned SrcReg, bool isKill, int FrameIndex,
+ const TargetRegisterClass *RC) const;
+
+ virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const;
+
+ virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned DestReg, int FrameIndex,
+ const TargetRegisterClass *RC) const;
+
+ virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const;
};
} // End llvm namespace
: IA64GenRegisterInfo(IA64::ADJUSTCALLSTACKDOWN, IA64::ADJUSTCALLSTACKUP),
TII(tii) {}
-void IA64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned SrcReg, bool isKill,
- int FrameIdx,
- const TargetRegisterClass *RC) const{
-
- if (RC == IA64::FPRegisterClass) {
- BuildMI(MBB, MI, TII.get(IA64::STF_SPILL)).addFrameIndex(FrameIdx)
- .addReg(SrcReg, false, false, isKill);
- } else if (RC == IA64::GRRegisterClass) {
- BuildMI(MBB, MI, TII.get(IA64::ST8)).addFrameIndex(FrameIdx)
- .addReg(SrcReg, false, false, isKill);
- } else if (RC == IA64::PRRegisterClass) {
- /* we use IA64::r2 as a temporary register for doing this hackery. */
- // first we load 0:
- BuildMI(MBB, MI, TII.get(IA64::MOV), IA64::r2).addReg(IA64::r0);
- // then conditionally add 1:
- BuildMI(MBB, MI, TII.get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2)
- .addImm(1).addReg(SrcReg, false, false, isKill);
- // and then store it to the stack
- BuildMI(MBB, MI, TII.get(IA64::ST8)).addFrameIndex(FrameIdx).addReg(IA64::r2);
- } else assert(0 &&
- "sorry, I don't know how to store this sort of reg in the stack\n");
-}
-
-void IA64RegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
- bool isKill,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const {
- unsigned Opc = 0;
- if (RC == IA64::FPRegisterClass) {
- Opc = IA64::STF8;
- } else if (RC == IA64::GRRegisterClass) {
- Opc = IA64::ST8;
- } else if (RC == IA64::PRRegisterClass) {
- Opc = IA64::ST1;
- } else {
- assert(0 &&
- "sorry, I don't know how to store this sort of reg\n");
- }
-
- MachineInstrBuilder MIB = BuildMI(TII.get(Opc));
- for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
- MachineOperand &MO = Addr[i];
- if (MO.isRegister())
- MIB.addReg(MO.getReg());
- else if (MO.isImmediate())
- MIB.addImm(MO.getImm());
- else
- MIB.addFrameIndex(MO.getIndex());
- }
- MIB.addReg(SrcReg, false, false, isKill);
- NewMIs.push_back(MIB);
- return;
-
-}
-
-void IA64RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned DestReg, int FrameIdx,
- const TargetRegisterClass *RC)const{
-
- if (RC == IA64::FPRegisterClass) {
- BuildMI(MBB, MI, TII.get(IA64::LDF_FILL), DestReg).addFrameIndex(FrameIdx);
- } else if (RC == IA64::GRRegisterClass) {
- BuildMI(MBB, MI, TII.get(IA64::LD8), DestReg).addFrameIndex(FrameIdx);
- } else if (RC == IA64::PRRegisterClass) {
- // first we load a byte from the stack into r2, our 'predicate hackery'
- // scratch reg
- BuildMI(MBB, MI, TII.get(IA64::LD8), IA64::r2).addFrameIndex(FrameIdx);
- // then we compare it to zero. If it _is_ zero, compare-not-equal to
- // r0 gives us 0, which is what we want, so that's nice.
- BuildMI(MBB, MI, TII.get(IA64::CMPNE), DestReg).addReg(IA64::r2).addReg(IA64::r0);
- } else assert(0 &&
- "sorry, I don't know how to load this sort of reg from the stack\n");
-}
-
-void IA64RegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const {
- unsigned Opc = 0;
- if (RC == IA64::FPRegisterClass) {
- Opc = IA64::LDF8;
- } else if (RC == IA64::GRRegisterClass) {
- Opc = IA64::LD8;
- } else if (RC == IA64::PRRegisterClass) {
- Opc = IA64::LD1;
- } else {
- assert(0 &&
- "sorry, I don't know how to store this sort of reg\n");
- }
-
- MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
- for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
- MachineOperand &MO = Addr[i];
- if (MO.isRegister())
- MIB.addReg(MO.getReg());
- else if (MO.isImmediate())
- MIB.addImm(MO.getImm());
- else
- MIB.addFrameIndex(MO.getIndex());
- }
- NewMIs.push_back(MIB);
- return;
-}
-
void IA64RegisterInfo::reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg,
IA64RegisterInfo(const TargetInstrInfo &tii);
/// Code Generation virtual methods...
- void storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned SrcReg, bool isKill, int FrameIndex,
- const TargetRegisterClass *RC) const;
-
- void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const;
-
- void loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned DestReg, int FrameIndex,
- const TargetRegisterClass *RC) const;
-
- void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const;
-
void copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
assert (0 && "Can't copy this register");
}
+void MipsInstrInfo::
+storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+ unsigned SrcReg, bool isKill, int FI,
+ const TargetRegisterClass *RC) const
+{
+ if (RC == Mips::CPURegsRegisterClass)
+ BuildMI(MBB, I, get(Mips::SW)).addReg(SrcReg, false, false, isKill)
+ .addImm(0).addFrameIndex(FI);
+ else
+ assert(0 && "Can't store this register to stack slot");
+}
+
+void MipsInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
+ bool isKill,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const {
+ if (RC != Mips::CPURegsRegisterClass)
+ assert(0 && "Can't store this register");
+ MachineInstrBuilder MIB = BuildMI(get(Mips::SW))
+ .addReg(SrcReg, false, false, isKill);
+ for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
+ MachineOperand &MO = Addr[i];
+ if (MO.isRegister())
+ MIB.addReg(MO.getReg());
+ else if (MO.isImmediate())
+ MIB.addImm(MO.getImm());
+ else
+ MIB.addFrameIndex(MO.getIndex());
+ }
+ NewMIs.push_back(MIB);
+ return;
+}
+
+void MipsInstrInfo::
+loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+ unsigned DestReg, int FI,
+ const TargetRegisterClass *RC) const
+{
+ if (RC == Mips::CPURegsRegisterClass)
+ BuildMI(MBB, I, get(Mips::LW), DestReg).addImm(0).addFrameIndex(FI);
+ else
+ assert(0 && "Can't load this register from stack slot");
+}
+
+void MipsInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const {
+ if (RC != Mips::CPURegsRegisterClass)
+ assert(0 && "Can't load this register");
+ MachineInstrBuilder MIB = BuildMI(get(Mips::LW), DestReg);
+ for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
+ MachineOperand &MO = Addr[i];
+ if (MO.isRegister())
+ MIB.addReg(MO.getReg());
+ else if (MO.isImmediate())
+ MIB.addImm(MO.getImm());
+ else
+ MIB.addFrameIndex(MO.getIndex());
+ }
+ NewMIs.push_back(MIB);
+ return;
+}
+
unsigned MipsInstrInfo::
RemoveBranch(MachineBasicBlock &MBB) const
{
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const;
+ virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ unsigned SrcReg, bool isKill, int FrameIndex,
+ const TargetRegisterClass *RC) const;
+
+ virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const;
+
+ virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ unsigned DestReg, int FrameIndex,
+ const TargetRegisterClass *RC) const;
+
+ virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const;
virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
}
}
-void MipsRegisterInfo::
-storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
- unsigned SrcReg, bool isKill, int FI,
- const TargetRegisterClass *RC) const
-{
- if (RC == Mips::CPURegsRegisterClass)
- BuildMI(MBB, I, TII.get(Mips::SW)).addReg(SrcReg, false, false, isKill)
- .addImm(0).addFrameIndex(FI);
- else
- assert(0 && "Can't store this register to stack slot");
-}
-
-void MipsRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
- bool isKill,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const {
- if (RC != Mips::CPURegsRegisterClass)
- assert(0 && "Can't store this register");
- MachineInstrBuilder MIB = BuildMI(TII.get(Mips::SW))
- .addReg(SrcReg, false, false, isKill);
- for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
- MachineOperand &MO = Addr[i];
- if (MO.isRegister())
- MIB.addReg(MO.getReg());
- else if (MO.isImmediate())
- MIB.addImm(MO.getImm());
- else
- MIB.addFrameIndex(MO.getIndex());
- }
- NewMIs.push_back(MIB);
- return;
-}
-
-void MipsRegisterInfo::
-loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
- unsigned DestReg, int FI,
- const TargetRegisterClass *RC) const
-{
- if (RC == Mips::CPURegsRegisterClass)
- BuildMI(MBB, I, TII.get(Mips::LW), DestReg).addImm(0).addFrameIndex(FI);
- else
- assert(0 && "Can't load this register from stack slot");
-}
-
-void MipsRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const {
- if (RC != Mips::CPURegsRegisterClass)
- assert(0 && "Can't load this register");
- MachineInstrBuilder MIB = BuildMI(TII.get(Mips::LW), DestReg);
- for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
- MachineOperand &MO = Addr[i];
- if (MO.isRegister())
- MIB.addReg(MO.getReg());
- else if (MO.isImmediate())
- MIB.addImm(MO.getImm());
- else
- MIB.addFrameIndex(MO.getIndex());
- }
- NewMIs.push_back(MIB);
- return;
-}
-
void MipsRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg,
static unsigned getRegisterNumbering(unsigned RegEnum);
/// Code Generation virtual methods...
- void storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- unsigned SrcReg, bool isKill, int FrameIndex,
- const TargetRegisterClass *RC) const;
-
- void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const;
-
- void loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- unsigned DestReg, int FrameIndex,
- const TargetRegisterClass *RC) const;
-
- void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const;
-
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
unsigned DestReg, const MachineInstr *Orig) const;
return 0;
}
- void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- unsigned DestReg, unsigned SrcReg,
- const TargetRegisterClass *DestRC,
- const TargetRegisterClass *SrcRC) const;
-
-
const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
const TargetRegisterClass* const*
//===----------------------------------------------------------------------===//
#include "PPCInstrInfo.h"
+#include "PPCInstrBuilder.h"
#include "PPCPredicates.h"
#include "PPCGenInstrInfo.inc"
#include "PPCTargetMachine.h"
}
}
+static void StoreRegToStackSlot(const TargetInstrInfo &TII,
+ unsigned SrcReg, bool isKill, int FrameIdx,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) {
+ if (RC == PPC::GPRCRegisterClass) {
+ if (SrcReg != PPC::LR) {
+ NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
+ .addReg(SrcReg, false, false, isKill), FrameIdx));
+ } else {
+ // FIXME: this spills LR immediately to memory in one step. To do this,
+ // we use R11, which we know cannot be used in the prolog/epilog. This is
+ // a hack.
+ NewMIs.push_back(BuildMI(TII.get(PPC::MFLR), PPC::R11));
+ NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
+ .addReg(PPC::R11, false, false, isKill), FrameIdx));
+ }
+ } else if (RC == PPC::G8RCRegisterClass) {
+ if (SrcReg != PPC::LR8) {
+ NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STD))
+ .addReg(SrcReg, false, false, isKill), FrameIdx));
+ } else {
+ // FIXME: this spills LR immediately to memory in one step. To do this,
+ // we use R11, which we know cannot be used in the prolog/epilog. This is
+ // a hack.
+ NewMIs.push_back(BuildMI(TII.get(PPC::MFLR8), PPC::X11));
+ NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STD))
+ .addReg(PPC::X11, false, false, isKill), FrameIdx));
+ }
+ } else if (RC == PPC::F8RCRegisterClass) {
+ NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFD))
+ .addReg(SrcReg, false, false, isKill), FrameIdx));
+ } else if (RC == PPC::F4RCRegisterClass) {
+ NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFS))
+ .addReg(SrcReg, false, false, isKill), FrameIdx));
+ } else if (RC == PPC::CRRCRegisterClass) {
+ // FIXME: We use R0 here, because it isn't available for RA.
+ // We need to store the CR in the low 4-bits of the saved value. First,
+ // issue a MFCR to save all of the CRBits.
+ NewMIs.push_back(BuildMI(TII.get(PPC::MFCR), PPC::R0));
+
+ // If the saved register wasn't CR0, shift the bits left so that they are in
+ // CR0's slot.
+ if (SrcReg != PPC::CR0) {
+ unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
+ // rlwinm r0, r0, ShiftBits, 0, 31.
+ NewMIs.push_back(BuildMI(TII.get(PPC::RLWINM), PPC::R0)
+ .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31));
+ }
+
+ NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
+ .addReg(PPC::R0, false, false, isKill), FrameIdx));
+ } else if (RC == PPC::VRRCRegisterClass) {
+ // We don't have indexed addressing for vector loads. Emit:
+ // R0 = ADDI FI#
+ // STVX VAL, 0, R0
+ //
+ // FIXME: We use R0 here, because it isn't available for RA.
+ NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::ADDI), PPC::R0),
+ FrameIdx, 0, 0));
+ NewMIs.push_back(BuildMI(TII.get(PPC::STVX))
+ .addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0));
+ } else {
+ assert(0 && "Unknown regclass!");
+ abort();
+ }
+}
+
+void
+PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned SrcReg, bool isKill, int FrameIdx,
+ const TargetRegisterClass *RC) const {
+ SmallVector<MachineInstr*, 4> NewMIs;
+ StoreRegToStackSlot(*this, SrcReg, isKill, FrameIdx, RC, NewMIs);
+ for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
+ MBB.insert(MI, NewMIs[i]);
+}
+
+void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
+ bool isKill,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const {
+ if (Addr[0].isFrameIndex()) {
+ StoreRegToStackSlot(*this, SrcReg, isKill, Addr[0].getIndex(), RC, NewMIs);
+ return;
+ }
+
+ unsigned Opc = 0;
+ if (RC == PPC::GPRCRegisterClass) {
+ Opc = PPC::STW;
+ } else if (RC == PPC::G8RCRegisterClass) {
+ Opc = PPC::STD;
+ } else if (RC == PPC::F8RCRegisterClass) {
+ Opc = PPC::STFD;
+ } else if (RC == PPC::F4RCRegisterClass) {
+ Opc = PPC::STFS;
+ } else if (RC == PPC::VRRCRegisterClass) {
+ Opc = PPC::STVX;
+ } else {
+ assert(0 && "Unknown regclass!");
+ abort();
+ }
+ MachineInstrBuilder MIB = BuildMI(get(Opc))
+ .addReg(SrcReg, false, false, isKill);
+ for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
+ MachineOperand &MO = Addr[i];
+ if (MO.isRegister())
+ MIB.addReg(MO.getReg());
+ else if (MO.isImmediate())
+ MIB.addImm(MO.getImm());
+ else
+ MIB.addFrameIndex(MO.getIndex());
+ }
+ NewMIs.push_back(MIB);
+ return;
+}
+
+static void LoadRegFromStackSlot(const TargetInstrInfo &TII,
+ unsigned DestReg, int FrameIdx,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) {
+ if (RC == PPC::GPRCRegisterClass) {
+ if (DestReg != PPC::LR) {
+ NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), DestReg),
+ FrameIdx));
+ } else {
+ NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), PPC::R11),
+ FrameIdx));
+ NewMIs.push_back(BuildMI(TII.get(PPC::MTLR)).addReg(PPC::R11));
+ }
+ } else if (RC == PPC::G8RCRegisterClass) {
+ if (DestReg != PPC::LR8) {
+ NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LD), DestReg),
+ FrameIdx));
+ } else {
+ NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LD), PPC::R11),
+ FrameIdx));
+ NewMIs.push_back(BuildMI(TII.get(PPC::MTLR8)).addReg(PPC::R11));
+ }
+ } else if (RC == PPC::F8RCRegisterClass) {
+ NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LFD), DestReg),
+ FrameIdx));
+ } else if (RC == PPC::F4RCRegisterClass) {
+ NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LFS), DestReg),
+ FrameIdx));
+ } else if (RC == PPC::CRRCRegisterClass) {
+ // FIXME: We use R0 here, because it isn't available for RA.
+ NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), PPC::R0),
+ FrameIdx));
+
+ // If the reloaded register isn't CR0, shift the bits right so that they are
+ // in the right CR's slot.
+ if (DestReg != PPC::CR0) {
+ unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
+ // rlwinm r11, r11, 32-ShiftBits, 0, 31.
+ NewMIs.push_back(BuildMI(TII.get(PPC::RLWINM), PPC::R0)
+ .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31));
+ }
+
+ NewMIs.push_back(BuildMI(TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0));
+ } else if (RC == PPC::VRRCRegisterClass) {
+ // We don't have indexed addressing for vector loads. Emit:
+ // R0 = ADDI FI#
+ // Dest = LVX 0, R0
+ //
+ // FIXME: We use R0 here, because it isn't available for RA.
+ NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::ADDI), PPC::R0),
+ FrameIdx, 0, 0));
+ NewMIs.push_back(BuildMI(TII.get(PPC::LVX),DestReg).addReg(PPC::R0)
+ .addReg(PPC::R0));
+ } else {
+ assert(0 && "Unknown regclass!");
+ abort();
+ }
+}
+
+void
+PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned DestReg, int FrameIdx,
+ const TargetRegisterClass *RC) const {
+ SmallVector<MachineInstr*, 4> NewMIs;
+ LoadRegFromStackSlot(*this, DestReg, FrameIdx, RC, NewMIs);
+ for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
+ MBB.insert(MI, NewMIs[i]);
+}
+
+void PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const{
+ if (Addr[0].isFrameIndex()) {
+ LoadRegFromStackSlot(*this, DestReg, Addr[0].getIndex(), RC, NewMIs);
+ return;
+ }
+
+ unsigned Opc = 0;
+ if (RC == PPC::GPRCRegisterClass) {
+ assert(DestReg != PPC::LR && "Can't handle this yet!");
+ Opc = PPC::LWZ;
+ } else if (RC == PPC::G8RCRegisterClass) {
+ assert(DestReg != PPC::LR8 && "Can't handle this yet!");
+ Opc = PPC::LD;
+ } else if (RC == PPC::F8RCRegisterClass) {
+ Opc = PPC::LFD;
+ } else if (RC == PPC::F4RCRegisterClass) {
+ Opc = PPC::LFS;
+ } else if (RC == PPC::VRRCRegisterClass) {
+ Opc = PPC::LVX;
+ } else {
+ assert(0 && "Unknown regclass!");
+ abort();
+ }
+ MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
+ for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
+ MachineOperand &MO = Addr[i];
+ if (MO.isRegister())
+ MIB.addReg(MO.getReg());
+ else if (MO.isImmediate())
+ MIB.addImm(MO.getImm());
+ else
+ MIB.addFrameIndex(MO.getIndex());
+ }
+ NewMIs.push_back(MIB);
+ return;
+}
+
+
bool PPCInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
if (MBB.empty()) return false;
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const std::vector<MachineOperand> &Cond) const;
- void copyRegToReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned DestReg, unsigned SrcReg,
- const TargetRegisterClass *DestRC,
- const TargetRegisterClass *SrcRC) const;
+ virtual void copyRegToReg(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned DestReg, unsigned SrcReg,
+ const TargetRegisterClass *DestRC,
+ const TargetRegisterClass *SrcRC) const;
+
+ virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ unsigned SrcReg, bool isKill, int FrameIndex,
+ const TargetRegisterClass *RC) const;
+
+ virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const;
+
+ virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ unsigned DestReg, int FrameIndex,
+ const TargetRegisterClass *RC) const;
+
+ virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const;
+
virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
};
ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
}
-static void StoreRegToStackSlot(const TargetInstrInfo &TII,
- unsigned SrcReg, bool isKill, int FrameIdx,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) {
- if (RC == PPC::GPRCRegisterClass) {
- if (SrcReg != PPC::LR) {
- NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
- .addReg(SrcReg, false, false, isKill), FrameIdx));
- } else {
- // FIXME: this spills LR immediately to memory in one step. To do this,
- // we use R11, which we know cannot be used in the prolog/epilog. This is
- // a hack.
- NewMIs.push_back(BuildMI(TII.get(PPC::MFLR), PPC::R11));
- NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
- .addReg(PPC::R11, false, false, isKill), FrameIdx));
- }
- } else if (RC == PPC::G8RCRegisterClass) {
- if (SrcReg != PPC::LR8) {
- NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STD))
- .addReg(SrcReg, false, false, isKill), FrameIdx));
- } else {
- // FIXME: this spills LR immediately to memory in one step. To do this,
- // we use R11, which we know cannot be used in the prolog/epilog. This is
- // a hack.
- NewMIs.push_back(BuildMI(TII.get(PPC::MFLR8), PPC::X11));
- NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STD))
- .addReg(PPC::X11, false, false, isKill), FrameIdx));
- }
- } else if (RC == PPC::F8RCRegisterClass) {
- NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFD))
- .addReg(SrcReg, false, false, isKill), FrameIdx));
- } else if (RC == PPC::F4RCRegisterClass) {
- NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFS))
- .addReg(SrcReg, false, false, isKill), FrameIdx));
- } else if (RC == PPC::CRRCRegisterClass) {
- // FIXME: We use R0 here, because it isn't available for RA.
- // We need to store the CR in the low 4-bits of the saved value. First,
- // issue a MFCR to save all of the CRBits.
- NewMIs.push_back(BuildMI(TII.get(PPC::MFCR), PPC::R0));
-
- // If the saved register wasn't CR0, shift the bits left so that they are in
- // CR0's slot.
- if (SrcReg != PPC::CR0) {
- unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
- // rlwinm r0, r0, ShiftBits, 0, 31.
- NewMIs.push_back(BuildMI(TII.get(PPC::RLWINM), PPC::R0)
- .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31));
- }
-
- NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
- .addReg(PPC::R0, false, false, isKill), FrameIdx));
- } else if (RC == PPC::VRRCRegisterClass) {
- // We don't have indexed addressing for vector loads. Emit:
- // R0 = ADDI FI#
- // STVX VAL, 0, R0
- //
- // FIXME: We use R0 here, because it isn't available for RA.
- NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::ADDI), PPC::R0),
- FrameIdx, 0, 0));
- NewMIs.push_back(BuildMI(TII.get(PPC::STVX))
- .addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0));
- } else {
- assert(0 && "Unknown regclass!");
- abort();
- }
-}
-
-void
-PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned SrcReg, bool isKill, int FrameIdx,
- const TargetRegisterClass *RC) const {
- SmallVector<MachineInstr*, 4> NewMIs;
- StoreRegToStackSlot(TII, SrcReg, isKill, FrameIdx, RC, NewMIs);
- for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
- MBB.insert(MI, NewMIs[i]);
-}
-
-void PPCRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
- bool isKill,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const {
- if (Addr[0].isFrameIndex()) {
- StoreRegToStackSlot(TII, SrcReg, isKill, Addr[0].getIndex(), RC, NewMIs);
- return;
- }
-
- unsigned Opc = 0;
- if (RC == PPC::GPRCRegisterClass) {
- Opc = PPC::STW;
- } else if (RC == PPC::G8RCRegisterClass) {
- Opc = PPC::STD;
- } else if (RC == PPC::F8RCRegisterClass) {
- Opc = PPC::STFD;
- } else if (RC == PPC::F4RCRegisterClass) {
- Opc = PPC::STFS;
- } else if (RC == PPC::VRRCRegisterClass) {
- Opc = PPC::STVX;
- } else {
- assert(0 && "Unknown regclass!");
- abort();
- }
- MachineInstrBuilder MIB = BuildMI(TII.get(Opc))
- .addReg(SrcReg, false, false, isKill);
- for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
- MachineOperand &MO = Addr[i];
- if (MO.isRegister())
- MIB.addReg(MO.getReg());
- else if (MO.isImmediate())
- MIB.addImm(MO.getImm());
- else
- MIB.addFrameIndex(MO.getIndex());
- }
- NewMIs.push_back(MIB);
- return;
-}
-
-static void LoadRegFromStackSlot(const TargetInstrInfo &TII,
- unsigned DestReg, int FrameIdx,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) {
- if (RC == PPC::GPRCRegisterClass) {
- if (DestReg != PPC::LR) {
- NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), DestReg),
- FrameIdx));
- } else {
- NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), PPC::R11),
- FrameIdx));
- NewMIs.push_back(BuildMI(TII.get(PPC::MTLR)).addReg(PPC::R11));
- }
- } else if (RC == PPC::G8RCRegisterClass) {
- if (DestReg != PPC::LR8) {
- NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LD), DestReg),
- FrameIdx));
- } else {
- NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LD), PPC::R11),
- FrameIdx));
- NewMIs.push_back(BuildMI(TII.get(PPC::MTLR8)).addReg(PPC::R11));
- }
- } else if (RC == PPC::F8RCRegisterClass) {
- NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LFD), DestReg),
- FrameIdx));
- } else if (RC == PPC::F4RCRegisterClass) {
- NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LFS), DestReg),
- FrameIdx));
- } else if (RC == PPC::CRRCRegisterClass) {
- // FIXME: We use R0 here, because it isn't available for RA.
- NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), PPC::R0),
- FrameIdx));
-
- // If the reloaded register isn't CR0, shift the bits right so that they are
- // in the right CR's slot.
- if (DestReg != PPC::CR0) {
- unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
- // rlwinm r11, r11, 32-ShiftBits, 0, 31.
- NewMIs.push_back(BuildMI(TII.get(PPC::RLWINM), PPC::R0)
- .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31));
- }
-
- NewMIs.push_back(BuildMI(TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0));
- } else if (RC == PPC::VRRCRegisterClass) {
- // We don't have indexed addressing for vector loads. Emit:
- // R0 = ADDI FI#
- // Dest = LVX 0, R0
- //
- // FIXME: We use R0 here, because it isn't available for RA.
- NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::ADDI), PPC::R0),
- FrameIdx, 0, 0));
- NewMIs.push_back(BuildMI(TII.get(PPC::LVX),DestReg).addReg(PPC::R0)
- .addReg(PPC::R0));
- } else {
- assert(0 && "Unknown regclass!");
- abort();
- }
-}
-
-void
-PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned DestReg, int FrameIdx,
- const TargetRegisterClass *RC) const {
- SmallVector<MachineInstr*, 4> NewMIs;
- LoadRegFromStackSlot(TII, DestReg, FrameIdx, RC, NewMIs);
- for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
- MBB.insert(MI, NewMIs[i]);
-}
-
-void PPCRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const{
- if (Addr[0].isFrameIndex()) {
- LoadRegFromStackSlot(TII, DestReg, Addr[0].getIndex(), RC, NewMIs);
- return;
- }
-
- unsigned Opc = 0;
- if (RC == PPC::GPRCRegisterClass) {
- assert(DestReg != PPC::LR && "Can't handle this yet!");
- Opc = PPC::LWZ;
- } else if (RC == PPC::G8RCRegisterClass) {
- assert(DestReg != PPC::LR8 && "Can't handle this yet!");
- Opc = PPC::LD;
- } else if (RC == PPC::F8RCRegisterClass) {
- Opc = PPC::LFD;
- } else if (RC == PPC::F4RCRegisterClass) {
- Opc = PPC::LFS;
- } else if (RC == PPC::VRRCRegisterClass) {
- Opc = PPC::LVX;
- } else {
- assert(0 && "Unknown regclass!");
- abort();
- }
- MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
- for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
- MachineOperand &MO = Addr[i];
- if (MO.isRegister())
- MIB.addReg(MO.getReg());
- else if (MO.isImmediate())
- MIB.addImm(MO.getImm());
- else
- MIB.addFrameIndex(MO.getIndex());
- }
- NewMIs.push_back(MIB);
- return;
-}
-
void PPCRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg,
static unsigned getRegisterNumbering(unsigned RegEnum);
/// Code Generation virtual methods...
- void storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- unsigned SrcReg, bool isKill, int FrameIndex,
- const TargetRegisterClass *RC) const;
-
- void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const;
-
- void loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- unsigned DestReg, int FrameIndex,
- const TargetRegisterClass *RC) const;
-
- void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const;
-
- void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- unsigned DestReg, unsigned SrcReg,
- const TargetRegisterClass *DestRC,
- const TargetRegisterClass *SrcRC) const;
-
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
unsigned DestReg, const MachineInstr *Orig) const;
else
assert (0 && "Can't copy this register");
}
+
+void SparcInstrInfo::
+storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+ unsigned SrcReg, bool isKill, int FI,
+ const TargetRegisterClass *RC) const {
+ // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
+ if (RC == SP::IntRegsRegisterClass)
+ BuildMI(MBB, I, get(SP::STri)).addFrameIndex(FI).addImm(0)
+ .addReg(SrcReg, false, false, isKill);
+ else if (RC == SP::FPRegsRegisterClass)
+ BuildMI(MBB, I, get(SP::STFri)).addFrameIndex(FI).addImm(0)
+ .addReg(SrcReg, false, false, isKill);
+ else if (RC == SP::DFPRegsRegisterClass)
+ BuildMI(MBB, I, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
+ .addReg(SrcReg, false, false, isKill);
+ else
+ assert(0 && "Can't store this register to stack slot");
+}
+
+void SparcInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
+ bool isKill,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const {
+ unsigned Opc = 0;
+ if (RC == SP::IntRegsRegisterClass)
+ Opc = SP::STri;
+ else if (RC == SP::FPRegsRegisterClass)
+ Opc = SP::STFri;
+ else if (RC == SP::DFPRegsRegisterClass)
+ Opc = SP::STDFri;
+ else
+ assert(0 && "Can't load this register");
+ MachineInstrBuilder MIB = BuildMI(get(Opc));
+ for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
+ MachineOperand &MO = Addr[i];
+ if (MO.isRegister())
+ MIB.addReg(MO.getReg());
+ else if (MO.isImmediate())
+ MIB.addImm(MO.getImm());
+ else {
+ assert(MO.isFI());
+ MIB.addFrameIndex(MO.getIndex());
+ }
+ }
+ MIB.addReg(SrcReg, false, false, isKill);
+ NewMIs.push_back(MIB);
+ return;
+}
+
+void SparcInstrInfo::
+loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+ unsigned DestReg, int FI,
+ const TargetRegisterClass *RC) const {
+ if (RC == SP::IntRegsRegisterClass)
+ BuildMI(MBB, I, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
+ else if (RC == SP::FPRegsRegisterClass)
+ BuildMI(MBB, I, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
+ else if (RC == SP::DFPRegsRegisterClass)
+ BuildMI(MBB, I, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
+ else
+ assert(0 && "Can't load this register from stack slot");
+}
+
+void SparcInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const {
+ unsigned Opc = 0;
+ if (RC == SP::IntRegsRegisterClass)
+ Opc = SP::LDri;
+ else if (RC == SP::FPRegsRegisterClass)
+ Opc = SP::LDFri;
+ else if (RC == SP::DFPRegsRegisterClass)
+ Opc = SP::LDDFri;
+ else
+ assert(0 && "Can't load this register");
+ MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
+ for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
+ MachineOperand &MO = Addr[i];
+ if (MO.isReg())
+ MIB.addReg(MO.getReg());
+ else if (MO.isImm())
+ MIB.addImm(MO.getImm());
+ else {
+ assert(MO.isFI());
+ MIB.addFrameIndex(MO.getIndex());
+ }
+ }
+ NewMIs.push_back(MIB);
+ return;
+}
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const;
+
+ virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ unsigned SrcReg, bool isKill, int FrameIndex,
+ const TargetRegisterClass *RC) const;
+
+ virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const;
+
+ virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ unsigned DestReg, int FrameIndex,
+ const TargetRegisterClass *RC) const;
+
+ virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const;
};
}
Subtarget(st), TII(tii) {
}
-void SparcRegisterInfo::
-storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
- unsigned SrcReg, bool isKill, int FI,
- const TargetRegisterClass *RC) const {
- // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
- if (RC == SP::IntRegsRegisterClass)
- BuildMI(MBB, I, TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
- .addReg(SrcReg, false, false, isKill);
- else if (RC == SP::FPRegsRegisterClass)
- BuildMI(MBB, I, TII.get(SP::STFri)).addFrameIndex(FI).addImm(0)
- .addReg(SrcReg, false, false, isKill);
- else if (RC == SP::DFPRegsRegisterClass)
- BuildMI(MBB, I, TII.get(SP::STDFri)).addFrameIndex(FI).addImm(0)
- .addReg(SrcReg, false, false, isKill);
- else
- assert(0 && "Can't store this register to stack slot");
-}
-
-void SparcRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
- bool isKill,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const {
- unsigned Opc = 0;
- if (RC == SP::IntRegsRegisterClass)
- Opc = SP::STri;
- else if (RC == SP::FPRegsRegisterClass)
- Opc = SP::STFri;
- else if (RC == SP::DFPRegsRegisterClass)
- Opc = SP::STDFri;
- else
- assert(0 && "Can't load this register");
- MachineInstrBuilder MIB = BuildMI(TII.get(Opc));
- for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
- MachineOperand &MO = Addr[i];
- if (MO.isRegister())
- MIB.addReg(MO.getReg());
- else if (MO.isImmediate())
- MIB.addImm(MO.getImm());
- else {
- assert(MO.isFI());
- MIB.addFrameIndex(MO.getIndex());
- }
- }
- MIB.addReg(SrcReg, false, false, isKill);
- NewMIs.push_back(MIB);
- return;
-}
-
-void SparcRegisterInfo::
-loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
- unsigned DestReg, int FI,
- const TargetRegisterClass *RC) const {
- if (RC == SP::IntRegsRegisterClass)
- BuildMI(MBB, I, TII.get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
- else if (RC == SP::FPRegsRegisterClass)
- BuildMI(MBB, I, TII.get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
- else if (RC == SP::DFPRegsRegisterClass)
- BuildMI(MBB, I, TII.get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
- else
- assert(0 && "Can't load this register from stack slot");
-}
-
-void SparcRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const {
- unsigned Opc = 0;
- if (RC == SP::IntRegsRegisterClass)
- Opc = SP::LDri;
- else if (RC == SP::FPRegsRegisterClass)
- Opc = SP::LDFri;
- else if (RC == SP::DFPRegsRegisterClass)
- Opc = SP::LDDFri;
- else
- assert(0 && "Can't load this register");
- MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
- for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
- MachineOperand &MO = Addr[i];
- if (MO.isReg())
- MIB.addReg(MO.getReg());
- else if (MO.isImm())
- MIB.addImm(MO.getImm());
- else {
- assert(MO.isFI());
- MIB.addFrameIndex(MO.getIndex());
- }
- }
- NewMIs.push_back(MIB);
- return;
-}
-
void SparcRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg,
SparcRegisterInfo(SparcSubtarget &st, const TargetInstrInfo &tii);
- /// Code Generation virtual methods...
- void storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- unsigned SrcReg, bool isKill, int FrameIndex,
- const TargetRegisterClass *RC) const;
-
- void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const;
-
- void loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- unsigned DestReg, int FrameIndex,
- const TargetRegisterClass *RC) const;
-
- void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const;
-
- void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- unsigned DestReg, unsigned SrcReg,
- const TargetRegisterClass *DestRC,
- const TargetRegisterClass *SrcRC) const;
-
+ /// Code Generation virtual methods...
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
unsigned DestReg, const MachineInstr *Orig) const;
return 2;
}
+static const MachineInstrBuilder &X86InstrAddOperand(MachineInstrBuilder &MIB,
+ MachineOperand &MO) {
+ if (MO.isRegister())
+ MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit(),
+ false, false, MO.getSubReg());
+ else if (MO.isImmediate())
+ MIB = MIB.addImm(MO.getImm());
+ else if (MO.isFrameIndex())
+ MIB = MIB.addFrameIndex(MO.getIndex());
+ else if (MO.isGlobalAddress())
+ MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
+ else if (MO.isConstantPoolIndex())
+ MIB = MIB.addConstantPoolIndex(MO.getIndex(), MO.getOffset());
+ else if (MO.isJumpTableIndex())
+ MIB = MIB.addJumpTableIndex(MO.getIndex());
+ else if (MO.isExternalSymbol())
+ MIB = MIB.addExternalSymbol(MO.getSymbolName());
+ else
+ assert(0 && "Unknown operand for X86InstrAddOperand!");
+
+ return MIB;
+}
+
unsigned
X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
BuildMI(MBB, MI, get(Opc), DestReg).addReg(SrcReg);
}
+static unsigned getStoreRegOpcode(const TargetRegisterClass *RC,
+ unsigned StackAlign) {
+ unsigned Opc = 0;
+ if (RC == &X86::GR64RegClass) {
+ Opc = X86::MOV64mr;
+ } else if (RC == &X86::GR32RegClass) {
+ Opc = X86::MOV32mr;
+ } else if (RC == &X86::GR16RegClass) {
+ Opc = X86::MOV16mr;
+ } else if (RC == &X86::GR8RegClass) {
+ Opc = X86::MOV8mr;
+ } else if (RC == &X86::GR32_RegClass) {
+ Opc = X86::MOV32_mr;
+ } else if (RC == &X86::GR16_RegClass) {
+ Opc = X86::MOV16_mr;
+ } else if (RC == &X86::RFP80RegClass) {
+ Opc = X86::ST_FpP80m; // pops
+ } else if (RC == &X86::RFP64RegClass) {
+ Opc = X86::ST_Fp64m;
+ } else if (RC == &X86::RFP32RegClass) {
+ Opc = X86::ST_Fp32m;
+ } else if (RC == &X86::FR32RegClass) {
+ Opc = X86::MOVSSmr;
+ } else if (RC == &X86::FR64RegClass) {
+ Opc = X86::MOVSDmr;
+ } else if (RC == &X86::VR128RegClass) {
+ // FIXME: Use movaps once we are capable of selectively
+ // aligning functions that spill SSE registers on 16-byte boundaries.
+ Opc = StackAlign >= 16 ? X86::MOVAPSmr : X86::MOVUPSmr;
+ } else if (RC == &X86::VR64RegClass) {
+ Opc = X86::MMX_MOVQ64mr;
+ } else {
+ assert(0 && "Unknown regclass");
+ abort();
+ }
+
+ return Opc;
+}
+
+void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned SrcReg, bool isKill, int FrameIdx,
+ const TargetRegisterClass *RC) const {
+ unsigned Opc = getStoreRegOpcode(RC, RI.getStackAlignment());
+ addFrameReference(BuildMI(MBB, MI, get(Opc)), FrameIdx)
+ .addReg(SrcReg, false, false, isKill);
+}
+
+void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
+ bool isKill,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const {
+ unsigned Opc = getStoreRegOpcode(RC, RI.getStackAlignment());
+ MachineInstrBuilder MIB = BuildMI(get(Opc));
+ for (unsigned i = 0, e = Addr.size(); i != e; ++i)
+ MIB = X86InstrAddOperand(MIB, Addr[i]);
+ MIB.addReg(SrcReg, false, false, isKill);
+ NewMIs.push_back(MIB);
+}
+
+static unsigned getLoadRegOpcode(const TargetRegisterClass *RC,
+ unsigned StackAlign) {
+ unsigned Opc = 0;
+ if (RC == &X86::GR64RegClass) {
+ Opc = X86::MOV64rm;
+ } else if (RC == &X86::GR32RegClass) {
+ Opc = X86::MOV32rm;
+ } else if (RC == &X86::GR16RegClass) {
+ Opc = X86::MOV16rm;
+ } else if (RC == &X86::GR8RegClass) {
+ Opc = X86::MOV8rm;
+ } else if (RC == &X86::GR32_RegClass) {
+ Opc = X86::MOV32_rm;
+ } else if (RC == &X86::GR16_RegClass) {
+ Opc = X86::MOV16_rm;
+ } else if (RC == &X86::RFP80RegClass) {
+ Opc = X86::LD_Fp80m;
+ } else if (RC == &X86::RFP64RegClass) {
+ Opc = X86::LD_Fp64m;
+ } else if (RC == &X86::RFP32RegClass) {
+ Opc = X86::LD_Fp32m;
+ } else if (RC == &X86::FR32RegClass) {
+ Opc = X86::MOVSSrm;
+ } else if (RC == &X86::FR64RegClass) {
+ Opc = X86::MOVSDrm;
+ } else if (RC == &X86::VR128RegClass) {
+ // FIXME: Use movaps once we are capable of selectively
+ // aligning functions that spill SSE registers on 16-byte boundaries.
+ Opc = StackAlign >= 16 ? X86::MOVAPSrm : X86::MOVUPSrm;
+ } else if (RC == &X86::VR64RegClass) {
+ Opc = X86::MMX_MOVQ64rm;
+ } else {
+ assert(0 && "Unknown regclass");
+ abort();
+ }
+
+ return Opc;
+}
+
+void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned DestReg, int FrameIdx,
+ const TargetRegisterClass *RC) const{
+ unsigned Opc = getLoadRegOpcode(RC, RI.getStackAlignment());
+ addFrameReference(BuildMI(MBB, MI, get(Opc), DestReg), FrameIdx);
+}
+
+void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const {
+ unsigned Opc = getLoadRegOpcode(RC, RI.getStackAlignment());
+ MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
+ for (unsigned i = 0, e = Addr.size(); i != e; ++i)
+ MIB = X86InstrAddOperand(MIB, Addr[i]);
+ NewMIs.push_back(MIB);
+}
+
bool X86InstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
if (MBB.empty()) return false;
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const;
+ virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned SrcReg, bool isKill, int FrameIndex,
+ const TargetRegisterClass *RC) const;
+
+ virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const;
+
+ virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ unsigned DestReg, int FrameIndex,
+ const TargetRegisterClass *RC) const;
+
+ virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const;
virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
return Opc;
}
-void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned SrcReg, bool isKill, int FrameIdx,
- const TargetRegisterClass *RC) const {
- unsigned Opc = getStoreRegOpcode(RC, StackAlign);
- addFrameReference(BuildMI(MBB, MI, TII.get(Opc)), FrameIdx)
- .addReg(SrcReg, false, false, isKill);
-}
-
-void X86RegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
- bool isKill,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const {
- unsigned Opc = getStoreRegOpcode(RC, StackAlign);
- MachineInstrBuilder MIB = BuildMI(TII.get(Opc));
- for (unsigned i = 0, e = Addr.size(); i != e; ++i)
- MIB = X86InstrAddOperand(MIB, Addr[i]);
- MIB.addReg(SrcReg, false, false, isKill);
- NewMIs.push_back(MIB);
-}
-
-static unsigned getLoadRegOpcode(const TargetRegisterClass *RC,
- unsigned StackAlign) {
- unsigned Opc = 0;
- if (RC == &X86::GR64RegClass) {
- Opc = X86::MOV64rm;
- } else if (RC == &X86::GR32RegClass) {
- Opc = X86::MOV32rm;
- } else if (RC == &X86::GR16RegClass) {
- Opc = X86::MOV16rm;
- } else if (RC == &X86::GR8RegClass) {
- Opc = X86::MOV8rm;
- } else if (RC == &X86::GR32_RegClass) {
- Opc = X86::MOV32_rm;
- } else if (RC == &X86::GR16_RegClass) {
- Opc = X86::MOV16_rm;
- } else if (RC == &X86::RFP80RegClass) {
- Opc = X86::LD_Fp80m;
- } else if (RC == &X86::RFP64RegClass) {
- Opc = X86::LD_Fp64m;
- } else if (RC == &X86::RFP32RegClass) {
- Opc = X86::LD_Fp32m;
- } else if (RC == &X86::FR32RegClass) {
- Opc = X86::MOVSSrm;
- } else if (RC == &X86::FR64RegClass) {
- Opc = X86::MOVSDrm;
- } else if (RC == &X86::VR128RegClass) {
- // FIXME: Use movaps once we are capable of selectively
- // aligning functions that spill SSE registers on 16-byte boundaries.
- Opc = StackAlign >= 16 ? X86::MOVAPSrm : X86::MOVUPSrm;
- } else if (RC == &X86::VR64RegClass) {
- Opc = X86::MMX_MOVQ64rm;
- } else {
- assert(0 && "Unknown regclass");
- abort();
- }
-
- return Opc;
-}
-
-void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned DestReg, int FrameIdx,
- const TargetRegisterClass *RC) const{
- unsigned Opc = getLoadRegOpcode(RC, StackAlign);
- addFrameReference(BuildMI(MBB, MI, TII.get(Opc), DestReg), FrameIdx);
-}
-
-void X86RegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const {
- unsigned Opc = getLoadRegOpcode(RC, StackAlign);
- MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
- for (unsigned i = 0, e = Addr.size(); i != e; ++i)
- MIB = X86InstrAddOperand(MIB, Addr[i]);
- NewMIs.push_back(MIB);
-}
-
const TargetRegisterClass *
X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
if (RC == &X86::CCRRegClass)
// Emit the load instruction.
if (UnfoldLoad) {
- loadRegFromAddr(MF, Reg, AddrOps, RC, NewMIs);
+ TII.loadRegFromAddr(MF, Reg, AddrOps, RC, NewMIs);
if (UnfoldStore) {
// Address operands cannot be marked isKill.
for (unsigned i = 1; i != 5; ++i) {
const TargetOperandInfo &DstTOI = TID.OpInfo[0];
const TargetRegisterClass *DstRC = (DstTOI.Flags & M_LOOK_UP_PTR_REG_CLASS)
? TII.getPointerRegClass() : getRegClass(DstTOI.RegClass);
- storeRegToAddr(MF, Reg, true, AddrOps, DstRC, NewMIs);
+ TII.storeRegToAddr(MF, Reg, true, AddrOps, DstRC, NewMIs);
}
return true;
}
+static unsigned getLoadRegOpcode(const TargetRegisterClass *RC,
+ unsigned StackAlign) {
+ unsigned Opc = 0;
+ if (RC == &X86::GR64RegClass) {
+ Opc = X86::MOV64rm;
+ } else if (RC == &X86::GR32RegClass) {
+ Opc = X86::MOV32rm;
+ } else if (RC == &X86::GR16RegClass) {
+ Opc = X86::MOV16rm;
+ } else if (RC == &X86::GR8RegClass) {
+ Opc = X86::MOV8rm;
+ } else if (RC == &X86::GR32_RegClass) {
+ Opc = X86::MOV32_rm;
+ } else if (RC == &X86::GR16_RegClass) {
+ Opc = X86::MOV16_rm;
+ } else if (RC == &X86::RFP80RegClass) {
+ Opc = X86::LD_Fp80m;
+ } else if (RC == &X86::RFP64RegClass) {
+ Opc = X86::LD_Fp64m;
+ } else if (RC == &X86::RFP32RegClass) {
+ Opc = X86::LD_Fp32m;
+ } else if (RC == &X86::FR32RegClass) {
+ Opc = X86::MOVSSrm;
+ } else if (RC == &X86::FR64RegClass) {
+ Opc = X86::MOVSDrm;
+ } else if (RC == &X86::VR128RegClass) {
+ // FIXME: Use movaps once we are capable of selectively
+ // aligning functions that spill SSE registers on 16-byte boundaries.
+ Opc = StackAlign >= 16 ? X86::MOVAPSrm : X86::MOVUPSrm;
+ } else if (RC == &X86::VR64RegClass) {
+ Opc = X86::MMX_MOVQ64rm;
+ } else {
+ assert(0 && "Unknown regclass");
+ abort();
+ }
+
+ return Opc;
+}
bool
X86RegisterInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
/// register identifier.
unsigned getX86RegNum(unsigned RegNo);
+ unsigned getStackAlignment() const { return StackAlign; }
+
/// getDwarfRegNum - allows modification of X86GenRegisterInfo::getDwarfRegNum
/// (created by TableGen) for target dependencies.
int getDwarfRegNum(unsigned RegNum, bool isEH) const;
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI) const;
-
- void storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned SrcReg, bool isKill, int FrameIndex,
- const TargetRegisterClass *RC) const;
-
- void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const;
-
- void loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned DestReg, int FrameIndex,
- const TargetRegisterClass *RC) const;
-
- void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const;
-
- void copyRegToReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned DestReg, unsigned SrcReg,
- const TargetRegisterClass *DestRC,
- const TargetRegisterClass *SrcRC) const;
const TargetRegisterClass *
getCrossCopyRegClass(const TargetRegisterClass *RC) const;
projects / oota-llvm.git / commitdiff