1 //===- IA64RegisterInfo.cpp - IA64 Register Information ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the IA64 implementation of the MRegisterInfo class. This
11 // file is responsible for the frame pointer elimination optimization on IA64.
13 //===----------------------------------------------------------------------===//
16 #include "IA64RegisterInfo.h"
17 #include "IA64InstrBuilder.h"
18 #include "IA64MachineFunctionInfo.h"
19 #include "llvm/Constants.h"
20 #include "llvm/Type.h"
21 #include "llvm/CodeGen/ValueTypes.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineLocation.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/Target/TargetFrameInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Target/TargetInstrInfo.h"
31 #include "llvm/ADT/BitVector.h"
32 #include "llvm/ADT/STLExtras.h"
35 IA64RegisterInfo::IA64RegisterInfo(const TargetInstrInfo &tii)
36 : IA64GenRegisterInfo(IA64::ADJUSTCALLSTACKDOWN, IA64::ADJUSTCALLSTACKUP),
39 void IA64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
40 MachineBasicBlock::iterator MI,
41 unsigned SrcReg, bool isKill,
43 const TargetRegisterClass *RC) const{
45 if (RC == IA64::FPRegisterClass) {
46 BuildMI(MBB, MI, TII.get(IA64::STF_SPILL)).addFrameIndex(FrameIdx)
47 .addReg(SrcReg, false, false, isKill);
48 } else if (RC == IA64::GRRegisterClass) {
49 BuildMI(MBB, MI, TII.get(IA64::ST8)).addFrameIndex(FrameIdx)
50 .addReg(SrcReg, false, false, isKill);
51 } else if (RC == IA64::PRRegisterClass) {
52 /* we use IA64::r2 as a temporary register for doing this hackery. */
54 BuildMI(MBB, MI, TII.get(IA64::MOV), IA64::r2).addReg(IA64::r0);
55 // then conditionally add 1:
56 BuildMI(MBB, MI, TII.get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2)
57 .addImm(1).addReg(SrcReg, false, false, isKill);
58 // and then store it to the stack
59 BuildMI(MBB, MI, TII.get(IA64::ST8)).addFrameIndex(FrameIdx).addReg(IA64::r2);
61 "sorry, I don't know how to store this sort of reg in the stack\n");
64 void IA64RegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
66 SmallVectorImpl<MachineOperand> &Addr,
67 const TargetRegisterClass *RC,
68 SmallVectorImpl<MachineInstr*> &NewMIs) const {
70 if (RC == IA64::FPRegisterClass) {
72 } else if (RC == IA64::GRRegisterClass) {
74 } else if (RC == IA64::PRRegisterClass) {
78 "sorry, I don't know how to store this sort of reg\n");
81 MachineInstrBuilder MIB = BuildMI(TII.get(Opc));
82 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
83 MachineOperand &MO = Addr[i];
85 MIB.addReg(MO.getReg());
86 else if (MO.isImmediate())
87 MIB.addImm(MO.getImm());
89 MIB.addFrameIndex(MO.getIndex());
91 MIB.addReg(SrcReg, false, false, isKill);
92 NewMIs.push_back(MIB);
97 void IA64RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
98 MachineBasicBlock::iterator MI,
99 unsigned DestReg, int FrameIdx,
100 const TargetRegisterClass *RC)const{
102 if (RC == IA64::FPRegisterClass) {
103 BuildMI(MBB, MI, TII.get(IA64::LDF_FILL), DestReg).addFrameIndex(FrameIdx);
104 } else if (RC == IA64::GRRegisterClass) {
105 BuildMI(MBB, MI, TII.get(IA64::LD8), DestReg).addFrameIndex(FrameIdx);
106 } else if (RC == IA64::PRRegisterClass) {
107 // first we load a byte from the stack into r2, our 'predicate hackery'
109 BuildMI(MBB, MI, TII.get(IA64::LD8), IA64::r2).addFrameIndex(FrameIdx);
110 // then we compare it to zero. If it _is_ zero, compare-not-equal to
111 // r0 gives us 0, which is what we want, so that's nice.
112 BuildMI(MBB, MI, TII.get(IA64::CMPNE), DestReg).addReg(IA64::r2).addReg(IA64::r0);
114 "sorry, I don't know how to load this sort of reg from the stack\n");
117 void IA64RegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
118 SmallVectorImpl<MachineOperand> &Addr,
119 const TargetRegisterClass *RC,
120 SmallVectorImpl<MachineInstr*> &NewMIs) const {
122 if (RC == IA64::FPRegisterClass) {
124 } else if (RC == IA64::GRRegisterClass) {
126 } else if (RC == IA64::PRRegisterClass) {
130 "sorry, I don't know how to store this sort of reg\n");
133 MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
134 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
135 MachineOperand &MO = Addr[i];
137 MIB.addReg(MO.getReg());
138 else if (MO.isImmediate())
139 MIB.addImm(MO.getImm());
141 MIB.addFrameIndex(MO.getIndex());
143 NewMIs.push_back(MIB);
147 void IA64RegisterInfo::reMaterialize(MachineBasicBlock &MBB,
148 MachineBasicBlock::iterator I,
150 const MachineInstr *Orig) const {
151 MachineInstr *MI = Orig->clone();
152 MI->getOperand(0).setReg(DestReg);
156 const unsigned* IA64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
158 static const unsigned CalleeSavedRegs[] = {
161 return CalleeSavedRegs;
164 const TargetRegisterClass* const*
165 IA64RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
166 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
169 return CalleeSavedRegClasses;
172 BitVector IA64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
173 BitVector Reserved(getNumRegs());
174 Reserved.set(IA64::r0);
175 Reserved.set(IA64::r1);
176 Reserved.set(IA64::r2);
177 Reserved.set(IA64::r5);
178 Reserved.set(IA64::r12);
179 Reserved.set(IA64::r13);
180 Reserved.set(IA64::r22);
181 Reserved.set(IA64::rp);
185 //===----------------------------------------------------------------------===//
186 // Stack Frame Processing methods
187 //===----------------------------------------------------------------------===//
189 // hasFP - Return true if the specified function should have a dedicated frame
190 // pointer register. This is true if the function has variable sized allocas or
191 // if frame pointer elimination is disabled.
193 bool IA64RegisterInfo::hasFP(const MachineFunction &MF) const {
194 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
197 void IA64RegisterInfo::
198 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
199 MachineBasicBlock::iterator I) const {
201 // If we have a frame pointer, turn the adjcallstackup instruction into a
202 // 'sub SP, <amt>' and the adjcallstackdown instruction into 'add SP,
204 MachineInstr *Old = I;
205 unsigned Amount = Old->getOperand(0).getImm();
207 // We need to keep the stack aligned properly. To do this, we round the
208 // amount of space needed for the outgoing arguments up to the next
209 // alignment boundary.
210 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
211 Amount = (Amount+Align-1)/Align*Align;
214 if (Old->getOpcode() == IA64::ADJUSTCALLSTACKDOWN) {
215 New=BuildMI(TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12)
218 assert(Old->getOpcode() == IA64::ADJUSTCALLSTACKUP);
219 New=BuildMI(TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12)
223 // Replace the pseudo instruction with a new instruction...
231 void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
232 int SPAdj, RegScavenger *RS)const{
233 assert(SPAdj == 0 && "Unexpected");
236 MachineInstr &MI = *II;
237 MachineBasicBlock &MBB = *MI.getParent();
238 MachineFunction &MF = *MBB.getParent();
242 while (!MI.getOperand(i).isFrameIndex()) {
244 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
247 int FrameIndex = MI.getOperand(i).getIndex();
249 // choose a base register: ( hasFP? framepointer : stack pointer )
250 unsigned BaseRegister = FP ? IA64::r5 : IA64::r12;
251 // Add the base register
252 MI.getOperand(i).ChangeToRegister(BaseRegister, false);
254 // Now add the frame object offset to the offset from r1.
255 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
257 // If we're not using a Frame Pointer that has been set to the value of the
258 // SP before having the stack size subtracted from it, then add the stack size
259 // to Offset to get the correct offset.
260 Offset += MF.getFrameInfo()->getStackSize();
262 // XXX: we use 'r22' as another hack+slash temporary register here :(
263 if (Offset <= 8191 && Offset >= -8192) { // smallish offset
265 MI.getOperand(i).ChangeToRegister(IA64::r22, false);
267 MachineInstr* nMI=BuildMI(TII.get(IA64::ADDIMM22), IA64::r22)
268 .addReg(BaseRegister).addImm(Offset);
272 MI.getOperand(i).ChangeToRegister(IA64::r22, false);
274 nMI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(Offset);
276 nMI=BuildMI(TII.get(IA64::ADD), IA64::r22).addReg(BaseRegister)
283 void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const {
284 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
285 MachineBasicBlock::iterator MBBI = MBB.begin();
286 MachineFrameInfo *MFI = MF.getFrameInfo();
290 // first, we handle the 'alloc' instruction, that should be right up the
291 // top of any function
292 static const unsigned RegsInOrder[96] = { // there are 96 GPRs the
294 IA64::r32, IA64::r33, IA64::r34, IA64::r35,
295 IA64::r36, IA64::r37, IA64::r38, IA64::r39, IA64::r40, IA64::r41,
296 IA64::r42, IA64::r43, IA64::r44, IA64::r45, IA64::r46, IA64::r47,
297 IA64::r48, IA64::r49, IA64::r50, IA64::r51, IA64::r52, IA64::r53,
298 IA64::r54, IA64::r55, IA64::r56, IA64::r57, IA64::r58, IA64::r59,
299 IA64::r60, IA64::r61, IA64::r62, IA64::r63, IA64::r64, IA64::r65,
300 IA64::r66, IA64::r67, IA64::r68, IA64::r69, IA64::r70, IA64::r71,
301 IA64::r72, IA64::r73, IA64::r74, IA64::r75, IA64::r76, IA64::r77,
302 IA64::r78, IA64::r79, IA64::r80, IA64::r81, IA64::r82, IA64::r83,
303 IA64::r84, IA64::r85, IA64::r86, IA64::r87, IA64::r88, IA64::r89,
304 IA64::r90, IA64::r91, IA64::r92, IA64::r93, IA64::r94, IA64::r95,
305 IA64::r96, IA64::r97, IA64::r98, IA64::r99, IA64::r100, IA64::r101,
306 IA64::r102, IA64::r103, IA64::r104, IA64::r105, IA64::r106, IA64::r107,
307 IA64::r108, IA64::r109, IA64::r110, IA64::r111, IA64::r112, IA64::r113,
308 IA64::r114, IA64::r115, IA64::r116, IA64::r117, IA64::r118, IA64::r119,
309 IA64::r120, IA64::r121, IA64::r122, IA64::r123, IA64::r124, IA64::r125,
310 IA64::r126, IA64::r127 };
312 unsigned numStackedGPRsUsed=0;
313 for (int i=0; i != 96; i++) {
314 if (MF.getRegInfo().isPhysRegUsed(RegsInOrder[i]))
315 numStackedGPRsUsed=i+1; // (i+1 and not ++ - consider fn(fp, fp, int)
318 unsigned numOutRegsUsed=MF.getInfo<IA64FunctionInfo>()->outRegsUsed;
320 // XXX FIXME : this code should be a bit more reliable (in case there _isn't_
321 // a pseudo_alloc in the MBB)
322 unsigned dstRegOfPseudoAlloc;
323 for(MBBI = MBB.begin(); /*MBBI->getOpcode() != IA64::PSEUDO_ALLOC*/; ++MBBI) {
324 assert(MBBI != MBB.end());
325 if(MBBI->getOpcode() == IA64::PSEUDO_ALLOC) {
326 dstRegOfPseudoAlloc=MBBI->getOperand(0).getReg();
331 MI=BuildMI(TII.get(IA64::ALLOC)).addReg(dstRegOfPseudoAlloc).addImm(0). \
332 addImm(numStackedGPRsUsed).addImm(numOutRegsUsed).addImm(0);
333 MBB.insert(MBBI, MI);
335 // Get the number of bytes to allocate from the FrameInfo
336 unsigned NumBytes = MFI->getStackSize();
339 NumBytes += 8; // reserve space for the old FP
341 // Do we need to allocate space on the stack?
345 // Add 16 bytes at the bottom of the stack (scratch area)
346 // and round the size to a multiple of the alignment.
347 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
348 unsigned Size = 16 + (FP ? 8 : 0);
349 NumBytes = (NumBytes+Size+Align-1)/Align*Align;
351 // Update frame info to pretend that this is part of the stack...
352 MFI->setStackSize(NumBytes);
354 // adjust stack pointer: r12 -= numbytes
355 if (NumBytes <= 8191) {
356 MI=BuildMI(TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12).
358 MBB.insert(MBBI, MI);
359 } else { // we use r22 as a scratch register here
360 MI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(-NumBytes);
361 // FIXME: MOVLSI32 expects a _u_32imm
362 MBB.insert(MBBI, MI); // first load the decrement into r22
363 MI=BuildMI(TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12).addReg(IA64::r22);
364 MBB.insert(MBBI, MI); // then add (subtract) it to r12 (stack ptr)
367 // now if we need to, save the old FP and set the new
369 MI = BuildMI(TII.get(IA64::ST8)).addReg(IA64::r12).addReg(IA64::r5);
370 MBB.insert(MBBI, MI);
371 // this must be the last instr in the prolog ? (XXX: why??)
372 MI = BuildMI(TII.get(IA64::MOV), IA64::r5).addReg(IA64::r12);
373 MBB.insert(MBBI, MI);
378 void IA64RegisterInfo::emitEpilogue(MachineFunction &MF,
379 MachineBasicBlock &MBB) const {
380 const MachineFrameInfo *MFI = MF.getFrameInfo();
381 MachineBasicBlock::iterator MBBI = prior(MBB.end());
383 assert(MBBI->getOpcode() == IA64::RET &&
384 "Can only insert epilog into returning blocks");
388 // Get the number of bytes allocated from the FrameInfo...
389 unsigned NumBytes = MFI->getStackSize();
391 //now if we need to, restore the old FP
394 //copy the FP into the SP (discards allocas)
395 MI=BuildMI(TII.get(IA64::MOV), IA64::r12).addReg(IA64::r5);
396 MBB.insert(MBBI, MI);
398 MI=BuildMI(TII.get(IA64::LD8), IA64::r5).addReg(IA64::r5);
399 MBB.insert(MBBI, MI);
404 if (NumBytes <= 8191) {
405 MI=BuildMI(TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12).
407 MBB.insert(MBBI, MI);
409 MI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(NumBytes);
410 MBB.insert(MBBI, MI);
411 MI=BuildMI(TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12).
413 MBB.insert(MBBI, MI);
419 unsigned IA64RegisterInfo::getRARegister() const {
420 assert(0 && "What is the return address register");
424 unsigned IA64RegisterInfo::getFrameRegister(MachineFunction &MF) const {
425 return hasFP(MF) ? IA64::r5 : IA64::r12;
428 unsigned IA64RegisterInfo::getEHExceptionRegister() const {
429 assert(0 && "What is the exception register");
433 unsigned IA64RegisterInfo::getEHHandlerRegister() const {
434 assert(0 && "What is the exception handler register");
438 int IA64RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
439 assert(0 && "What is the dwarf register number");
443 #include "IA64GenRegisterInfo.inc"