1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for SI
13 //===----------------------------------------------------------------------===//
17 #define _USE_MATH_DEFINES
21 #include "SIISelLowering.h"
23 #include "AMDGPUIntrinsicInfo.h"
24 #include "AMDGPUSubtarget.h"
25 #include "SIInstrInfo.h"
26 #include "SIMachineFunctionInfo.h"
27 #include "SIRegisterInfo.h"
28 #include "llvm/ADT/BitVector.h"
29 #include "llvm/CodeGen/CallingConvLower.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/SelectionDAG.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/ADT/SmallString.h"
38 SITargetLowering::SITargetLowering(TargetMachine &TM,
39 const AMDGPUSubtarget &STI)
40 : AMDGPUTargetLowering(TM, STI) {
41 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
42 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
44 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
45 addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass);
47 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
48 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass);
50 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);
51 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
52 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
54 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
55 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
57 addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass);
58 addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
60 addRegisterClass(MVT::v16i32, &AMDGPU::SReg_512RegClass);
61 addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
63 computeRegisterProperties(STI.getRegisterInfo());
65 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
66 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
67 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
68 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
70 setOperationAction(ISD::ADD, MVT::i32, Legal);
71 setOperationAction(ISD::ADDC, MVT::i32, Legal);
72 setOperationAction(ISD::ADDE, MVT::i32, Legal);
73 setOperationAction(ISD::SUBC, MVT::i32, Legal);
74 setOperationAction(ISD::SUBE, MVT::i32, Legal);
76 setOperationAction(ISD::FSIN, MVT::f32, Custom);
77 setOperationAction(ISD::FCOS, MVT::f32, Custom);
79 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
80 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
82 // We need to custom lower vector stores from local memory
83 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
84 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
85 setOperationAction(ISD::LOAD, MVT::v16i32, Custom);
87 setOperationAction(ISD::STORE, MVT::v8i32, Custom);
88 setOperationAction(ISD::STORE, MVT::v16i32, Custom);
90 setOperationAction(ISD::STORE, MVT::i1, Custom);
91 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
93 setOperationAction(ISD::SELECT, MVT::i64, Custom);
94 setOperationAction(ISD::SELECT, MVT::f64, Promote);
95 AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
97 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
98 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
99 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
100 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
102 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
103 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
105 setOperationAction(ISD::BSWAP, MVT::i32, Legal);
107 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Legal);
108 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
109 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
111 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Legal);
112 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
113 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
115 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
116 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
117 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
120 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom);
122 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
123 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom);
124 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v16i8, Custom);
125 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
127 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
128 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
130 for (MVT VT : MVT::integer_valuetypes()) {
134 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
135 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Legal);
136 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Legal);
137 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
139 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
140 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Legal);
141 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Legal);
142 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
144 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
145 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Legal);
146 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Legal);
147 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
150 for (MVT VT : MVT::integer_vector_valuetypes()) {
151 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i16, Expand);
152 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v16i16, Expand);
155 for (MVT VT : MVT::fp_valuetypes())
156 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
158 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
159 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand);
160 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Expand);
161 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand);
163 setOperationAction(ISD::LOAD, MVT::i1, Custom);
165 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
166 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
167 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
169 // These should use UDIVREM, so set them to expand
170 setOperationAction(ISD::UDIV, MVT::i64, Expand);
171 setOperationAction(ISD::UREM, MVT::i64, Expand);
173 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
174 setOperationAction(ISD::SELECT, MVT::i1, Promote);
176 // We only support LOAD/STORE and vector manipulation ops for vectors
177 // with > 4 elements.
178 for (MVT VT : {MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32}) {
179 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
183 case ISD::BUILD_VECTOR:
185 case ISD::EXTRACT_VECTOR_ELT:
186 case ISD::INSERT_VECTOR_ELT:
187 case ISD::INSERT_SUBVECTOR:
188 case ISD::EXTRACT_SUBVECTOR:
190 case ISD::CONCAT_VECTORS:
191 setOperationAction(Op, VT, Custom);
194 setOperationAction(Op, VT, Expand);
200 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS) {
201 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
202 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
203 setOperationAction(ISD::FRINT, MVT::f64, Legal);
206 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
207 setOperationAction(ISD::FDIV, MVT::f32, Custom);
208 setOperationAction(ISD::FDIV, MVT::f64, Custom);
210 setTargetDAGCombine(ISD::FADD);
211 setTargetDAGCombine(ISD::FSUB);
212 setTargetDAGCombine(ISD::FMINNUM);
213 setTargetDAGCombine(ISD::FMAXNUM);
214 setTargetDAGCombine(ISD::SMIN);
215 setTargetDAGCombine(ISD::SMAX);
216 setTargetDAGCombine(ISD::UMIN);
217 setTargetDAGCombine(ISD::UMAX);
218 setTargetDAGCombine(ISD::SELECT_CC);
219 setTargetDAGCombine(ISD::SETCC);
220 setTargetDAGCombine(ISD::AND);
221 setTargetDAGCombine(ISD::OR);
222 setTargetDAGCombine(ISD::UINT_TO_FP);
224 // All memory operations. Some folding on the pointer operand is done to help
225 // matching the constant offsets in the addressing modes.
226 setTargetDAGCombine(ISD::LOAD);
227 setTargetDAGCombine(ISD::STORE);
228 setTargetDAGCombine(ISD::ATOMIC_LOAD);
229 setTargetDAGCombine(ISD::ATOMIC_STORE);
230 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP);
231 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
232 setTargetDAGCombine(ISD::ATOMIC_SWAP);
233 setTargetDAGCombine(ISD::ATOMIC_LOAD_ADD);
234 setTargetDAGCombine(ISD::ATOMIC_LOAD_SUB);
235 setTargetDAGCombine(ISD::ATOMIC_LOAD_AND);
236 setTargetDAGCombine(ISD::ATOMIC_LOAD_OR);
237 setTargetDAGCombine(ISD::ATOMIC_LOAD_XOR);
238 setTargetDAGCombine(ISD::ATOMIC_LOAD_NAND);
239 setTargetDAGCombine(ISD::ATOMIC_LOAD_MIN);
240 setTargetDAGCombine(ISD::ATOMIC_LOAD_MAX);
241 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMIN);
242 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMAX);
244 setSchedulingPreference(Sched::RegPressure);
247 //===----------------------------------------------------------------------===//
248 // TargetLowering queries
249 //===----------------------------------------------------------------------===//
251 bool SITargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &,
253 // SI has some legal vector types, but no legal vector operations. Say no
254 // shuffles are legal in order to prefer scalarizing some vector operations.
258 bool SITargetLowering::isLegalFlatAddressingMode(const AddrMode &AM) const {
259 // Flat instructions do not have offsets, and only have the register
261 return AM.BaseOffs == 0 && (AM.Scale == 0 || AM.Scale == 1);
264 bool SITargetLowering::isLegalAddressingMode(const DataLayout &DL,
265 const AddrMode &AM, Type *Ty,
267 // No global is ever allowed as a base.
272 case AMDGPUAS::GLOBAL_ADDRESS:
273 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
274 // Assume the we will use FLAT for all global memory accesses
276 // FIXME: This assumption is currently wrong. On VI we still use
277 // MUBUF instructions for the r + i addressing mode. As currently
278 // implemented, the MUBUF instructions only work on buffer < 4GB.
279 // It may be possible to support > 4GB buffers with MUBUF instructions,
280 // by setting the stride value in the resource descriptor which would
281 // increase the size limit to (stride * 4GB). However, this is risky,
282 // because it has never been validated.
283 return isLegalFlatAddressingMode(AM);
286 case AMDGPUAS::PRIVATE_ADDRESS:
287 case AMDGPUAS::CONSTANT_ADDRESS: // XXX - Should we assume SMRD instructions?
288 case AMDGPUAS::UNKNOWN_ADDRESS_SPACE: {
289 // MUBUF / MTBUF instructions have a 12-bit unsigned byte offset, and
290 // additionally can do r + r + i with addr64. 32-bit has more addressing
291 // mode options. Depending on the resource constant, it can also do
292 // (i64 r0) + (i32 r1) * (i14 i).
294 // SMRD instructions have an 8-bit, dword offset.
296 // Assume nonunifom access, since the address space isn't enough to know
297 // what instruction we will use, and since we don't know if this is a load
298 // or store and scalar stores are only available on VI.
300 // We also know if we are doing an extload, we can't do a scalar load.
302 // Private arrays end up using a scratch buffer most of the time, so also
303 // assume those use MUBUF instructions. Scratch loads / stores are currently
304 // implemented as mubuf instructions with offen bit set, so slightly
305 // different than the normal addr64.
306 if (!isUInt<12>(AM.BaseOffs))
309 // FIXME: Since we can split immediate into soffset and immediate offset,
310 // would it make sense to allow any immediate?
313 case 0: // r + i or just i, depending on HasBaseReg.
316 return true; // We have r + r or r + i.
323 // Allow 2 * r as r + r
324 // Or 2 * r + i is allowed as r + r + i.
326 default: // Don't allow n * r
330 case AMDGPUAS::LOCAL_ADDRESS:
331 case AMDGPUAS::REGION_ADDRESS: {
332 // Basic, single offset DS instructions allow a 16-bit unsigned immediate
334 // XXX - If doing a 4-byte aligned 8-byte type access, we effectively have
335 // an 8-bit dword offset but we don't know the alignment here.
336 if (!isUInt<16>(AM.BaseOffs))
339 if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
342 if (AM.Scale == 1 && AM.HasBaseReg)
347 case AMDGPUAS::FLAT_ADDRESS:
348 return isLegalFlatAddressingMode(AM);
351 llvm_unreachable("unhandled address space");
355 bool SITargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
358 bool *IsFast) const {
362 // TODO: I think v3i32 should allow unaligned accesses on CI with DS_READ_B96,
363 // which isn't a simple VT.
364 if (!VT.isSimple() || VT == MVT::Other)
367 // TODO - CI+ supports unaligned memory accesses, but this requires driver
370 // XXX - The only mention I see of this in the ISA manual is for LDS direct
371 // reads the "byte address and must be dword aligned". Is it also true for the
372 // normal loads and stores?
373 if (AddrSpace == AMDGPUAS::LOCAL_ADDRESS) {
374 // ds_read/write_b64 require 8-byte alignment, but we can do a 4 byte
375 // aligned, 8 byte access in a single operation using ds_read2/write2_b32
376 // with adjacent offsets.
377 return Align % 4 == 0;
380 // Smaller than dword value must be aligned.
381 // FIXME: This should be allowed on CI+
382 if (VT.bitsLT(MVT::i32))
385 // 8.1.6 - For Dword or larger reads or writes, the two LSBs of the
386 // byte-address are ignored, thus forcing Dword alignment.
387 // This applies to private, global, and constant memory.
391 return VT.bitsGT(MVT::i32) && Align % 4 == 0;
394 EVT SITargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
395 unsigned SrcAlign, bool IsMemset,
398 MachineFunction &MF) const {
399 // FIXME: Should account for address space here.
401 // The default fallback uses the private pointer size as a guess for a type to
402 // use. Make sure we switch these to 64-bit accesses.
404 if (Size >= 16 && DstAlign >= 4) // XXX: Should only do for global
407 if (Size >= 8 && DstAlign >= 4)
414 TargetLoweringBase::LegalizeTypeAction
415 SITargetLowering::getPreferredVectorAction(EVT VT) const {
416 if (VT.getVectorNumElements() != 1 && VT.getScalarType().bitsLE(MVT::i16))
417 return TypeSplitVector;
419 return TargetLoweringBase::getPreferredVectorAction(VT);
422 bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
424 const SIInstrInfo *TII =
425 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
426 return TII->isInlineConstant(Imm);
429 static EVT toIntegerVT(EVT VT) {
431 return VT.changeVectorElementTypeToInteger();
432 return MVT::getIntegerVT(VT.getSizeInBits());
435 SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
436 SDLoc SL, SDValue Chain,
437 unsigned Offset, bool Signed) const {
438 const DataLayout &DL = DAG.getDataLayout();
439 MachineFunction &MF = DAG.getMachineFunction();
440 const SIRegisterInfo *TRI =
441 static_cast<const SIRegisterInfo*>(Subtarget->getRegisterInfo());
442 unsigned InputPtrReg = TRI->getPreloadedValue(MF, SIRegisterInfo::INPUT_PTR);
444 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
446 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
447 MVT PtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS);
448 PointerType *PtrTy = PointerType::get(Ty, AMDGPUAS::CONSTANT_ADDRESS);
449 SDValue BasePtr = DAG.getCopyFromReg(Chain, SL,
450 MRI.getLiveInVirtReg(InputPtrReg), PtrVT);
451 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
452 DAG.getConstant(Offset, SL, PtrVT));
453 SDValue PtrOffset = DAG.getUNDEF(PtrVT);
454 MachinePointerInfo PtrInfo(UndefValue::get(PtrTy));
456 unsigned Align = DL.getABITypeAlignment(Ty);
458 if (VT != MemVT && VT.isFloatingPoint()) {
459 // Do an integer load and convert.
460 // FIXME: This is mostly because load legalization after type legalization
461 // doesn't handle FP extloads.
462 assert(VT.getScalarType() == MVT::f32 &&
463 MemVT.getScalarType() == MVT::f16);
465 EVT IVT = toIntegerVT(VT);
466 EVT MemIVT = toIntegerVT(MemVT);
467 SDValue Load = DAG.getLoad(ISD::UNINDEXED, ISD::ZEXTLOAD,
468 IVT, SL, Chain, Ptr, PtrOffset, PtrInfo, MemIVT,
470 true, // isNonTemporal
474 DAG.getNode(ISD::FP16_TO_FP, SL, VT, Load),
478 return DAG.getMergeValues(Ops, SL);
481 ISD::LoadExtType ExtTy = Signed ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
482 return DAG.getLoad(ISD::UNINDEXED, ExtTy,
483 VT, SL, Chain, Ptr, PtrOffset, PtrInfo, MemVT,
485 true, // isNonTemporal
490 SDValue SITargetLowering::LowerFormalArguments(
491 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
492 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
493 SmallVectorImpl<SDValue> &InVals) const {
494 const SIRegisterInfo *TRI =
495 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
497 MachineFunction &MF = DAG.getMachineFunction();
498 FunctionType *FType = MF.getFunction()->getFunctionType();
499 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
501 assert(CallConv == CallingConv::C);
503 SmallVector<ISD::InputArg, 16> Splits;
504 BitVector Skipped(Ins.size());
506 for (unsigned i = 0, e = Ins.size(), PSInputNum = 0; i != e; ++i) {
507 const ISD::InputArg &Arg = Ins[i];
509 // First check if it's a PS input addr
510 if (Info->getShaderType() == ShaderType::PIXEL && !Arg.Flags.isInReg() &&
511 !Arg.Flags.isByVal()) {
513 assert((PSInputNum <= 15) && "Too many PS inputs!");
516 // We can savely skip PS inputs
522 Info->PSInputAddr |= 1 << PSInputNum++;
525 // Second split vertices into their elements
526 if (Info->getShaderType() != ShaderType::COMPUTE && Arg.VT.isVector()) {
527 ISD::InputArg NewArg = Arg;
528 NewArg.Flags.setSplit();
529 NewArg.VT = Arg.VT.getVectorElementType();
531 // We REALLY want the ORIGINAL number of vertex elements here, e.g. a
532 // three or five element vertex only needs three or five registers,
533 // NOT four or eigth.
534 Type *ParamType = FType->getParamType(Arg.getOrigArgIndex());
535 unsigned NumElements = ParamType->getVectorNumElements();
537 for (unsigned j = 0; j != NumElements; ++j) {
538 Splits.push_back(NewArg);
539 NewArg.PartOffset += NewArg.VT.getStoreSize();
542 } else if (Info->getShaderType() != ShaderType::COMPUTE) {
543 Splits.push_back(Arg);
547 SmallVector<CCValAssign, 16> ArgLocs;
548 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
551 // At least one interpolation mode must be enabled or else the GPU will hang.
552 if (Info->getShaderType() == ShaderType::PIXEL &&
553 (Info->PSInputAddr & 0x7F) == 0) {
554 Info->PSInputAddr |= 1;
555 CCInfo.AllocateReg(AMDGPU::VGPR0);
556 CCInfo.AllocateReg(AMDGPU::VGPR1);
559 // The pointer to the list of arguments is stored in SGPR0, SGPR1
560 // The pointer to the scratch buffer is stored in SGPR2, SGPR3
561 if (Info->getShaderType() == ShaderType::COMPUTE) {
562 if (Subtarget->isAmdHsaOS())
563 Info->NumUserSGPRs = 2; // FIXME: Need to support scratch buffers.
565 Info->NumUserSGPRs = 4;
567 unsigned InputPtrReg =
568 TRI->getPreloadedValue(MF, SIRegisterInfo::INPUT_PTR);
569 unsigned InputPtrRegLo =
570 TRI->getPhysRegSubReg(InputPtrReg, &AMDGPU::SReg_32RegClass, 0);
571 unsigned InputPtrRegHi =
572 TRI->getPhysRegSubReg(InputPtrReg, &AMDGPU::SReg_32RegClass, 1);
574 unsigned ScratchPtrReg =
575 TRI->getPreloadedValue(MF, SIRegisterInfo::SCRATCH_PTR);
576 unsigned ScratchPtrRegLo =
577 TRI->getPhysRegSubReg(ScratchPtrReg, &AMDGPU::SReg_32RegClass, 0);
578 unsigned ScratchPtrRegHi =
579 TRI->getPhysRegSubReg(ScratchPtrReg, &AMDGPU::SReg_32RegClass, 1);
581 CCInfo.AllocateReg(InputPtrRegLo);
582 CCInfo.AllocateReg(InputPtrRegHi);
583 CCInfo.AllocateReg(ScratchPtrRegLo);
584 CCInfo.AllocateReg(ScratchPtrRegHi);
585 MF.addLiveIn(InputPtrReg, &AMDGPU::SReg_64RegClass);
586 MF.addLiveIn(ScratchPtrReg, &AMDGPU::SReg_64RegClass);
589 if (Info->getShaderType() == ShaderType::COMPUTE) {
590 getOriginalFunctionArgs(DAG, DAG.getMachineFunction().getFunction(), Ins,
594 AnalyzeFormalArguments(CCInfo, Splits);
596 SmallVector<SDValue, 16> Chains;
598 for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
600 const ISD::InputArg &Arg = Ins[i];
602 InVals.push_back(DAG.getUNDEF(Arg.VT));
606 CCValAssign &VA = ArgLocs[ArgIdx++];
607 MVT VT = VA.getLocVT();
611 EVT MemVT = Splits[i].VT;
612 const unsigned Offset = Subtarget->getExplicitKernelArgOffset() +
613 VA.getLocMemOffset();
614 // The first 36 bytes of the input buffer contains information about
615 // thread group and global sizes.
616 SDValue Arg = LowerParameter(DAG, VT, MemVT, DL, Chain,
617 Offset, Ins[i].Flags.isSExt());
618 Chains.push_back(Arg.getValue(1));
620 const PointerType *ParamTy =
621 dyn_cast<PointerType>(FType->getParamType(Ins[i].getOrigArgIndex()));
622 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS &&
623 ParamTy && ParamTy->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS) {
624 // On SI local pointers are just offsets into LDS, so they are always
625 // less than 16-bits. On CI and newer they could potentially be
626 // real pointers, so we can't guarantee their size.
627 Arg = DAG.getNode(ISD::AssertZext, DL, Arg.getValueType(), Arg,
628 DAG.getValueType(MVT::i16));
631 InVals.push_back(Arg);
632 Info->ABIArgOffset = Offset + MemVT.getStoreSize();
635 assert(VA.isRegLoc() && "Parameter must be in a register!");
637 unsigned Reg = VA.getLocReg();
639 if (VT == MVT::i64) {
640 // For now assume it is a pointer
641 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
642 &AMDGPU::SReg_64RegClass);
643 Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass);
644 SDValue Copy = DAG.getCopyFromReg(Chain, DL, Reg, VT);
645 InVals.push_back(Copy);
649 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
651 Reg = MF.addLiveIn(Reg, RC);
652 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
654 if (Arg.VT.isVector()) {
656 // Build a vector from the registers
657 Type *ParamType = FType->getParamType(Arg.getOrigArgIndex());
658 unsigned NumElements = ParamType->getVectorNumElements();
660 SmallVector<SDValue, 4> Regs;
662 for (unsigned j = 1; j != NumElements; ++j) {
663 Reg = ArgLocs[ArgIdx++].getLocReg();
664 Reg = MF.addLiveIn(Reg, RC);
666 SDValue Copy = DAG.getCopyFromReg(Chain, DL, Reg, VT);
667 Regs.push_back(Copy);
670 // Fill up the missing vector elements
671 NumElements = Arg.VT.getVectorNumElements() - NumElements;
672 Regs.append(NumElements, DAG.getUNDEF(VT));
674 InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT, Regs));
678 InVals.push_back(Val);
681 if (Info->getShaderType() != ShaderType::COMPUTE) {
682 unsigned ScratchIdx = CCInfo.getFirstUnallocated(ArrayRef<MCPhysReg>(
683 AMDGPU::SGPR_32RegClass.begin(), AMDGPU::SGPR_32RegClass.getNumRegs()));
684 Info->ScratchOffsetReg = AMDGPU::SGPR_32RegClass.getRegister(ScratchIdx);
690 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
693 MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
694 MachineInstr * MI, MachineBasicBlock * BB) const {
696 MachineBasicBlock::iterator I = *MI;
697 const SIInstrInfo *TII =
698 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
700 switch (MI->getOpcode()) {
702 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
705 case AMDGPU::SI_RegisterStorePseudo: {
706 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
707 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
708 MachineInstrBuilder MIB =
709 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::SI_RegisterStore),
711 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
712 MIB.addOperand(MI->getOperand(i));
714 MI->eraseFromParent();
721 bool SITargetLowering::enableAggressiveFMAFusion(EVT VT) const {
722 // This currently forces unfolding various combinations of fsub into fma with
723 // free fneg'd operands. As long as we have fast FMA (controlled by
724 // isFMAFasterThanFMulAndFAdd), we should perform these.
726 // When fma is quarter rate, for f64 where add / sub are at best half rate,
727 // most of these combines appear to be cycle neutral but save on instruction
728 // count / code size.
732 EVT SITargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx,
734 if (!VT.isVector()) {
737 return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
740 MVT SITargetLowering::getScalarShiftAmountTy(const DataLayout &, EVT) const {
744 // Answering this is somewhat tricky and depends on the specific device which
745 // have different rates for fma or all f64 operations.
747 // v_fma_f64 and v_mul_f64 always take the same number of cycles as each other
748 // regardless of which device (although the number of cycles differs between
749 // devices), so it is always profitable for f64.
751 // v_fma_f32 takes 4 or 16 cycles depending on the device, so it is profitable
752 // only on full rate devices. Normally, we should prefer selecting v_mad_f32
753 // which we can always do even without fused FP ops since it returns the same
754 // result as the separate operations and since it is always full
755 // rate. Therefore, we lie and report that it is not faster for f32. v_mad_f32
756 // however does not support denormals, so we do report fma as faster if we have
757 // a fast fma device and require denormals.
759 bool SITargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
760 VT = VT.getScalarType();
765 switch (VT.getSimpleVT().SimpleTy) {
767 // This is as fast on some subtargets. However, we always have full rate f32
768 // mad available which returns the same result as the separate operations
769 // which we should prefer over fma. We can't use this if we want to support
770 // denormals, so only report this in these cases.
771 return Subtarget->hasFP32Denormals() && Subtarget->hasFastFMAF32();
781 //===----------------------------------------------------------------------===//
782 // Custom DAG Lowering Operations
783 //===----------------------------------------------------------------------===//
785 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
786 switch (Op.getOpcode()) {
787 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
788 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
789 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
791 SDValue Result = LowerLOAD(Op, DAG);
792 assert((!Result.getNode() ||
793 Result.getNode()->getNumValues() == 2) &&
794 "Load should return a value and a chain");
800 return LowerTrig(Op, DAG);
801 case ISD::SELECT: return LowerSELECT(Op, DAG);
802 case ISD::FDIV: return LowerFDIV(Op, DAG);
803 case ISD::STORE: return LowerSTORE(Op, DAG);
804 case ISD::GlobalAddress: {
805 MachineFunction &MF = DAG.getMachineFunction();
806 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
807 return LowerGlobalAddress(MFI, Op, DAG);
809 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
810 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
815 /// \brief Helper function for LowerBRCOND
816 static SDNode *findUser(SDValue Value, unsigned Opcode) {
818 SDNode *Parent = Value.getNode();
819 for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
822 if (I.getUse().get() != Value)
825 if (I->getOpcode() == Opcode)
831 SDValue SITargetLowering::LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const {
834 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Op);
835 unsigned FrameIndex = FINode->getIndex();
837 // A FrameIndex node represents a 32-bit offset into scratch memory. If
838 // the high bit of a frame index offset were to be set, this would mean
839 // that it represented an offset of ~2GB * 64 = ~128GB from the start of the
840 // scratch buffer, with 64 being the number of threads per wave.
842 // If we know the machine uses less than 128GB of scratch, then we can
843 // amrk the high bit of the FrameIndex node as known zero,
844 // which is important, because it means in most situations we can
845 // prove that values derived from FrameIndex nodes are non-negative.
846 // This enables us to take advantage of more addressing modes when
847 // accessing scratch buffers, since for scratch reads/writes, the register
848 // offset must always be positive.
850 SDValue TFI = DAG.getTargetFrameIndex(FrameIndex, MVT::i32);
851 if (Subtarget->enableHugeScratchBuffer())
854 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, TFI,
855 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), 31)));
858 /// This transforms the control flow intrinsics to get the branch destination as
859 /// last parameter, also switches branch target with BR if the need arise
860 SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
861 SelectionDAG &DAG) const {
865 SDNode *Intr = BRCOND.getOperand(1).getNode();
866 SDValue Target = BRCOND.getOperand(2);
867 SDNode *BR = nullptr;
869 if (Intr->getOpcode() == ISD::SETCC) {
870 // As long as we negate the condition everything is fine
871 SDNode *SetCC = Intr;
872 assert(SetCC->getConstantOperandVal(1) == 1);
873 assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
875 Intr = SetCC->getOperand(0).getNode();
878 // Get the target from BR if we don't negate the condition
879 BR = findUser(BRCOND, ISD::BR);
880 Target = BR->getOperand(1);
883 assert(Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN);
885 // Build the result and
886 ArrayRef<EVT> Res(Intr->value_begin() + 1, Intr->value_end());
888 // operands of the new intrinsic call
889 SmallVector<SDValue, 4> Ops;
890 Ops.push_back(BRCOND.getOperand(0));
891 Ops.append(Intr->op_begin() + 1, Intr->op_end());
892 Ops.push_back(Target);
894 // build the new intrinsic call
895 SDNode *Result = DAG.getNode(
896 Res.size() > 1 ? ISD::INTRINSIC_W_CHAIN : ISD::INTRINSIC_VOID, DL,
897 DAG.getVTList(Res), Ops).getNode();
900 // Give the branch instruction our target
905 SDValue NewBR = DAG.getNode(ISD::BR, DL, BR->getVTList(), Ops);
906 DAG.ReplaceAllUsesWith(BR, NewBR.getNode());
907 BR = NewBR.getNode();
910 SDValue Chain = SDValue(Result, Result->getNumValues() - 1);
912 // Copy the intrinsic results to registers
913 for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
914 SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
918 Chain = DAG.getCopyToReg(
920 CopyToReg->getOperand(1),
921 SDValue(Result, i - 1),
924 DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0));
927 // Remove the old intrinsic from the chain
928 DAG.ReplaceAllUsesOfValueWith(
929 SDValue(Intr, Intr->getNumValues() - 1),
930 Intr->getOperand(0));
935 SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
937 SelectionDAG &DAG) const {
938 GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Op);
940 if (GSD->getAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
941 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG);
944 const GlobalValue *GV = GSD->getGlobal();
945 MVT PtrVT = getPointerTy(DAG.getDataLayout(), GSD->getAddressSpace());
947 SDValue Ptr = DAG.getNode(AMDGPUISD::CONST_DATA_PTR, DL, PtrVT);
948 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32);
950 SDValue PtrLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Ptr,
951 DAG.getConstant(0, DL, MVT::i32));
952 SDValue PtrHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Ptr,
953 DAG.getConstant(1, DL, MVT::i32));
955 SDValue Lo = DAG.getNode(ISD::ADDC, DL, DAG.getVTList(MVT::i32, MVT::Glue),
957 SDValue Hi = DAG.getNode(ISD::ADDE, DL, DAG.getVTList(MVT::i32, MVT::Glue),
958 PtrHi, DAG.getConstant(0, DL, MVT::i32),
959 SDValue(Lo.getNode(), 1));
960 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
963 SDValue SITargetLowering::copyToM0(SelectionDAG &DAG, SDValue Chain, SDLoc DL,
965 // We can't use CopyToReg, because MachineCSE won't combine COPY instructions,
966 // so we will end up with redundant moves to m0.
968 // We can't use S_MOV_B32, because there is no way to specify m0 as the
969 // destination register.
971 // We have to use them both. Machine cse will combine all the S_MOV_B32
972 // instructions and the register coalescer eliminate the extra copies.
973 SDNode *M0 = DAG.getMachineNode(AMDGPU::S_MOV_B32, DL, V.getValueType(), V);
974 return DAG.getCopyToReg(Chain, DL, DAG.getRegister(AMDGPU::M0, MVT::i32),
975 SDValue(M0, 0), SDValue()); // Glue
976 // A Null SDValue creates
980 SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
981 SelectionDAG &DAG) const {
982 MachineFunction &MF = DAG.getMachineFunction();
983 auto MFI = MF.getInfo<SIMachineFunctionInfo>();
984 const SIRegisterInfo *TRI =
985 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
987 EVT VT = Op.getValueType();
989 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
991 switch (IntrinsicID) {
992 case Intrinsic::r600_read_ngroups_x:
993 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
994 SI::KernelInputOffsets::NGROUPS_X, false);
995 case Intrinsic::r600_read_ngroups_y:
996 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
997 SI::KernelInputOffsets::NGROUPS_Y, false);
998 case Intrinsic::r600_read_ngroups_z:
999 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1000 SI::KernelInputOffsets::NGROUPS_Z, false);
1001 case Intrinsic::r600_read_global_size_x:
1002 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1003 SI::KernelInputOffsets::GLOBAL_SIZE_X, false);
1004 case Intrinsic::r600_read_global_size_y:
1005 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1006 SI::KernelInputOffsets::GLOBAL_SIZE_Y, false);
1007 case Intrinsic::r600_read_global_size_z:
1008 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1009 SI::KernelInputOffsets::GLOBAL_SIZE_Z, false);
1010 case Intrinsic::r600_read_local_size_x:
1011 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1012 SI::KernelInputOffsets::LOCAL_SIZE_X, false);
1013 case Intrinsic::r600_read_local_size_y:
1014 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1015 SI::KernelInputOffsets::LOCAL_SIZE_Y, false);
1016 case Intrinsic::r600_read_local_size_z:
1017 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1018 SI::KernelInputOffsets::LOCAL_SIZE_Z, false);
1020 case Intrinsic::AMDGPU_read_workdim:
1021 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1022 getImplicitParameterOffset(MFI, GRID_DIM), false);
1024 case Intrinsic::r600_read_tgid_x:
1025 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
1026 TRI->getPreloadedValue(MF, SIRegisterInfo::TGID_X), VT);
1027 case Intrinsic::r600_read_tgid_y:
1028 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
1029 TRI->getPreloadedValue(MF, SIRegisterInfo::TGID_Y), VT);
1030 case Intrinsic::r600_read_tgid_z:
1031 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
1032 TRI->getPreloadedValue(MF, SIRegisterInfo::TGID_Z), VT);
1033 case Intrinsic::r600_read_tidig_x:
1034 return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass,
1035 TRI->getPreloadedValue(MF, SIRegisterInfo::TIDIG_X), VT);
1036 case Intrinsic::r600_read_tidig_y:
1037 return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass,
1038 TRI->getPreloadedValue(MF, SIRegisterInfo::TIDIG_Y), VT);
1039 case Intrinsic::r600_read_tidig_z:
1040 return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass,
1041 TRI->getPreloadedValue(MF, SIRegisterInfo::TIDIG_Z), VT);
1042 case AMDGPUIntrinsic::SI_load_const: {
1048 MachineMemOperand *MMO = MF.getMachineMemOperand(
1049 MachinePointerInfo(),
1050 MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant,
1051 VT.getStoreSize(), 4);
1052 return DAG.getMemIntrinsicNode(AMDGPUISD::LOAD_CONSTANT, DL,
1053 Op->getVTList(), Ops, VT, MMO);
1055 case AMDGPUIntrinsic::SI_sample:
1056 return LowerSampleIntrinsic(AMDGPUISD::SAMPLE, Op, DAG);
1057 case AMDGPUIntrinsic::SI_sampleb:
1058 return LowerSampleIntrinsic(AMDGPUISD::SAMPLEB, Op, DAG);
1059 case AMDGPUIntrinsic::SI_sampled:
1060 return LowerSampleIntrinsic(AMDGPUISD::SAMPLED, Op, DAG);
1061 case AMDGPUIntrinsic::SI_samplel:
1062 return LowerSampleIntrinsic(AMDGPUISD::SAMPLEL, Op, DAG);
1063 case AMDGPUIntrinsic::SI_vs_load_input:
1064 return DAG.getNode(AMDGPUISD::LOAD_INPUT, DL, VT,
1069 case AMDGPUIntrinsic::AMDGPU_fract:
1070 case AMDGPUIntrinsic::AMDIL_fraction: // Legacy name.
1071 return DAG.getNode(ISD::FSUB, DL, VT, Op.getOperand(1),
1072 DAG.getNode(ISD::FFLOOR, DL, VT, Op.getOperand(1)));
1073 case AMDGPUIntrinsic::SI_fs_constant: {
1074 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(3));
1075 SDValue Glue = M0.getValue(1);
1076 return DAG.getNode(AMDGPUISD::INTERP_MOV, DL, MVT::f32,
1077 DAG.getConstant(2, DL, MVT::i32), // P0
1078 Op.getOperand(1), Op.getOperand(2), Glue);
1080 case AMDGPUIntrinsic::SI_fs_interp: {
1081 SDValue IJ = Op.getOperand(4);
1082 SDValue I = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, IJ,
1083 DAG.getConstant(0, DL, MVT::i32));
1084 SDValue J = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, IJ,
1085 DAG.getConstant(1, DL, MVT::i32));
1086 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(3));
1087 SDValue Glue = M0.getValue(1);
1088 SDValue P1 = DAG.getNode(AMDGPUISD::INTERP_P1, DL,
1089 DAG.getVTList(MVT::f32, MVT::Glue),
1090 I, Op.getOperand(1), Op.getOperand(2), Glue);
1091 Glue = SDValue(P1.getNode(), 1);
1092 return DAG.getNode(AMDGPUISD::INTERP_P2, DL, MVT::f32, P1, J,
1093 Op.getOperand(1), Op.getOperand(2), Glue);
1096 return AMDGPUTargetLowering::LowerOperation(Op, DAG);
1100 SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
1101 SelectionDAG &DAG) const {
1102 MachineFunction &MF = DAG.getMachineFunction();
1104 SDValue Chain = Op.getOperand(0);
1105 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1107 switch (IntrinsicID) {
1108 case AMDGPUIntrinsic::SI_sendmsg: {
1109 Chain = copyToM0(DAG, Chain, DL, Op.getOperand(3));
1110 SDValue Glue = Chain.getValue(1);
1111 return DAG.getNode(AMDGPUISD::SENDMSG, DL, MVT::Other, Chain,
1112 Op.getOperand(2), Glue);
1114 case AMDGPUIntrinsic::SI_tbuffer_store: {
1132 EVT VT = Op.getOperand(3).getValueType();
1134 MachineMemOperand *MMO = MF.getMachineMemOperand(
1135 MachinePointerInfo(),
1136 MachineMemOperand::MOStore,
1137 VT.getStoreSize(), 4);
1138 return DAG.getMemIntrinsicNode(AMDGPUISD::TBUFFER_STORE_FORMAT, DL,
1139 Op->getVTList(), Ops, VT, MMO);
1146 SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1148 LoadSDNode *Load = cast<LoadSDNode>(Op);
1150 if (Op.getValueType().isVector()) {
1151 assert(Op.getValueType().getVectorElementType() == MVT::i32 &&
1152 "Custom lowering for non-i32 vectors hasn't been implemented.");
1153 unsigned NumElements = Op.getValueType().getVectorNumElements();
1154 assert(NumElements != 2 && "v2 loads are supported for all address spaces.");
1155 switch (Load->getAddressSpace()) {
1157 case AMDGPUAS::GLOBAL_ADDRESS:
1158 case AMDGPUAS::PRIVATE_ADDRESS:
1159 // v4 loads are supported for private and global memory.
1160 if (NumElements <= 4)
1163 case AMDGPUAS::LOCAL_ADDRESS:
1164 return ScalarizeVectorLoad(Op, DAG);
1168 return AMDGPUTargetLowering::LowerLOAD(Op, DAG);
1171 SDValue SITargetLowering::LowerSampleIntrinsic(unsigned Opcode,
1173 SelectionDAG &DAG) const {
1174 return DAG.getNode(Opcode, SDLoc(Op), Op.getValueType(), Op.getOperand(1),
1180 SDValue SITargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
1181 if (Op.getValueType() != MVT::i64)
1185 SDValue Cond = Op.getOperand(0);
1187 SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
1188 SDValue One = DAG.getConstant(1, DL, MVT::i32);
1190 SDValue LHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(1));
1191 SDValue RHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(2));
1193 SDValue Lo0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, Zero);
1194 SDValue Lo1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, Zero);
1196 SDValue Lo = DAG.getSelect(DL, MVT::i32, Cond, Lo0, Lo1);
1198 SDValue Hi0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, One);
1199 SDValue Hi1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, One);
1201 SDValue Hi = DAG.getSelect(DL, MVT::i32, Cond, Hi0, Hi1);
1203 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2i32, Lo, Hi);
1204 return DAG.getNode(ISD::BITCAST, DL, MVT::i64, Res);
1207 // Catch division cases where we can use shortcuts with rcp and rsq
1209 SDValue SITargetLowering::LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const {
1211 SDValue LHS = Op.getOperand(0);
1212 SDValue RHS = Op.getOperand(1);
1213 EVT VT = Op.getValueType();
1214 bool Unsafe = DAG.getTarget().Options.UnsafeFPMath;
1216 if (const ConstantFPSDNode *CLHS = dyn_cast<ConstantFPSDNode>(LHS)) {
1217 if ((Unsafe || (VT == MVT::f32 && !Subtarget->hasFP32Denormals())) &&
1218 CLHS->isExactlyValue(1.0)) {
1219 // v_rcp_f32 and v_rsq_f32 do not support denormals, and according to
1220 // the CI documentation has a worst case error of 1 ulp.
1221 // OpenCL requires <= 2.5 ulp for 1.0 / x, so it should always be OK to
1222 // use it as long as we aren't trying to use denormals.
1224 // 1.0 / sqrt(x) -> rsq(x)
1226 // XXX - Is UnsafeFPMath sufficient to do this for f64? The maximum ULP
1227 // error seems really high at 2^29 ULP.
1228 if (RHS.getOpcode() == ISD::FSQRT)
1229 return DAG.getNode(AMDGPUISD::RSQ, SL, VT, RHS.getOperand(0));
1231 // 1.0 / x -> rcp(x)
1232 return DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
1237 // Turn into multiply by the reciprocal.
1238 // x / y -> x * (1.0 / y)
1239 SDValue Recip = DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
1240 return DAG.getNode(ISD::FMUL, SL, VT, LHS, Recip);
1246 SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const {
1247 SDValue FastLowered = LowerFastFDIV(Op, DAG);
1248 if (FastLowered.getNode())
1251 // This uses v_rcp_f32 which does not handle denormals. Let this hit a
1252 // selection error for now rather than do something incorrect.
1253 if (Subtarget->hasFP32Denormals())
1257 SDValue LHS = Op.getOperand(0);
1258 SDValue RHS = Op.getOperand(1);
1260 SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS);
1262 const APFloat K0Val(BitsToFloat(0x6f800000));
1263 const SDValue K0 = DAG.getConstantFP(K0Val, SL, MVT::f32);
1265 const APFloat K1Val(BitsToFloat(0x2f800000));
1266 const SDValue K1 = DAG.getConstantFP(K1Val, SL, MVT::f32);
1268 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32);
1271 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f32);
1273 SDValue r2 = DAG.getSetCC(SL, SetCCVT, r1, K0, ISD::SETOGT);
1275 SDValue r3 = DAG.getNode(ISD::SELECT, SL, MVT::f32, r2, K1, One);
1277 r1 = DAG.getNode(ISD::FMUL, SL, MVT::f32, RHS, r3);
1279 SDValue r0 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, r1);
1281 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, LHS, r0);
1283 return DAG.getNode(ISD::FMUL, SL, MVT::f32, r3, Mul);
1286 SDValue SITargetLowering::LowerFDIV64(SDValue Op, SelectionDAG &DAG) const {
1287 if (DAG.getTarget().Options.UnsafeFPMath)
1288 return LowerFastFDIV(Op, DAG);
1291 SDValue X = Op.getOperand(0);
1292 SDValue Y = Op.getOperand(1);
1294 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64);
1296 SDVTList ScaleVT = DAG.getVTList(MVT::f64, MVT::i1);
1298 SDValue DivScale0 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, Y, Y, X);
1300 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f64, DivScale0);
1302 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f64, DivScale0);
1304 SDValue Fma0 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Rcp, One);
1306 SDValue Fma1 = DAG.getNode(ISD::FMA, SL, MVT::f64, Rcp, Fma0, Rcp);
1308 SDValue Fma2 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Fma1, One);
1310 SDValue DivScale1 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, X, Y, X);
1312 SDValue Fma3 = DAG.getNode(ISD::FMA, SL, MVT::f64, Fma1, Fma2, Fma1);
1313 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, DivScale1, Fma3);
1315 SDValue Fma4 = DAG.getNode(ISD::FMA, SL, MVT::f64,
1316 NegDivScale0, Mul, DivScale1);
1320 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS) {
1321 // Workaround a hardware bug on SI where the condition output from div_scale
1324 const SDValue Hi = DAG.getConstant(1, SL, MVT::i32);
1326 // Figure out if the scale to use for div_fmas.
1327 SDValue NumBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
1328 SDValue DenBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Y);
1329 SDValue Scale0BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale0);
1330 SDValue Scale1BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale1);
1332 SDValue NumHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, NumBC, Hi);
1333 SDValue DenHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, DenBC, Hi);
1336 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Scale0BC, Hi);
1338 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Scale1BC, Hi);
1340 SDValue CmpDen = DAG.getSetCC(SL, MVT::i1, DenHi, Scale0Hi, ISD::SETEQ);
1341 SDValue CmpNum = DAG.getSetCC(SL, MVT::i1, NumHi, Scale1Hi, ISD::SETEQ);
1342 Scale = DAG.getNode(ISD::XOR, SL, MVT::i1, CmpNum, CmpDen);
1344 Scale = DivScale1.getValue(1);
1347 SDValue Fmas = DAG.getNode(AMDGPUISD::DIV_FMAS, SL, MVT::f64,
1348 Fma4, Fma3, Mul, Scale);
1350 return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f64, Fmas, Y, X);
1353 SDValue SITargetLowering::LowerFDIV(SDValue Op, SelectionDAG &DAG) const {
1354 EVT VT = Op.getValueType();
1357 return LowerFDIV32(Op, DAG);
1360 return LowerFDIV64(Op, DAG);
1362 llvm_unreachable("Unexpected type for fdiv");
1365 SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1367 StoreSDNode *Store = cast<StoreSDNode>(Op);
1368 EVT VT = Store->getMemoryVT();
1370 // These stores are legal.
1371 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) {
1372 if (VT.isVector() && VT.getVectorNumElements() > 4)
1373 return ScalarizeVectorStore(Op, DAG);
1377 SDValue Ret = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
1381 if (VT.isVector() && VT.getVectorNumElements() >= 8)
1382 return ScalarizeVectorStore(Op, DAG);
1385 return DAG.getTruncStore(Store->getChain(), DL,
1386 DAG.getSExtOrTrunc(Store->getValue(), DL, MVT::i32),
1387 Store->getBasePtr(), MVT::i1, Store->getMemOperand());
1392 SDValue SITargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
1394 EVT VT = Op.getValueType();
1395 SDValue Arg = Op.getOperand(0);
1396 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, DL, VT,
1397 DAG.getNode(ISD::FMUL, DL, VT, Arg,
1398 DAG.getConstantFP(0.5/M_PI, DL,
1401 switch (Op.getOpcode()) {
1403 return DAG.getNode(AMDGPUISD::COS_HW, SDLoc(Op), VT, FractPart);
1405 return DAG.getNode(AMDGPUISD::SIN_HW, SDLoc(Op), VT, FractPart);
1407 llvm_unreachable("Wrong trig opcode");
1411 //===----------------------------------------------------------------------===//
1412 // Custom DAG optimizations
1413 //===----------------------------------------------------------------------===//
1415 SDValue SITargetLowering::performUCharToFloatCombine(SDNode *N,
1416 DAGCombinerInfo &DCI) const {
1417 EVT VT = N->getValueType(0);
1418 EVT ScalarVT = VT.getScalarType();
1419 if (ScalarVT != MVT::f32)
1422 SelectionDAG &DAG = DCI.DAG;
1425 SDValue Src = N->getOperand(0);
1426 EVT SrcVT = Src.getValueType();
1428 // TODO: We could try to match extracting the higher bytes, which would be
1429 // easier if i8 vectors weren't promoted to i32 vectors, particularly after
1430 // types are legalized. v4i8 -> v4f32 is probably the only case to worry
1431 // about in practice.
1432 if (DCI.isAfterLegalizeVectorOps() && SrcVT == MVT::i32) {
1433 if (DAG.MaskedValueIsZero(Src, APInt::getHighBitsSet(32, 24))) {
1434 SDValue Cvt = DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Src);
1435 DCI.AddToWorklist(Cvt.getNode());
1440 // We are primarily trying to catch operations on illegal vector types
1441 // before they are expanded.
1442 // For scalars, we can use the more flexible method of checking masked bits
1443 // after legalization.
1444 if (!DCI.isBeforeLegalize() ||
1445 !SrcVT.isVector() ||
1446 SrcVT.getVectorElementType() != MVT::i8) {
1450 assert(DCI.isBeforeLegalize() && "Unexpected legal type");
1452 // Weird sized vectors are a pain to handle, but we know 3 is really the same
1454 unsigned NElts = SrcVT.getVectorNumElements();
1455 if (!SrcVT.isSimple() && NElts != 3)
1458 // Handle v4i8 -> v4f32 extload. Replace the v4i8 with a legal i32 load to
1459 // prevent a mess from expanding to v4i32 and repacking.
1460 if (ISD::isNormalLoad(Src.getNode()) && Src.hasOneUse()) {
1461 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), SrcVT);
1462 EVT RegVT = getEquivalentLoadRegType(*DAG.getContext(), SrcVT);
1463 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f32, NElts);
1464 LoadSDNode *Load = cast<LoadSDNode>(Src);
1466 unsigned AS = Load->getAddressSpace();
1467 unsigned Align = Load->getAlignment();
1468 Type *Ty = LoadVT.getTypeForEVT(*DAG.getContext());
1469 unsigned ABIAlignment = DAG.getDataLayout().getABITypeAlignment(Ty);
1471 // Don't try to replace the load if we have to expand it due to alignment
1472 // problems. Otherwise we will end up scalarizing the load, and trying to
1473 // repack into the vector for no real reason.
1474 if (Align < ABIAlignment &&
1475 !allowsMisalignedMemoryAccesses(LoadVT, AS, Align, nullptr)) {
1479 SDValue NewLoad = DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegVT,
1483 Load->getMemOperand());
1485 // Make sure successors of the original load stay after it by updating
1486 // them to use the new Chain.
1487 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), NewLoad.getValue(1));
1489 SmallVector<SDValue, 4> Elts;
1490 if (RegVT.isVector())
1491 DAG.ExtractVectorElements(NewLoad, Elts);
1493 Elts.push_back(NewLoad);
1495 SmallVector<SDValue, 4> Ops;
1497 unsigned EltIdx = 0;
1498 for (SDValue Elt : Elts) {
1499 unsigned ComponentsInElt = std::min(4u, NElts - 4 * EltIdx);
1500 for (unsigned I = 0; I < ComponentsInElt; ++I) {
1501 unsigned Opc = AMDGPUISD::CVT_F32_UBYTE0 + I;
1502 SDValue Cvt = DAG.getNode(Opc, DL, MVT::f32, Elt);
1503 DCI.AddToWorklist(Cvt.getNode());
1510 assert(Ops.size() == NElts);
1512 return DAG.getNode(ISD::BUILD_VECTOR, DL, FloatVT, Ops);
1518 /// \brief Return true if the given offset Size in bytes can be folded into
1519 /// the immediate offsets of a memory instruction for the given address space.
1520 static bool canFoldOffset(unsigned OffsetSize, unsigned AS,
1521 const AMDGPUSubtarget &STI) {
1523 case AMDGPUAS::GLOBAL_ADDRESS: {
1524 // MUBUF instructions a 12-bit offset in bytes.
1525 return isUInt<12>(OffsetSize);
1527 case AMDGPUAS::CONSTANT_ADDRESS: {
1528 // SMRD instructions have an 8-bit offset in dwords on SI and
1529 // a 20-bit offset in bytes on VI.
1530 if (STI.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1531 return isUInt<20>(OffsetSize);
1533 return (OffsetSize % 4 == 0) && isUInt<8>(OffsetSize / 4);
1535 case AMDGPUAS::LOCAL_ADDRESS:
1536 case AMDGPUAS::REGION_ADDRESS: {
1537 // The single offset versions have a 16-bit offset in bytes.
1538 return isUInt<16>(OffsetSize);
1540 case AMDGPUAS::PRIVATE_ADDRESS:
1541 // Indirect register addressing does not use any offsets.
1547 // (shl (add x, c1), c2) -> add (shl x, c2), (shl c1, c2)
1549 // This is a variant of
1550 // (mul (add x, c1), c2) -> add (mul x, c2), (mul c1, c2),
1552 // The normal DAG combiner will do this, but only if the add has one use since
1553 // that would increase the number of instructions.
1555 // This prevents us from seeing a constant offset that can be folded into a
1556 // memory instruction's addressing mode. If we know the resulting add offset of
1557 // a pointer can be folded into an addressing offset, we can replace the pointer
1558 // operand with the add of new constant offset. This eliminates one of the uses,
1559 // and may allow the remaining use to also be simplified.
1561 SDValue SITargetLowering::performSHLPtrCombine(SDNode *N,
1563 DAGCombinerInfo &DCI) const {
1564 SDValue N0 = N->getOperand(0);
1565 SDValue N1 = N->getOperand(1);
1567 if (N0.getOpcode() != ISD::ADD)
1570 const ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(N1);
1574 const ConstantSDNode *CAdd = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1578 // If the resulting offset is too large, we can't fold it into the addressing
1580 APInt Offset = CAdd->getAPIntValue() << CN1->getAPIntValue();
1581 if (!canFoldOffset(Offset.getZExtValue(), AddrSpace, *Subtarget))
1584 SelectionDAG &DAG = DCI.DAG;
1586 EVT VT = N->getValueType(0);
1588 SDValue ShlX = DAG.getNode(ISD::SHL, SL, VT, N0.getOperand(0), N1);
1589 SDValue COffset = DAG.getConstant(Offset, SL, MVT::i32);
1591 return DAG.getNode(ISD::ADD, SL, VT, ShlX, COffset);
1594 SDValue SITargetLowering::performAndCombine(SDNode *N,
1595 DAGCombinerInfo &DCI) const {
1596 if (DCI.isBeforeLegalize())
1599 SelectionDAG &DAG = DCI.DAG;
1601 // (and (fcmp ord x, x), (fcmp une (fabs x), inf)) ->
1602 // fp_class x, ~(s_nan | q_nan | n_infinity | p_infinity)
1603 SDValue LHS = N->getOperand(0);
1604 SDValue RHS = N->getOperand(1);
1606 if (LHS.getOpcode() == ISD::SETCC &&
1607 RHS.getOpcode() == ISD::SETCC) {
1608 ISD::CondCode LCC = cast<CondCodeSDNode>(LHS.getOperand(2))->get();
1609 ISD::CondCode RCC = cast<CondCodeSDNode>(RHS.getOperand(2))->get();
1611 SDValue X = LHS.getOperand(0);
1612 SDValue Y = RHS.getOperand(0);
1613 if (Y.getOpcode() != ISD::FABS || Y.getOperand(0) != X)
1616 if (LCC == ISD::SETO) {
1617 if (X != LHS.getOperand(1))
1620 if (RCC == ISD::SETUNE) {
1621 const ConstantFPSDNode *C1 = dyn_cast<ConstantFPSDNode>(RHS.getOperand(1));
1622 if (!C1 || !C1->isInfinity() || C1->isNegative())
1625 const uint32_t Mask = SIInstrFlags::N_NORMAL |
1626 SIInstrFlags::N_SUBNORMAL |
1627 SIInstrFlags::N_ZERO |
1628 SIInstrFlags::P_ZERO |
1629 SIInstrFlags::P_SUBNORMAL |
1630 SIInstrFlags::P_NORMAL;
1632 static_assert(((~(SIInstrFlags::S_NAN |
1633 SIInstrFlags::Q_NAN |
1634 SIInstrFlags::N_INFINITY |
1635 SIInstrFlags::P_INFINITY)) & 0x3ff) == Mask,
1639 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, MVT::i1,
1640 X, DAG.getConstant(Mask, DL, MVT::i32));
1648 SDValue SITargetLowering::performOrCombine(SDNode *N,
1649 DAGCombinerInfo &DCI) const {
1650 SelectionDAG &DAG = DCI.DAG;
1651 SDValue LHS = N->getOperand(0);
1652 SDValue RHS = N->getOperand(1);
1654 // or (fp_class x, c1), (fp_class x, c2) -> fp_class x, (c1 | c2)
1655 if (LHS.getOpcode() == AMDGPUISD::FP_CLASS &&
1656 RHS.getOpcode() == AMDGPUISD::FP_CLASS) {
1657 SDValue Src = LHS.getOperand(0);
1658 if (Src != RHS.getOperand(0))
1661 const ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(LHS.getOperand(1));
1662 const ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(RHS.getOperand(1));
1666 // Only 10 bits are used.
1667 static const uint32_t MaxMask = 0x3ff;
1669 uint32_t NewMask = (CLHS->getZExtValue() | CRHS->getZExtValue()) & MaxMask;
1671 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, MVT::i1,
1672 Src, DAG.getConstant(NewMask, DL, MVT::i32));
1678 SDValue SITargetLowering::performClassCombine(SDNode *N,
1679 DAGCombinerInfo &DCI) const {
1680 SelectionDAG &DAG = DCI.DAG;
1681 SDValue Mask = N->getOperand(1);
1683 // fp_class x, 0 -> false
1684 if (const ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(Mask)) {
1685 if (CMask->isNullValue())
1686 return DAG.getConstant(0, SDLoc(N), MVT::i1);
1692 static unsigned minMaxOpcToMin3Max3Opc(unsigned Opc) {
1695 return AMDGPUISD::FMAX3;
1697 return AMDGPUISD::SMAX3;
1699 return AMDGPUISD::UMAX3;
1701 return AMDGPUISD::FMIN3;
1703 return AMDGPUISD::SMIN3;
1705 return AMDGPUISD::UMIN3;
1707 llvm_unreachable("Not a min/max opcode");
1711 SDValue SITargetLowering::performMin3Max3Combine(SDNode *N,
1712 DAGCombinerInfo &DCI) const {
1713 SelectionDAG &DAG = DCI.DAG;
1715 unsigned Opc = N->getOpcode();
1716 SDValue Op0 = N->getOperand(0);
1717 SDValue Op1 = N->getOperand(1);
1719 // Only do this if the inner op has one use since this will just increases
1720 // register pressure for no benefit.
1722 // max(max(a, b), c)
1723 if (Op0.getOpcode() == Opc && Op0.hasOneUse()) {
1725 return DAG.getNode(minMaxOpcToMin3Max3Opc(Opc),
1733 // max(a, max(b, c))
1734 if (Op1.getOpcode() == Opc && Op1.hasOneUse()) {
1736 return DAG.getNode(minMaxOpcToMin3Max3Opc(Opc),
1747 SDValue SITargetLowering::performSetCCCombine(SDNode *N,
1748 DAGCombinerInfo &DCI) const {
1749 SelectionDAG &DAG = DCI.DAG;
1752 SDValue LHS = N->getOperand(0);
1753 SDValue RHS = N->getOperand(1);
1754 EVT VT = LHS.getValueType();
1756 if (VT != MVT::f32 && VT != MVT::f64)
1759 // Match isinf pattern
1760 // (fcmp oeq (fabs x), inf) -> (fp_class x, (p_infinity | n_infinity))
1761 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
1762 if (CC == ISD::SETOEQ && LHS.getOpcode() == ISD::FABS) {
1763 const ConstantFPSDNode *CRHS = dyn_cast<ConstantFPSDNode>(RHS);
1767 const APFloat &APF = CRHS->getValueAPF();
1768 if (APF.isInfinity() && !APF.isNegative()) {
1769 unsigned Mask = SIInstrFlags::P_INFINITY | SIInstrFlags::N_INFINITY;
1770 return DAG.getNode(AMDGPUISD::FP_CLASS, SL, MVT::i1, LHS.getOperand(0),
1771 DAG.getConstant(Mask, SL, MVT::i32));
1778 SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
1779 DAGCombinerInfo &DCI) const {
1780 SelectionDAG &DAG = DCI.DAG;
1783 switch (N->getOpcode()) {
1785 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1787 return performSetCCCombine(N, DCI);
1788 case ISD::FMAXNUM: // TODO: What about fmax_legacy?
1794 if (DCI.getDAGCombineLevel() >= AfterLegalizeDAG &&
1795 N->getValueType(0) != MVT::f64 &&
1796 getTargetMachine().getOptLevel() > CodeGenOpt::None)
1797 return performMin3Max3Combine(N, DCI);
1801 case AMDGPUISD::CVT_F32_UBYTE0:
1802 case AMDGPUISD::CVT_F32_UBYTE1:
1803 case AMDGPUISD::CVT_F32_UBYTE2:
1804 case AMDGPUISD::CVT_F32_UBYTE3: {
1805 unsigned Offset = N->getOpcode() - AMDGPUISD::CVT_F32_UBYTE0;
1807 SDValue Src = N->getOperand(0);
1808 APInt Demanded = APInt::getBitsSet(32, 8 * Offset, 8 * Offset + 8);
1810 APInt KnownZero, KnownOne;
1811 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1812 !DCI.isBeforeLegalizeOps());
1813 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1814 if (TLO.ShrinkDemandedConstant(Src, Demanded) ||
1815 TLI.SimplifyDemandedBits(Src, Demanded, KnownZero, KnownOne, TLO)) {
1816 DCI.CommitTargetLoweringOpt(TLO);
1822 case ISD::UINT_TO_FP: {
1823 return performUCharToFloatCombine(N, DCI);
1826 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
1829 EVT VT = N->getValueType(0);
1833 // Only do this if we are not trying to support denormals. v_mad_f32 does
1834 // not support denormals ever.
1835 if (Subtarget->hasFP32Denormals())
1838 SDValue LHS = N->getOperand(0);
1839 SDValue RHS = N->getOperand(1);
1841 // These should really be instruction patterns, but writing patterns with
1842 // source modiifiers is a pain.
1844 // fadd (fadd (a, a), b) -> mad 2.0, a, b
1845 if (LHS.getOpcode() == ISD::FADD) {
1846 SDValue A = LHS.getOperand(0);
1847 if (A == LHS.getOperand(1)) {
1848 const SDValue Two = DAG.getConstantFP(2.0, DL, MVT::f32);
1849 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, RHS);
1853 // fadd (b, fadd (a, a)) -> mad 2.0, a, b
1854 if (RHS.getOpcode() == ISD::FADD) {
1855 SDValue A = RHS.getOperand(0);
1856 if (A == RHS.getOperand(1)) {
1857 const SDValue Two = DAG.getConstantFP(2.0, DL, MVT::f32);
1858 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, LHS);
1865 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
1868 EVT VT = N->getValueType(0);
1870 // Try to get the fneg to fold into the source modifier. This undoes generic
1871 // DAG combines and folds them into the mad.
1873 // Only do this if we are not trying to support denormals. v_mad_f32 does
1874 // not support denormals ever.
1875 if (VT == MVT::f32 &&
1876 !Subtarget->hasFP32Denormals()) {
1877 SDValue LHS = N->getOperand(0);
1878 SDValue RHS = N->getOperand(1);
1879 if (LHS.getOpcode() == ISD::FADD) {
1880 // (fsub (fadd a, a), c) -> mad 2.0, a, (fneg c)
1882 SDValue A = LHS.getOperand(0);
1883 if (A == LHS.getOperand(1)) {
1884 const SDValue Two = DAG.getConstantFP(2.0, DL, MVT::f32);
1885 SDValue NegRHS = DAG.getNode(ISD::FNEG, DL, VT, RHS);
1887 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, NegRHS);
1891 if (RHS.getOpcode() == ISD::FADD) {
1892 // (fsub c, (fadd a, a)) -> mad -2.0, a, c
1894 SDValue A = RHS.getOperand(0);
1895 if (A == RHS.getOperand(1)) {
1896 const SDValue NegTwo = DAG.getConstantFP(-2.0, DL, MVT::f32);
1897 return DAG.getNode(ISD::FMAD, DL, VT, NegTwo, A, LHS);
1909 case ISD::ATOMIC_LOAD:
1910 case ISD::ATOMIC_STORE:
1911 case ISD::ATOMIC_CMP_SWAP:
1912 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
1913 case ISD::ATOMIC_SWAP:
1914 case ISD::ATOMIC_LOAD_ADD:
1915 case ISD::ATOMIC_LOAD_SUB:
1916 case ISD::ATOMIC_LOAD_AND:
1917 case ISD::ATOMIC_LOAD_OR:
1918 case ISD::ATOMIC_LOAD_XOR:
1919 case ISD::ATOMIC_LOAD_NAND:
1920 case ISD::ATOMIC_LOAD_MIN:
1921 case ISD::ATOMIC_LOAD_MAX:
1922 case ISD::ATOMIC_LOAD_UMIN:
1923 case ISD::ATOMIC_LOAD_UMAX: { // TODO: Target mem intrinsics.
1924 if (DCI.isBeforeLegalize())
1927 MemSDNode *MemNode = cast<MemSDNode>(N);
1928 SDValue Ptr = MemNode->getBasePtr();
1930 // TODO: We could also do this for multiplies.
1931 unsigned AS = MemNode->getAddressSpace();
1932 if (Ptr.getOpcode() == ISD::SHL && AS != AMDGPUAS::PRIVATE_ADDRESS) {
1933 SDValue NewPtr = performSHLPtrCombine(Ptr.getNode(), AS, DCI);
1935 SmallVector<SDValue, 8> NewOps(MemNode->op_begin(), MemNode->op_end());
1937 NewOps[N->getOpcode() == ISD::STORE ? 2 : 1] = NewPtr;
1938 return SDValue(DAG.UpdateNodeOperands(MemNode, NewOps), 0);
1944 return performAndCombine(N, DCI);
1946 return performOrCombine(N, DCI);
1947 case AMDGPUISD::FP_CLASS:
1948 return performClassCombine(N, DCI);
1950 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1953 /// \brief Analyze the possible immediate value Op
1955 /// Returns -1 if it isn't an immediate, 0 if it's and inline immediate
1956 /// and the immediate value if it's a literal immediate
1957 int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
1959 const SIInstrInfo *TII =
1960 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
1962 if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N)) {
1963 if (TII->isInlineConstant(Node->getAPIntValue()))
1966 uint64_t Val = Node->getZExtValue();
1967 return isUInt<32>(Val) ? Val : -1;
1970 if (const ConstantFPSDNode *Node = dyn_cast<ConstantFPSDNode>(N)) {
1971 if (TII->isInlineConstant(Node->getValueAPF().bitcastToAPInt()))
1974 if (Node->getValueType(0) == MVT::f32)
1975 return FloatToBits(Node->getValueAPF().convertToFloat());
1983 /// \brief Helper function for adjustWritemask
1984 static unsigned SubIdx2Lane(unsigned Idx) {
1987 case AMDGPU::sub0: return 0;
1988 case AMDGPU::sub1: return 1;
1989 case AMDGPU::sub2: return 2;
1990 case AMDGPU::sub3: return 3;
1994 /// \brief Adjust the writemask of MIMG instructions
1995 void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
1996 SelectionDAG &DAG) const {
1997 SDNode *Users[4] = { };
1999 unsigned OldDmask = Node->getConstantOperandVal(0);
2000 unsigned NewDmask = 0;
2002 // Try to figure out the used register components
2003 for (SDNode::use_iterator I = Node->use_begin(), E = Node->use_end();
2006 // Abort if we can't understand the usage
2007 if (!I->isMachineOpcode() ||
2008 I->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG)
2011 // Lane means which subreg of %VGPRa_VGPRb_VGPRc_VGPRd is used.
2012 // Note that subregs are packed, i.e. Lane==0 is the first bit set
2013 // in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit
2015 Lane = SubIdx2Lane(I->getConstantOperandVal(1));
2017 // Set which texture component corresponds to the lane.
2019 for (unsigned i = 0, Dmask = OldDmask; i <= Lane; i++) {
2021 Comp = countTrailingZeros(Dmask);
2022 Dmask &= ~(1 << Comp);
2025 // Abort if we have more than one user per component
2030 NewDmask |= 1 << Comp;
2033 // Abort if there's no change
2034 if (NewDmask == OldDmask)
2037 // Adjust the writemask in the node
2038 std::vector<SDValue> Ops;
2039 Ops.push_back(DAG.getTargetConstant(NewDmask, SDLoc(Node), MVT::i32));
2040 Ops.insert(Ops.end(), Node->op_begin() + 1, Node->op_end());
2041 Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops);
2043 // If we only got one lane, replace it with a copy
2044 // (if NewDmask has only one bit set...)
2045 if (NewDmask && (NewDmask & (NewDmask-1)) == 0) {
2046 SDValue RC = DAG.getTargetConstant(AMDGPU::VGPR_32RegClassID, SDLoc(),
2048 SDNode *Copy = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
2049 SDLoc(), Users[Lane]->getValueType(0),
2050 SDValue(Node, 0), RC);
2051 DAG.ReplaceAllUsesWith(Users[Lane], Copy);
2055 // Update the users of the node with the new indices
2056 for (unsigned i = 0, Idx = AMDGPU::sub0; i < 4; ++i) {
2058 SDNode *User = Users[i];
2062 SDValue Op = DAG.getTargetConstant(Idx, SDLoc(User), MVT::i32);
2063 DAG.UpdateNodeOperands(User, User->getOperand(0), Op);
2067 case AMDGPU::sub0: Idx = AMDGPU::sub1; break;
2068 case AMDGPU::sub1: Idx = AMDGPU::sub2; break;
2069 case AMDGPU::sub2: Idx = AMDGPU::sub3; break;
2074 static bool isFrameIndexOp(SDValue Op) {
2075 if (Op.getOpcode() == ISD::AssertZext)
2076 Op = Op.getOperand(0);
2078 return isa<FrameIndexSDNode>(Op);
2081 /// \brief Legalize target independent instructions (e.g. INSERT_SUBREG)
2082 /// with frame index operands.
2083 /// LLVM assumes that inputs are to these instructions are registers.
2084 void SITargetLowering::legalizeTargetIndependentNode(SDNode *Node,
2085 SelectionDAG &DAG) const {
2087 SmallVector<SDValue, 8> Ops;
2088 for (unsigned i = 0; i < Node->getNumOperands(); ++i) {
2089 if (!isFrameIndexOp(Node->getOperand(i))) {
2090 Ops.push_back(Node->getOperand(i));
2095 Ops.push_back(SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL,
2096 Node->getOperand(i).getValueType(),
2097 Node->getOperand(i)), 0));
2100 DAG.UpdateNodeOperands(Node, Ops);
2103 /// \brief Fold the instructions after selecting them.
2104 SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
2105 SelectionDAG &DAG) const {
2106 const SIInstrInfo *TII =
2107 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
2109 if (TII->isMIMG(Node->getMachineOpcode()))
2110 adjustWritemask(Node, DAG);
2112 if (Node->getMachineOpcode() == AMDGPU::INSERT_SUBREG ||
2113 Node->getMachineOpcode() == AMDGPU::REG_SEQUENCE) {
2114 legalizeTargetIndependentNode(Node, DAG);
2120 /// \brief Assign the register class depending on the number of
2121 /// bits set in the writemask
2122 void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
2123 SDNode *Node) const {
2124 const SIInstrInfo *TII =
2125 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
2127 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
2128 TII->legalizeOperands(MI);
2130 if (TII->isMIMG(MI->getOpcode())) {
2131 unsigned VReg = MI->getOperand(0).getReg();
2132 unsigned Writemask = MI->getOperand(1).getImm();
2133 unsigned BitsSet = 0;
2134 for (unsigned i = 0; i < 4; ++i)
2135 BitsSet += Writemask & (1 << i) ? 1 : 0;
2137 const TargetRegisterClass *RC;
2140 case 1: RC = &AMDGPU::VGPR_32RegClass; break;
2141 case 2: RC = &AMDGPU::VReg_64RegClass; break;
2142 case 3: RC = &AMDGPU::VReg_96RegClass; break;
2145 unsigned NewOpcode = TII->getMaskedMIMGOp(MI->getOpcode(), BitsSet);
2146 MI->setDesc(TII->get(NewOpcode));
2147 MRI.setRegClass(VReg, RC);
2151 // Replace unused atomics with the no return version.
2152 int NoRetAtomicOp = AMDGPU::getAtomicNoRetOp(MI->getOpcode());
2153 if (NoRetAtomicOp != -1) {
2154 if (!Node->hasAnyUseOfValue(0)) {
2155 MI->setDesc(TII->get(NoRetAtomicOp));
2156 MI->RemoveOperand(0);
2163 static SDValue buildSMovImm32(SelectionDAG &DAG, SDLoc DL, uint64_t Val) {
2164 SDValue K = DAG.getTargetConstant(Val, DL, MVT::i32);
2165 return SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, K), 0);
2168 MachineSDNode *SITargetLowering::wrapAddr64Rsrc(SelectionDAG &DAG,
2170 SDValue Ptr) const {
2171 const SIInstrInfo *TII =
2172 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
2174 // XXX - Workaround for moveToVALU not handling different register class
2175 // inserts for REG_SEQUENCE.
2177 // Build the half of the subregister with the constants.
2178 const SDValue Ops0[] = {
2179 DAG.getTargetConstant(AMDGPU::SGPR_64RegClassID, DL, MVT::i32),
2180 buildSMovImm32(DAG, DL, 0),
2181 DAG.getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
2182 buildSMovImm32(DAG, DL, TII->getDefaultRsrcDataFormat() >> 32),
2183 DAG.getTargetConstant(AMDGPU::sub1, DL, MVT::i32)
2186 SDValue SubRegHi = SDValue(DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL,
2187 MVT::v2i32, Ops0), 0);
2189 // Combine the constants and the pointer.
2190 const SDValue Ops1[] = {
2191 DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32),
2193 DAG.getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32),
2195 DAG.getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32)
2198 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops1);
2200 const SDValue Ops[] = {
2201 DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32),
2203 DAG.getTargetConstant(AMDGPU::sub0_sub1, MVT::i32),
2204 buildSMovImm32(DAG, DL, 0),
2205 DAG.getTargetConstant(AMDGPU::sub2, MVT::i32),
2206 buildSMovImm32(DAG, DL, TII->getDefaultRsrcFormat() >> 32),
2207 DAG.getTargetConstant(AMDGPU::sub3, MVT::i32)
2210 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops);
2215 /// \brief Return a resource descriptor with the 'Add TID' bit enabled
2216 /// The TID (Thread ID) is multipled by the stride value (bits [61:48]
2217 /// of the resource descriptor) to create an offset, which is added to the
2218 /// resource ponter.
2219 MachineSDNode *SITargetLowering::buildRSRC(SelectionDAG &DAG,
2222 uint32_t RsrcDword1,
2223 uint64_t RsrcDword2And3) const {
2224 SDValue PtrLo = DAG.getTargetExtractSubreg(AMDGPU::sub0, DL, MVT::i32, Ptr);
2225 SDValue PtrHi = DAG.getTargetExtractSubreg(AMDGPU::sub1, DL, MVT::i32, Ptr);
2227 PtrHi = SDValue(DAG.getMachineNode(AMDGPU::S_OR_B32, DL, MVT::i32, PtrHi,
2228 DAG.getConstant(RsrcDword1, DL, MVT::i32)),
2232 SDValue DataLo = buildSMovImm32(DAG, DL,
2233 RsrcDword2And3 & UINT64_C(0xFFFFFFFF));
2234 SDValue DataHi = buildSMovImm32(DAG, DL, RsrcDword2And3 >> 32);
2236 const SDValue Ops[] = {
2237 DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32),
2239 DAG.getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
2241 DAG.getTargetConstant(AMDGPU::sub1, DL, MVT::i32),
2243 DAG.getTargetConstant(AMDGPU::sub2, DL, MVT::i32),
2245 DAG.getTargetConstant(AMDGPU::sub3, DL, MVT::i32)
2248 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops);
2251 MachineSDNode *SITargetLowering::buildScratchRSRC(SelectionDAG &DAG,
2253 SDValue Ptr) const {
2254 const SIInstrInfo *TII =
2255 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
2256 uint64_t Rsrc = TII->getDefaultRsrcDataFormat() | AMDGPU::RSRC_TID_ENABLE |
2259 return buildRSRC(DAG, DL, Ptr, 0, Rsrc);
2262 SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2263 const TargetRegisterClass *RC,
2264 unsigned Reg, EVT VT) const {
2265 SDValue VReg = AMDGPUTargetLowering::CreateLiveInRegister(DAG, RC, Reg, VT);
2267 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(DAG.getEntryNode()),
2268 cast<RegisterSDNode>(VReg)->getReg(), VT);
2271 //===----------------------------------------------------------------------===//
2272 // SI Inline Assembly Support
2273 //===----------------------------------------------------------------------===//
2275 std::pair<unsigned, const TargetRegisterClass *>
2276 SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
2277 StringRef Constraint,
2279 if (Constraint == "r") {
2280 switch(VT.SimpleTy) {
2281 default: llvm_unreachable("Unhandled type for 'r' inline asm constraint");
2283 return std::make_pair(0U, &AMDGPU::SGPR_64RegClass);
2285 return std::make_pair(0U, &AMDGPU::SGPR_32RegClass);
2289 if (Constraint.size() > 1) {
2290 const TargetRegisterClass *RC = nullptr;
2291 if (Constraint[1] == 'v') {
2292 RC = &AMDGPU::VGPR_32RegClass;
2293 } else if (Constraint[1] == 's') {
2294 RC = &AMDGPU::SGPR_32RegClass;
2299 bool Failed = Constraint.substr(2).getAsInteger(10, Idx);
2300 if (!Failed && Idx < RC->getNumRegs())
2301 return std::make_pair(RC->getRegister(Idx), RC);
2304 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);