1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for SI
13 //===----------------------------------------------------------------------===//
17 #define _USE_MATH_DEFINES
21 #include "SIISelLowering.h"
23 #include "AMDGPUDiagnosticInfoUnsupported.h"
24 #include "AMDGPUIntrinsicInfo.h"
25 #include "AMDGPUSubtarget.h"
26 #include "SIInstrInfo.h"
27 #include "SIMachineFunctionInfo.h"
28 #include "SIRegisterInfo.h"
29 #include "llvm/ADT/BitVector.h"
30 #include "llvm/CodeGen/CallingConvLower.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/SelectionDAG.h"
34 #include "llvm/IR/Function.h"
35 #include "llvm/ADT/SmallString.h"
39 SITargetLowering::SITargetLowering(TargetMachine &TM,
40 const AMDGPUSubtarget &STI)
41 : AMDGPUTargetLowering(TM, STI) {
42 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
43 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
45 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
46 addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass);
48 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
49 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass);
51 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);
52 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
53 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
55 addRegisterClass(MVT::v2i64, &AMDGPU::SReg_128RegClass);
56 addRegisterClass(MVT::v2f64, &AMDGPU::SReg_128RegClass);
58 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
59 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
61 addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass);
62 addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
64 addRegisterClass(MVT::v16i32, &AMDGPU::SReg_512RegClass);
65 addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
67 computeRegisterProperties(STI.getRegisterInfo());
69 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
70 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
71 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
72 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
74 setOperationAction(ISD::ADD, MVT::i32, Legal);
75 setOperationAction(ISD::ADDC, MVT::i32, Legal);
76 setOperationAction(ISD::ADDE, MVT::i32, Legal);
77 setOperationAction(ISD::SUBC, MVT::i32, Legal);
78 setOperationAction(ISD::SUBE, MVT::i32, Legal);
80 setOperationAction(ISD::FSIN, MVT::f32, Custom);
81 setOperationAction(ISD::FCOS, MVT::f32, Custom);
83 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
84 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
86 // We need to custom lower vector stores from local memory
87 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
88 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
89 setOperationAction(ISD::LOAD, MVT::v16i32, Custom);
91 setOperationAction(ISD::STORE, MVT::v8i32, Custom);
92 setOperationAction(ISD::STORE, MVT::v16i32, Custom);
94 setOperationAction(ISD::STORE, MVT::i1, Custom);
95 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
97 setOperationAction(ISD::SELECT, MVT::i64, Custom);
98 setOperationAction(ISD::SELECT, MVT::f64, Promote);
99 AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
101 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
102 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
103 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
104 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
106 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
107 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
109 setOperationAction(ISD::BSWAP, MVT::i32, Legal);
110 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
112 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Legal);
113 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
114 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
116 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Legal);
117 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
120 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
121 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
122 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
124 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
125 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom);
127 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
128 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom);
129 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v16i8, Custom);
130 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
132 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
133 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
135 for (MVT VT : MVT::integer_valuetypes()) {
139 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
140 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Legal);
141 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Legal);
142 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
144 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
145 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Legal);
146 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Legal);
147 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
149 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
150 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Legal);
151 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Legal);
152 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
155 for (MVT VT : MVT::integer_vector_valuetypes()) {
156 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i16, Expand);
157 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v16i16, Expand);
160 for (MVT VT : MVT::fp_valuetypes())
161 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
163 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
164 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand);
166 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
167 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand);
168 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Expand);
169 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand);
172 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Expand);
174 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
175 setTruncStoreAction(MVT::v2f64, MVT::v2f16, Expand);
177 setOperationAction(ISD::LOAD, MVT::i1, Custom);
179 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
180 AddPromotedToType(ISD::LOAD, MVT::v2i64, MVT::v4i32);
182 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
183 AddPromotedToType(ISD::STORE, MVT::v2i64, MVT::v4i32);
185 setOperationAction(ISD::ConstantPool, MVT::v2i64, Expand);
187 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
188 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
189 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
191 // These should use UDIVREM, so set them to expand
192 setOperationAction(ISD::UDIV, MVT::i64, Expand);
193 setOperationAction(ISD::UREM, MVT::i64, Expand);
195 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
196 setOperationAction(ISD::SELECT, MVT::i1, Promote);
198 setOperationAction(ISD::TRUNCATE, MVT::v2i32, Expand);
201 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
203 // We only support LOAD/STORE and vector manipulation ops for vectors
204 // with > 4 elements.
205 for (MVT VT : {MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32, MVT::v2i64, MVT::v2f64}) {
206 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
210 case ISD::BUILD_VECTOR:
212 case ISD::EXTRACT_VECTOR_ELT:
213 case ISD::INSERT_VECTOR_ELT:
214 case ISD::INSERT_SUBVECTOR:
215 case ISD::EXTRACT_SUBVECTOR:
216 case ISD::SCALAR_TO_VECTOR:
218 case ISD::CONCAT_VECTORS:
219 setOperationAction(Op, VT, Custom);
222 setOperationAction(Op, VT, Expand);
228 // Most operations are naturally 32-bit vector operations. We only support
229 // load and store of i64 vectors, so promote v2i64 vector operations to v4i32.
230 for (MVT Vec64 : { MVT::v2i64, MVT::v2f64 }) {
231 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote);
232 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v4i32);
234 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote);
235 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v4i32);
237 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote);
238 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32);
240 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote);
241 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v4i32);
244 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS) {
245 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
246 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
247 setOperationAction(ISD::FRINT, MVT::f64, Legal);
250 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
251 setOperationAction(ISD::FDIV, MVT::f32, Custom);
252 setOperationAction(ISD::FDIV, MVT::f64, Custom);
254 setTargetDAGCombine(ISD::FADD);
255 setTargetDAGCombine(ISD::FSUB);
256 setTargetDAGCombine(ISD::FMINNUM);
257 setTargetDAGCombine(ISD::FMAXNUM);
258 setTargetDAGCombine(ISD::SMIN);
259 setTargetDAGCombine(ISD::SMAX);
260 setTargetDAGCombine(ISD::UMIN);
261 setTargetDAGCombine(ISD::UMAX);
262 setTargetDAGCombine(ISD::SETCC);
263 setTargetDAGCombine(ISD::AND);
264 setTargetDAGCombine(ISD::OR);
265 setTargetDAGCombine(ISD::UINT_TO_FP);
267 // All memory operations. Some folding on the pointer operand is done to help
268 // matching the constant offsets in the addressing modes.
269 setTargetDAGCombine(ISD::LOAD);
270 setTargetDAGCombine(ISD::STORE);
271 setTargetDAGCombine(ISD::ATOMIC_LOAD);
272 setTargetDAGCombine(ISD::ATOMIC_STORE);
273 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP);
274 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
275 setTargetDAGCombine(ISD::ATOMIC_SWAP);
276 setTargetDAGCombine(ISD::ATOMIC_LOAD_ADD);
277 setTargetDAGCombine(ISD::ATOMIC_LOAD_SUB);
278 setTargetDAGCombine(ISD::ATOMIC_LOAD_AND);
279 setTargetDAGCombine(ISD::ATOMIC_LOAD_OR);
280 setTargetDAGCombine(ISD::ATOMIC_LOAD_XOR);
281 setTargetDAGCombine(ISD::ATOMIC_LOAD_NAND);
282 setTargetDAGCombine(ISD::ATOMIC_LOAD_MIN);
283 setTargetDAGCombine(ISD::ATOMIC_LOAD_MAX);
284 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMIN);
285 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMAX);
287 setSchedulingPreference(Sched::RegPressure);
290 //===----------------------------------------------------------------------===//
291 // TargetLowering queries
292 //===----------------------------------------------------------------------===//
294 bool SITargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &,
296 // SI has some legal vector types, but no legal vector operations. Say no
297 // shuffles are legal in order to prefer scalarizing some vector operations.
301 bool SITargetLowering::isLegalFlatAddressingMode(const AddrMode &AM) const {
302 // Flat instructions do not have offsets, and only have the register
304 return AM.BaseOffs == 0 && (AM.Scale == 0 || AM.Scale == 1);
307 bool SITargetLowering::isLegalMUBUFAddressingMode(const AddrMode &AM) const {
308 // MUBUF / MTBUF instructions have a 12-bit unsigned byte offset, and
309 // additionally can do r + r + i with addr64. 32-bit has more addressing
310 // mode options. Depending on the resource constant, it can also do
311 // (i64 r0) + (i32 r1) * (i14 i).
313 // Private arrays end up using a scratch buffer most of the time, so also
314 // assume those use MUBUF instructions. Scratch loads / stores are currently
315 // implemented as mubuf instructions with offen bit set, so slightly
316 // different than the normal addr64.
317 if (!isUInt<12>(AM.BaseOffs))
320 // FIXME: Since we can split immediate into soffset and immediate offset,
321 // would it make sense to allow any immediate?
324 case 0: // r + i or just i, depending on HasBaseReg.
327 return true; // We have r + r or r + i.
334 // Allow 2 * r as r + r
335 // Or 2 * r + i is allowed as r + r + i.
337 default: // Don't allow n * r
342 bool SITargetLowering::isLegalAddressingMode(const DataLayout &DL,
343 const AddrMode &AM, Type *Ty,
345 // No global is ever allowed as a base.
350 case AMDGPUAS::GLOBAL_ADDRESS: {
351 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
352 // Assume the we will use FLAT for all global memory accesses
354 // FIXME: This assumption is currently wrong. On VI we still use
355 // MUBUF instructions for the r + i addressing mode. As currently
356 // implemented, the MUBUF instructions only work on buffer < 4GB.
357 // It may be possible to support > 4GB buffers with MUBUF instructions,
358 // by setting the stride value in the resource descriptor which would
359 // increase the size limit to (stride * 4GB). However, this is risky,
360 // because it has never been validated.
361 return isLegalFlatAddressingMode(AM);
364 return isLegalMUBUFAddressingMode(AM);
366 case AMDGPUAS::CONSTANT_ADDRESS: {
367 // If the offset isn't a multiple of 4, it probably isn't going to be
368 // correctly aligned.
369 if (AM.BaseOffs % 4 != 0)
370 return isLegalMUBUFAddressingMode(AM);
372 // There are no SMRD extloads, so if we have to do a small type access we
373 // will use a MUBUF load.
374 // FIXME?: We also need to do this if unaligned, but we don't know the
376 if (DL.getTypeStoreSize(Ty) < 4)
377 return isLegalMUBUFAddressingMode(AM);
379 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS) {
380 // SMRD instructions have an 8-bit, dword offset on SI.
381 if (!isUInt<8>(AM.BaseOffs / 4))
383 } else if (Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS) {
384 // On CI+, this can also be a 32-bit literal constant offset. If it fits
385 // in 8-bits, it can use a smaller encoding.
386 if (!isUInt<32>(AM.BaseOffs / 4))
388 } else if (Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS) {
389 // On VI, these use the SMEM format and the offset is 20-bit in bytes.
390 if (!isUInt<20>(AM.BaseOffs))
393 llvm_unreachable("unhandled generation");
395 if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
398 if (AM.Scale == 1 && AM.HasBaseReg)
404 case AMDGPUAS::PRIVATE_ADDRESS:
405 case AMDGPUAS::UNKNOWN_ADDRESS_SPACE:
406 return isLegalMUBUFAddressingMode(AM);
408 case AMDGPUAS::LOCAL_ADDRESS:
409 case AMDGPUAS::REGION_ADDRESS: {
410 // Basic, single offset DS instructions allow a 16-bit unsigned immediate
412 // XXX - If doing a 4-byte aligned 8-byte type access, we effectively have
413 // an 8-bit dword offset but we don't know the alignment here.
414 if (!isUInt<16>(AM.BaseOffs))
417 if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
420 if (AM.Scale == 1 && AM.HasBaseReg)
425 case AMDGPUAS::FLAT_ADDRESS:
426 return isLegalFlatAddressingMode(AM);
429 llvm_unreachable("unhandled address space");
433 bool SITargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
436 bool *IsFast) const {
440 // TODO: I think v3i32 should allow unaligned accesses on CI with DS_READ_B96,
441 // which isn't a simple VT.
442 if (!VT.isSimple() || VT == MVT::Other)
445 // TODO - CI+ supports unaligned memory accesses, but this requires driver
448 // XXX - The only mention I see of this in the ISA manual is for LDS direct
449 // reads the "byte address and must be dword aligned". Is it also true for the
450 // normal loads and stores?
451 if (AddrSpace == AMDGPUAS::LOCAL_ADDRESS) {
452 // ds_read/write_b64 require 8-byte alignment, but we can do a 4 byte
453 // aligned, 8 byte access in a single operation using ds_read2/write2_b32
454 // with adjacent offsets.
455 bool AlignedBy4 = (Align % 4 == 0);
457 *IsFast = AlignedBy4;
461 // Smaller than dword value must be aligned.
462 // FIXME: This should be allowed on CI+
463 if (VT.bitsLT(MVT::i32))
466 // 8.1.6 - For Dword or larger reads or writes, the two LSBs of the
467 // byte-address are ignored, thus forcing Dword alignment.
468 // This applies to private, global, and constant memory.
472 return VT.bitsGT(MVT::i32) && Align % 4 == 0;
475 EVT SITargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
476 unsigned SrcAlign, bool IsMemset,
479 MachineFunction &MF) const {
480 // FIXME: Should account for address space here.
482 // The default fallback uses the private pointer size as a guess for a type to
483 // use. Make sure we switch these to 64-bit accesses.
485 if (Size >= 16 && DstAlign >= 4) // XXX: Should only do for global
488 if (Size >= 8 && DstAlign >= 4)
495 static bool isFlatGlobalAddrSpace(unsigned AS) {
496 return AS == AMDGPUAS::GLOBAL_ADDRESS ||
497 AS == AMDGPUAS::FLAT_ADDRESS ||
498 AS == AMDGPUAS::CONSTANT_ADDRESS;
501 bool SITargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
502 unsigned DestAS) const {
503 return isFlatGlobalAddrSpace(SrcAS) && isFlatGlobalAddrSpace(DestAS);
507 bool SITargetLowering::isMemOpUniform(const SDNode *N) const {
508 const MemSDNode *MemNode = cast<MemSDNode>(N);
509 const Value *Ptr = MemNode->getMemOperand()->getValue();
511 // UndefValue means this is a load of a kernel input. These are uniform.
512 // Sometimes LDS instructions have constant pointers
513 if (isa<UndefValue>(Ptr) || isa<Argument>(Ptr) || isa<Constant>(Ptr) ||
514 isa<GlobalValue>(Ptr))
517 const Instruction *I = dyn_cast_or_null<Instruction>(Ptr);
518 return I && I->getMetadata("amdgpu.uniform");
521 TargetLoweringBase::LegalizeTypeAction
522 SITargetLowering::getPreferredVectorAction(EVT VT) const {
523 if (VT.getVectorNumElements() != 1 && VT.getScalarType().bitsLE(MVT::i16))
524 return TypeSplitVector;
526 return TargetLoweringBase::getPreferredVectorAction(VT);
529 bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
531 const SIInstrInfo *TII =
532 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
533 return TII->isInlineConstant(Imm);
536 SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
537 SDLoc SL, SDValue Chain,
538 unsigned Offset, bool Signed) const {
539 const DataLayout &DL = DAG.getDataLayout();
540 MachineFunction &MF = DAG.getMachineFunction();
541 const SIRegisterInfo *TRI =
542 static_cast<const SIRegisterInfo*>(Subtarget->getRegisterInfo());
543 unsigned InputPtrReg = TRI->getPreloadedValue(MF, SIRegisterInfo::KERNARG_SEGMENT_PTR);
545 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
547 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
548 MVT PtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS);
549 PointerType *PtrTy = PointerType::get(Ty, AMDGPUAS::CONSTANT_ADDRESS);
550 SDValue BasePtr = DAG.getCopyFromReg(Chain, SL,
551 MRI.getLiveInVirtReg(InputPtrReg), PtrVT);
552 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
553 DAG.getConstant(Offset, SL, PtrVT));
554 SDValue PtrOffset = DAG.getUNDEF(PtrVT);
555 MachinePointerInfo PtrInfo(UndefValue::get(PtrTy));
557 unsigned Align = DL.getABITypeAlignment(Ty);
559 ISD::LoadExtType ExtTy = Signed ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
560 if (MemVT.isFloatingPoint())
561 ExtTy = ISD::EXTLOAD;
563 return DAG.getLoad(ISD::UNINDEXED, ExtTy,
564 VT, SL, Chain, Ptr, PtrOffset, PtrInfo, MemVT,
566 true, // isNonTemporal
571 SDValue SITargetLowering::LowerFormalArguments(
572 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
573 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
574 SmallVectorImpl<SDValue> &InVals) const {
575 const SIRegisterInfo *TRI =
576 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
578 MachineFunction &MF = DAG.getMachineFunction();
579 FunctionType *FType = MF.getFunction()->getFunctionType();
580 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
581 const AMDGPUSubtarget &ST = MF.getSubtarget<AMDGPUSubtarget>();
583 if (Subtarget->isAmdHsaOS() && Info->getShaderType() != ShaderType::COMPUTE) {
584 const Function *Fn = MF.getFunction();
585 DiagnosticInfoUnsupported NoGraphicsHSA(*Fn, "non-compute shaders with HSA");
586 DAG.getContext()->diagnose(NoGraphicsHSA);
590 // FIXME: We currently assume all calling conventions are kernels.
592 SmallVector<ISD::InputArg, 16> Splits;
593 BitVector Skipped(Ins.size());
595 for (unsigned i = 0, e = Ins.size(), PSInputNum = 0; i != e; ++i) {
596 const ISD::InputArg &Arg = Ins[i];
598 // First check if it's a PS input addr
599 if (Info->getShaderType() == ShaderType::PIXEL && !Arg.Flags.isInReg() &&
600 !Arg.Flags.isByVal() && PSInputNum <= 15) {
602 if (!Arg.Used && !Info->isPSInputAllocated(PSInputNum)) {
603 // We can safely skip PS inputs
609 Info->markPSInputAllocated(PSInputNum);
611 Info->PSInputEna |= 1 << PSInputNum;
616 // Second split vertices into their elements
617 if (Info->getShaderType() != ShaderType::COMPUTE && Arg.VT.isVector()) {
618 ISD::InputArg NewArg = Arg;
619 NewArg.Flags.setSplit();
620 NewArg.VT = Arg.VT.getVectorElementType();
622 // We REALLY want the ORIGINAL number of vertex elements here, e.g. a
623 // three or five element vertex only needs three or five registers,
624 // NOT four or eight.
625 Type *ParamType = FType->getParamType(Arg.getOrigArgIndex());
626 unsigned NumElements = ParamType->getVectorNumElements();
628 for (unsigned j = 0; j != NumElements; ++j) {
629 Splits.push_back(NewArg);
630 NewArg.PartOffset += NewArg.VT.getStoreSize();
633 } else if (Info->getShaderType() != ShaderType::COMPUTE) {
634 Splits.push_back(Arg);
638 SmallVector<CCValAssign, 16> ArgLocs;
639 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
642 // At least one interpolation mode must be enabled or else the GPU will hang.
644 // Check PSInputAddr instead of PSInputEna. The idea is that if the user set
645 // PSInputAddr, the user wants to enable some bits after the compilation
646 // based on run-time states. Since we can't know what the final PSInputEna
647 // will look like, so we shouldn't do anything here and the user should take
648 // responsibility for the correct programming.
650 // Otherwise, the following restrictions apply:
651 // - At least one of PERSP_* (0xF) or LINEAR_* (0x70) must be enabled.
652 // - If POS_W_FLOAT (11) is enabled, at least one of PERSP_* must be
654 if (Info->getShaderType() == ShaderType::PIXEL &&
655 ((Info->getPSInputAddr() & 0x7F) == 0 ||
656 ((Info->getPSInputAddr() & 0xF) == 0 &&
657 Info->isPSInputAllocated(11)))) {
658 CCInfo.AllocateReg(AMDGPU::VGPR0);
659 CCInfo.AllocateReg(AMDGPU::VGPR1);
660 Info->markPSInputAllocated(0);
661 Info->PSInputEna |= 1;
664 if (Info->getShaderType() == ShaderType::COMPUTE) {
665 getOriginalFunctionArgs(DAG, DAG.getMachineFunction().getFunction(), Ins,
669 // FIXME: How should these inputs interact with inreg / custom SGPR inputs?
670 if (Info->hasPrivateSegmentBuffer()) {
671 unsigned PrivateSegmentBufferReg = Info->addPrivateSegmentBuffer(*TRI);
672 MF.addLiveIn(PrivateSegmentBufferReg, &AMDGPU::SReg_128RegClass);
673 CCInfo.AllocateReg(PrivateSegmentBufferReg);
676 if (Info->hasDispatchPtr()) {
677 unsigned DispatchPtrReg = Info->addDispatchPtr(*TRI);
678 MF.addLiveIn(DispatchPtrReg, &AMDGPU::SReg_64RegClass);
679 CCInfo.AllocateReg(DispatchPtrReg);
682 if (Info->hasKernargSegmentPtr()) {
683 unsigned InputPtrReg = Info->addKernargSegmentPtr(*TRI);
684 MF.addLiveIn(InputPtrReg, &AMDGPU::SReg_64RegClass);
685 CCInfo.AllocateReg(InputPtrReg);
688 AnalyzeFormalArguments(CCInfo, Splits);
690 SmallVector<SDValue, 16> Chains;
692 for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
694 const ISD::InputArg &Arg = Ins[i];
696 InVals.push_back(DAG.getUNDEF(Arg.VT));
700 CCValAssign &VA = ArgLocs[ArgIdx++];
701 MVT VT = VA.getLocVT();
705 EVT MemVT = Splits[i].VT;
706 const unsigned Offset = Subtarget->getExplicitKernelArgOffset() +
707 VA.getLocMemOffset();
708 // The first 36 bytes of the input buffer contains information about
709 // thread group and global sizes.
710 SDValue Arg = LowerParameter(DAG, VT, MemVT, DL, Chain,
711 Offset, Ins[i].Flags.isSExt());
712 Chains.push_back(Arg.getValue(1));
715 dyn_cast<PointerType>(FType->getParamType(Ins[i].getOrigArgIndex()));
716 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS &&
717 ParamTy && ParamTy->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS) {
718 // On SI local pointers are just offsets into LDS, so they are always
719 // less than 16-bits. On CI and newer they could potentially be
720 // real pointers, so we can't guarantee their size.
721 Arg = DAG.getNode(ISD::AssertZext, DL, Arg.getValueType(), Arg,
722 DAG.getValueType(MVT::i16));
725 InVals.push_back(Arg);
726 Info->ABIArgOffset = Offset + MemVT.getStoreSize();
729 assert(VA.isRegLoc() && "Parameter must be in a register!");
731 unsigned Reg = VA.getLocReg();
733 if (VT == MVT::i64) {
734 // For now assume it is a pointer
735 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
736 &AMDGPU::SReg_64RegClass);
737 Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass);
738 SDValue Copy = DAG.getCopyFromReg(Chain, DL, Reg, VT);
739 InVals.push_back(Copy);
743 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
745 Reg = MF.addLiveIn(Reg, RC);
746 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
748 if (Arg.VT.isVector()) {
750 // Build a vector from the registers
751 Type *ParamType = FType->getParamType(Arg.getOrigArgIndex());
752 unsigned NumElements = ParamType->getVectorNumElements();
754 SmallVector<SDValue, 4> Regs;
756 for (unsigned j = 1; j != NumElements; ++j) {
757 Reg = ArgLocs[ArgIdx++].getLocReg();
758 Reg = MF.addLiveIn(Reg, RC);
760 SDValue Copy = DAG.getCopyFromReg(Chain, DL, Reg, VT);
761 Regs.push_back(Copy);
764 // Fill up the missing vector elements
765 NumElements = Arg.VT.getVectorNumElements() - NumElements;
766 Regs.append(NumElements, DAG.getUNDEF(VT));
768 InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT, Regs));
772 InVals.push_back(Val);
775 // TODO: Add GridWorkGroupCount user SGPRs when used. For now with HSA we read
776 // these from the dispatch pointer.
778 // Start adding system SGPRs.
779 if (Info->hasWorkGroupIDX()) {
780 unsigned Reg = Info->addWorkGroupIDX();
781 MF.addLiveIn(Reg, &AMDGPU::SReg_32RegClass);
782 CCInfo.AllocateReg(Reg);
784 llvm_unreachable("work group id x is always enabled");
786 if (Info->hasWorkGroupIDY()) {
787 unsigned Reg = Info->addWorkGroupIDY();
788 MF.addLiveIn(Reg, &AMDGPU::SReg_32RegClass);
789 CCInfo.AllocateReg(Reg);
792 if (Info->hasWorkGroupIDZ()) {
793 unsigned Reg = Info->addWorkGroupIDZ();
794 MF.addLiveIn(Reg, &AMDGPU::SReg_32RegClass);
795 CCInfo.AllocateReg(Reg);
798 if (Info->hasWorkGroupInfo()) {
799 unsigned Reg = Info->addWorkGroupInfo();
800 MF.addLiveIn(Reg, &AMDGPU::SReg_32RegClass);
801 CCInfo.AllocateReg(Reg);
804 if (Info->hasPrivateSegmentWaveByteOffset()) {
805 // Scratch wave offset passed in system SGPR.
806 unsigned PrivateSegmentWaveByteOffsetReg
807 = Info->addPrivateSegmentWaveByteOffset();
809 MF.addLiveIn(PrivateSegmentWaveByteOffsetReg, &AMDGPU::SGPR_32RegClass);
810 CCInfo.AllocateReg(PrivateSegmentWaveByteOffsetReg);
813 // Now that we've figured out where the scratch register inputs are, see if
814 // should reserve the arguments and use them directly.
816 bool HasStackObjects = MF.getFrameInfo()->hasStackObjects();
818 if (ST.isAmdHsaOS()) {
819 // TODO: Assume we will spill without optimizations.
820 if (HasStackObjects) {
821 // If we have stack objects, we unquestionably need the private buffer
822 // resource. For the HSA ABI, this will be the first 4 user SGPR
823 // inputs. We can reserve those and use them directly.
825 unsigned PrivateSegmentBufferReg = TRI->getPreloadedValue(
826 MF, SIRegisterInfo::PRIVATE_SEGMENT_BUFFER);
827 Info->setScratchRSrcReg(PrivateSegmentBufferReg);
829 unsigned PrivateSegmentWaveByteOffsetReg = TRI->getPreloadedValue(
830 MF, SIRegisterInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET);
831 Info->setScratchWaveOffsetReg(PrivateSegmentWaveByteOffsetReg);
833 unsigned ReservedBufferReg
834 = TRI->reservedPrivateSegmentBufferReg(MF);
835 unsigned ReservedOffsetReg
836 = TRI->reservedPrivateSegmentWaveByteOffsetReg(MF);
838 // We tentatively reserve the last registers (skipping the last two
839 // which may contain VCC). After register allocation, we'll replace
840 // these with the ones immediately after those which were really
841 // allocated. In the prologue copies will be inserted from the argument
842 // to these reserved registers.
843 Info->setScratchRSrcReg(ReservedBufferReg);
844 Info->setScratchWaveOffsetReg(ReservedOffsetReg);
847 unsigned ReservedBufferReg = TRI->reservedPrivateSegmentBufferReg(MF);
849 // Without HSA, relocations are used for the scratch pointer and the
850 // buffer resource setup is always inserted in the prologue. Scratch wave
851 // offset is still in an input SGPR.
852 Info->setScratchRSrcReg(ReservedBufferReg);
854 if (HasStackObjects) {
855 unsigned ScratchWaveOffsetReg = TRI->getPreloadedValue(
856 MF, SIRegisterInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET);
857 Info->setScratchWaveOffsetReg(ScratchWaveOffsetReg);
859 unsigned ReservedOffsetReg
860 = TRI->reservedPrivateSegmentWaveByteOffsetReg(MF);
861 Info->setScratchWaveOffsetReg(ReservedOffsetReg);
865 if (Info->hasWorkItemIDX()) {
866 unsigned Reg = TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_X);
867 MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
868 CCInfo.AllocateReg(Reg);
870 llvm_unreachable("workitem id x should always be enabled");
872 if (Info->hasWorkItemIDY()) {
873 unsigned Reg = TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_Y);
874 MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
875 CCInfo.AllocateReg(Reg);
878 if (Info->hasWorkItemIDZ()) {
879 unsigned Reg = TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_Z);
880 MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
881 CCInfo.AllocateReg(Reg);
887 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
890 SDValue SITargetLowering::LowerReturn(SDValue Chain,
891 CallingConv::ID CallConv,
893 const SmallVectorImpl<ISD::OutputArg> &Outs,
894 const SmallVectorImpl<SDValue> &OutVals,
895 SDLoc DL, SelectionDAG &DAG) const {
896 MachineFunction &MF = DAG.getMachineFunction();
897 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
899 if (Info->getShaderType() == ShaderType::COMPUTE)
900 return AMDGPUTargetLowering::LowerReturn(Chain, CallConv, isVarArg, Outs,
903 Info->setIfReturnsVoid(Outs.size() == 0);
905 SmallVector<ISD::OutputArg, 48> Splits;
906 SmallVector<SDValue, 48> SplitVals;
908 // Split vectors into their elements.
909 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
910 const ISD::OutputArg &Out = Outs[i];
912 if (Out.VT.isVector()) {
913 MVT VT = Out.VT.getVectorElementType();
914 ISD::OutputArg NewOut = Out;
915 NewOut.Flags.setSplit();
918 // We want the original number of vector elements here, e.g.
919 // three or five, not four or eight.
920 unsigned NumElements = Out.ArgVT.getVectorNumElements();
922 for (unsigned j = 0; j != NumElements; ++j) {
923 SDValue Elem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, OutVals[i],
924 DAG.getConstant(j, DL, MVT::i32));
925 SplitVals.push_back(Elem);
926 Splits.push_back(NewOut);
927 NewOut.PartOffset += NewOut.VT.getStoreSize();
930 SplitVals.push_back(OutVals[i]);
931 Splits.push_back(Out);
935 // CCValAssign - represent the assignment of the return value to a location.
936 SmallVector<CCValAssign, 48> RVLocs;
938 // CCState - Info about the registers and stack slots.
939 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
942 // Analyze outgoing return values.
943 AnalyzeReturn(CCInfo, Splits);
946 SmallVector<SDValue, 48> RetOps;
947 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
949 // Copy the result values into the output registers.
950 for (unsigned i = 0, realRVLocIdx = 0;
952 ++i, ++realRVLocIdx) {
953 CCValAssign &VA = RVLocs[i];
954 assert(VA.isRegLoc() && "Can only return in registers!");
956 SDValue Arg = SplitVals[realRVLocIdx];
958 // Copied from other backends.
959 switch (VA.getLocInfo()) {
960 default: llvm_unreachable("Unknown loc info!");
961 case CCValAssign::Full:
963 case CCValAssign::BCvt:
964 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
968 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
969 Flag = Chain.getValue(1);
970 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
973 // Update chain and glue.
976 RetOps.push_back(Flag);
978 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, RetOps);
981 MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
982 MachineInstr * MI, MachineBasicBlock * BB) const {
984 switch (MI->getOpcode()) {
986 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
993 bool SITargetLowering::enableAggressiveFMAFusion(EVT VT) const {
994 // This currently forces unfolding various combinations of fsub into fma with
995 // free fneg'd operands. As long as we have fast FMA (controlled by
996 // isFMAFasterThanFMulAndFAdd), we should perform these.
998 // When fma is quarter rate, for f64 where add / sub are at best half rate,
999 // most of these combines appear to be cycle neutral but save on instruction
1000 // count / code size.
1004 EVT SITargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx,
1006 if (!VT.isVector()) {
1009 return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
1012 MVT SITargetLowering::getScalarShiftAmountTy(const DataLayout &, EVT) const {
1016 // Answering this is somewhat tricky and depends on the specific device which
1017 // have different rates for fma or all f64 operations.
1019 // v_fma_f64 and v_mul_f64 always take the same number of cycles as each other
1020 // regardless of which device (although the number of cycles differs between
1021 // devices), so it is always profitable for f64.
1023 // v_fma_f32 takes 4 or 16 cycles depending on the device, so it is profitable
1024 // only on full rate devices. Normally, we should prefer selecting v_mad_f32
1025 // which we can always do even without fused FP ops since it returns the same
1026 // result as the separate operations and since it is always full
1027 // rate. Therefore, we lie and report that it is not faster for f32. v_mad_f32
1028 // however does not support denormals, so we do report fma as faster if we have
1029 // a fast fma device and require denormals.
1031 bool SITargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
1032 VT = VT.getScalarType();
1037 switch (VT.getSimpleVT().SimpleTy) {
1039 // This is as fast on some subtargets. However, we always have full rate f32
1040 // mad available which returns the same result as the separate operations
1041 // which we should prefer over fma. We can't use this if we want to support
1042 // denormals, so only report this in these cases.
1043 return Subtarget->hasFP32Denormals() && Subtarget->hasFastFMAF32();
1053 //===----------------------------------------------------------------------===//
1054 // Custom DAG Lowering Operations
1055 //===----------------------------------------------------------------------===//
1057 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
1058 switch (Op.getOpcode()) {
1059 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
1060 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
1061 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
1063 SDValue Result = LowerLOAD(Op, DAG);
1064 assert((!Result.getNode() ||
1065 Result.getNode()->getNumValues() == 2) &&
1066 "Load should return a value and a chain");
1072 return LowerTrig(Op, DAG);
1073 case ISD::SELECT: return LowerSELECT(Op, DAG);
1074 case ISD::FDIV: return LowerFDIV(Op, DAG);
1075 case ISD::STORE: return LowerSTORE(Op, DAG);
1076 case ISD::GlobalAddress: {
1077 MachineFunction &MF = DAG.getMachineFunction();
1078 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1079 return LowerGlobalAddress(MFI, Op, DAG);
1081 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
1082 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
1087 /// \brief Helper function for LowerBRCOND
1088 static SDNode *findUser(SDValue Value, unsigned Opcode) {
1090 SDNode *Parent = Value.getNode();
1091 for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
1094 if (I.getUse().get() != Value)
1097 if (I->getOpcode() == Opcode)
1103 SDValue SITargetLowering::LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const {
1106 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Op);
1107 unsigned FrameIndex = FINode->getIndex();
1109 // A FrameIndex node represents a 32-bit offset into scratch memory. If
1110 // the high bit of a frame index offset were to be set, this would mean
1111 // that it represented an offset of ~2GB * 64 = ~128GB from the start of the
1112 // scratch buffer, with 64 being the number of threads per wave.
1114 // If we know the machine uses less than 128GB of scratch, then we can
1115 // amrk the high bit of the FrameIndex node as known zero,
1116 // which is important, because it means in most situations we can
1117 // prove that values derived from FrameIndex nodes are non-negative.
1118 // This enables us to take advantage of more addressing modes when
1119 // accessing scratch buffers, since for scratch reads/writes, the register
1120 // offset must always be positive.
1122 SDValue TFI = DAG.getTargetFrameIndex(FrameIndex, MVT::i32);
1123 if (Subtarget->enableHugeScratchBuffer())
1126 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, TFI,
1127 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), 31)));
1130 /// This transforms the control flow intrinsics to get the branch destination as
1131 /// last parameter, also switches branch target with BR if the need arise
1132 SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
1133 SelectionDAG &DAG) const {
1137 SDNode *Intr = BRCOND.getOperand(1).getNode();
1138 SDValue Target = BRCOND.getOperand(2);
1139 SDNode *BR = nullptr;
1141 if (Intr->getOpcode() == ISD::SETCC) {
1142 // As long as we negate the condition everything is fine
1143 SDNode *SetCC = Intr;
1144 assert(SetCC->getConstantOperandVal(1) == 1);
1145 assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
1147 Intr = SetCC->getOperand(0).getNode();
1150 // Get the target from BR if we don't negate the condition
1151 BR = findUser(BRCOND, ISD::BR);
1152 Target = BR->getOperand(1);
1155 assert(Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN);
1157 // Build the result and
1158 ArrayRef<EVT> Res(Intr->value_begin() + 1, Intr->value_end());
1160 // operands of the new intrinsic call
1161 SmallVector<SDValue, 4> Ops;
1162 Ops.push_back(BRCOND.getOperand(0));
1163 Ops.append(Intr->op_begin() + 1, Intr->op_end());
1164 Ops.push_back(Target);
1166 // build the new intrinsic call
1167 SDNode *Result = DAG.getNode(
1168 Res.size() > 1 ? ISD::INTRINSIC_W_CHAIN : ISD::INTRINSIC_VOID, DL,
1169 DAG.getVTList(Res), Ops).getNode();
1172 // Give the branch instruction our target
1175 BRCOND.getOperand(2)
1177 SDValue NewBR = DAG.getNode(ISD::BR, DL, BR->getVTList(), Ops);
1178 DAG.ReplaceAllUsesWith(BR, NewBR.getNode());
1179 BR = NewBR.getNode();
1182 SDValue Chain = SDValue(Result, Result->getNumValues() - 1);
1184 // Copy the intrinsic results to registers
1185 for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
1186 SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
1190 Chain = DAG.getCopyToReg(
1192 CopyToReg->getOperand(1),
1193 SDValue(Result, i - 1),
1196 DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0));
1199 // Remove the old intrinsic from the chain
1200 DAG.ReplaceAllUsesOfValueWith(
1201 SDValue(Intr, Intr->getNumValues() - 1),
1202 Intr->getOperand(0));
1207 SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
1209 SelectionDAG &DAG) const {
1210 GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Op);
1212 if (GSD->getAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
1213 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG);
1216 const GlobalValue *GV = GSD->getGlobal();
1217 MVT PtrVT = getPointerTy(DAG.getDataLayout(), GSD->getAddressSpace());
1219 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32);
1220 return DAG.getNode(AMDGPUISD::CONST_DATA_PTR, DL, PtrVT, GA);
1223 SDValue SITargetLowering::copyToM0(SelectionDAG &DAG, SDValue Chain, SDLoc DL,
1225 // We can't use CopyToReg, because MachineCSE won't combine COPY instructions,
1226 // so we will end up with redundant moves to m0.
1228 // We can't use S_MOV_B32, because there is no way to specify m0 as the
1229 // destination register.
1231 // We have to use them both. Machine cse will combine all the S_MOV_B32
1232 // instructions and the register coalescer eliminate the extra copies.
1233 SDNode *M0 = DAG.getMachineNode(AMDGPU::S_MOV_B32, DL, V.getValueType(), V);
1234 return DAG.getCopyToReg(Chain, DL, DAG.getRegister(AMDGPU::M0, MVT::i32),
1235 SDValue(M0, 0), SDValue()); // Glue
1236 // A Null SDValue creates
1240 SDValue SITargetLowering::lowerImplicitZextParam(SelectionDAG &DAG,
1243 unsigned Offset) const {
1245 SDValue Param = LowerParameter(DAG, MVT::i32, MVT::i32, SL,
1246 DAG.getEntryNode(), Offset, false);
1247 // The local size values will have the hi 16-bits as zero.
1248 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, Param,
1249 DAG.getValueType(VT));
1252 SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
1253 SelectionDAG &DAG) const {
1254 MachineFunction &MF = DAG.getMachineFunction();
1255 auto MFI = MF.getInfo<SIMachineFunctionInfo>();
1256 const SIRegisterInfo *TRI =
1257 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
1259 EVT VT = Op.getValueType();
1261 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1263 // TODO: Should this propagate fast-math-flags?
1265 switch (IntrinsicID) {
1266 case Intrinsic::amdgcn_dispatch_ptr:
1267 if (!Subtarget->isAmdHsaOS()) {
1268 DiagnosticInfoUnsupported BadIntrin(*MF.getFunction(),
1269 "hsa intrinsic without hsa target");
1270 DAG.getContext()->diagnose(BadIntrin);
1271 return DAG.getUNDEF(VT);
1274 return CreateLiveInRegister(DAG, &AMDGPU::SReg_64RegClass,
1275 TRI->getPreloadedValue(MF, SIRegisterInfo::DISPATCH_PTR), VT);
1277 case Intrinsic::r600_read_ngroups_x:
1278 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1279 SI::KernelInputOffsets::NGROUPS_X, false);
1280 case Intrinsic::r600_read_ngroups_y:
1281 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1282 SI::KernelInputOffsets::NGROUPS_Y, false);
1283 case Intrinsic::r600_read_ngroups_z:
1284 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1285 SI::KernelInputOffsets::NGROUPS_Z, false);
1286 case Intrinsic::r600_read_global_size_x:
1287 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1288 SI::KernelInputOffsets::GLOBAL_SIZE_X, false);
1289 case Intrinsic::r600_read_global_size_y:
1290 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1291 SI::KernelInputOffsets::GLOBAL_SIZE_Y, false);
1292 case Intrinsic::r600_read_global_size_z:
1293 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1294 SI::KernelInputOffsets::GLOBAL_SIZE_Z, false);
1295 case Intrinsic::r600_read_local_size_x:
1296 return lowerImplicitZextParam(DAG, Op, MVT::i16,
1297 SI::KernelInputOffsets::LOCAL_SIZE_X);
1298 case Intrinsic::r600_read_local_size_y:
1299 return lowerImplicitZextParam(DAG, Op, MVT::i16,
1300 SI::KernelInputOffsets::LOCAL_SIZE_Y);
1301 case Intrinsic::r600_read_local_size_z:
1302 return lowerImplicitZextParam(DAG, Op, MVT::i16,
1303 SI::KernelInputOffsets::LOCAL_SIZE_Z);
1304 case Intrinsic::AMDGPU_read_workdim:
1305 // Really only 2 bits.
1306 return lowerImplicitZextParam(DAG, Op, MVT::i8,
1307 getImplicitParameterOffset(MFI, GRID_DIM));
1308 case Intrinsic::r600_read_tgid_x:
1309 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
1310 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKGROUP_ID_X), VT);
1311 case Intrinsic::r600_read_tgid_y:
1312 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
1313 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKGROUP_ID_Y), VT);
1314 case Intrinsic::r600_read_tgid_z:
1315 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
1316 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKGROUP_ID_Z), VT);
1317 case Intrinsic::r600_read_tidig_x:
1318 return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass,
1319 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_X), VT);
1320 case Intrinsic::r600_read_tidig_y:
1321 return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass,
1322 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_Y), VT);
1323 case Intrinsic::r600_read_tidig_z:
1324 return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass,
1325 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_Z), VT);
1326 case AMDGPUIntrinsic::SI_load_const: {
1332 MachineMemOperand *MMO = MF.getMachineMemOperand(
1333 MachinePointerInfo(),
1334 MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant,
1335 VT.getStoreSize(), 4);
1336 return DAG.getMemIntrinsicNode(AMDGPUISD::LOAD_CONSTANT, DL,
1337 Op->getVTList(), Ops, VT, MMO);
1339 case AMDGPUIntrinsic::SI_sample:
1340 return LowerSampleIntrinsic(AMDGPUISD::SAMPLE, Op, DAG);
1341 case AMDGPUIntrinsic::SI_sampleb:
1342 return LowerSampleIntrinsic(AMDGPUISD::SAMPLEB, Op, DAG);
1343 case AMDGPUIntrinsic::SI_sampled:
1344 return LowerSampleIntrinsic(AMDGPUISD::SAMPLED, Op, DAG);
1345 case AMDGPUIntrinsic::SI_samplel:
1346 return LowerSampleIntrinsic(AMDGPUISD::SAMPLEL, Op, DAG);
1347 case AMDGPUIntrinsic::SI_vs_load_input:
1348 return DAG.getNode(AMDGPUISD::LOAD_INPUT, DL, VT,
1353 case AMDGPUIntrinsic::AMDGPU_fract:
1354 case AMDGPUIntrinsic::AMDIL_fraction: // Legacy name.
1355 return DAG.getNode(ISD::FSUB, DL, VT, Op.getOperand(1),
1356 DAG.getNode(ISD::FFLOOR, DL, VT, Op.getOperand(1)));
1357 case AMDGPUIntrinsic::SI_fs_constant: {
1358 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(3));
1359 SDValue Glue = M0.getValue(1);
1360 return DAG.getNode(AMDGPUISD::INTERP_MOV, DL, MVT::f32,
1361 DAG.getConstant(2, DL, MVT::i32), // P0
1362 Op.getOperand(1), Op.getOperand(2), Glue);
1364 case AMDGPUIntrinsic::SI_packf16:
1365 if (Op.getOperand(1).isUndef() && Op.getOperand(2).isUndef())
1366 return DAG.getUNDEF(MVT::i32);
1368 case AMDGPUIntrinsic::SI_fs_interp: {
1369 SDValue IJ = Op.getOperand(4);
1370 SDValue I = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, IJ,
1371 DAG.getConstant(0, DL, MVT::i32));
1372 SDValue J = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, IJ,
1373 DAG.getConstant(1, DL, MVT::i32));
1374 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(3));
1375 SDValue Glue = M0.getValue(1);
1376 SDValue P1 = DAG.getNode(AMDGPUISD::INTERP_P1, DL,
1377 DAG.getVTList(MVT::f32, MVT::Glue),
1378 I, Op.getOperand(1), Op.getOperand(2), Glue);
1379 Glue = SDValue(P1.getNode(), 1);
1380 return DAG.getNode(AMDGPUISD::INTERP_P2, DL, MVT::f32, P1, J,
1381 Op.getOperand(1), Op.getOperand(2), Glue);
1383 case Intrinsic::amdgcn_interp_p1: {
1384 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(4));
1385 SDValue Glue = M0.getValue(1);
1386 return DAG.getNode(AMDGPUISD::INTERP_P1, DL, MVT::f32, Op.getOperand(1),
1387 Op.getOperand(2), Op.getOperand(3), Glue);
1389 case Intrinsic::amdgcn_interp_p2: {
1390 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(5));
1391 SDValue Glue = SDValue(M0.getNode(), 1);
1392 return DAG.getNode(AMDGPUISD::INTERP_P2, DL, MVT::f32, Op.getOperand(1),
1393 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4),
1397 return AMDGPUTargetLowering::LowerOperation(Op, DAG);
1401 SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
1402 SelectionDAG &DAG) const {
1403 MachineFunction &MF = DAG.getMachineFunction();
1405 SDValue Chain = Op.getOperand(0);
1406 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1408 switch (IntrinsicID) {
1409 case AMDGPUIntrinsic::SI_sendmsg: {
1410 Chain = copyToM0(DAG, Chain, DL, Op.getOperand(3));
1411 SDValue Glue = Chain.getValue(1);
1412 return DAG.getNode(AMDGPUISD::SENDMSG, DL, MVT::Other, Chain,
1413 Op.getOperand(2), Glue);
1415 case AMDGPUIntrinsic::SI_tbuffer_store: {
1433 EVT VT = Op.getOperand(3).getValueType();
1435 MachineMemOperand *MMO = MF.getMachineMemOperand(
1436 MachinePointerInfo(),
1437 MachineMemOperand::MOStore,
1438 VT.getStoreSize(), 4);
1439 return DAG.getMemIntrinsicNode(AMDGPUISD::TBUFFER_STORE_FORMAT, DL,
1440 Op->getVTList(), Ops, VT, MMO);
1447 SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1449 LoadSDNode *Load = cast<LoadSDNode>(Op);
1451 if (Op.getValueType().isVector()) {
1452 assert(Op.getValueType().getVectorElementType() == MVT::i32 &&
1453 "Custom lowering for non-i32 vectors hasn't been implemented.");
1454 unsigned NumElements = Op.getValueType().getVectorNumElements();
1455 assert(NumElements != 2 && "v2 loads are supported for all address spaces.");
1457 switch (Load->getAddressSpace()) {
1459 case AMDGPUAS::CONSTANT_ADDRESS:
1460 if (isMemOpUniform(Load))
1462 // Non-uniform loads will be selected to MUBUF instructions, so they
1463 // have the same legalization requires ments as global and private
1467 case AMDGPUAS::GLOBAL_ADDRESS:
1468 case AMDGPUAS::PRIVATE_ADDRESS:
1469 if (NumElements >= 8)
1470 return SplitVectorLoad(Op, DAG);
1472 // v4 loads are supported for private and global memory.
1473 if (NumElements <= 4)
1476 case AMDGPUAS::LOCAL_ADDRESS:
1477 // If properly aligned, if we split we might be able to use ds_read_b64.
1478 return SplitVectorLoad(Op, DAG);
1482 return AMDGPUTargetLowering::LowerLOAD(Op, DAG);
1485 SDValue SITargetLowering::LowerSampleIntrinsic(unsigned Opcode,
1487 SelectionDAG &DAG) const {
1488 return DAG.getNode(Opcode, SDLoc(Op), Op.getValueType(), Op.getOperand(1),
1494 SDValue SITargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
1495 if (Op.getValueType() != MVT::i64)
1499 SDValue Cond = Op.getOperand(0);
1501 SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
1502 SDValue One = DAG.getConstant(1, DL, MVT::i32);
1504 SDValue LHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(1));
1505 SDValue RHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(2));
1507 SDValue Lo0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, Zero);
1508 SDValue Lo1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, Zero);
1510 SDValue Lo = DAG.getSelect(DL, MVT::i32, Cond, Lo0, Lo1);
1512 SDValue Hi0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, One);
1513 SDValue Hi1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, One);
1515 SDValue Hi = DAG.getSelect(DL, MVT::i32, Cond, Hi0, Hi1);
1517 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2i32, Lo, Hi);
1518 return DAG.getNode(ISD::BITCAST, DL, MVT::i64, Res);
1521 // Catch division cases where we can use shortcuts with rcp and rsq
1523 SDValue SITargetLowering::LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const {
1525 SDValue LHS = Op.getOperand(0);
1526 SDValue RHS = Op.getOperand(1);
1527 EVT VT = Op.getValueType();
1528 bool Unsafe = DAG.getTarget().Options.UnsafeFPMath;
1530 if (const ConstantFPSDNode *CLHS = dyn_cast<ConstantFPSDNode>(LHS)) {
1531 if ((Unsafe || (VT == MVT::f32 && !Subtarget->hasFP32Denormals())) &&
1532 CLHS->isExactlyValue(1.0)) {
1533 // v_rcp_f32 and v_rsq_f32 do not support denormals, and according to
1534 // the CI documentation has a worst case error of 1 ulp.
1535 // OpenCL requires <= 2.5 ulp for 1.0 / x, so it should always be OK to
1536 // use it as long as we aren't trying to use denormals.
1538 // 1.0 / sqrt(x) -> rsq(x)
1540 // XXX - Is UnsafeFPMath sufficient to do this for f64? The maximum ULP
1541 // error seems really high at 2^29 ULP.
1542 if (RHS.getOpcode() == ISD::FSQRT)
1543 return DAG.getNode(AMDGPUISD::RSQ, SL, VT, RHS.getOperand(0));
1545 // 1.0 / x -> rcp(x)
1546 return DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
1551 // Turn into multiply by the reciprocal.
1552 // x / y -> x * (1.0 / y)
1554 Flags.setUnsafeAlgebra(true);
1555 SDValue Recip = DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
1556 return DAG.getNode(ISD::FMUL, SL, VT, LHS, Recip, &Flags);
1562 SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const {
1563 SDValue FastLowered = LowerFastFDIV(Op, DAG);
1564 if (FastLowered.getNode())
1567 // This uses v_rcp_f32 which does not handle denormals. Let this hit a
1568 // selection error for now rather than do something incorrect.
1569 if (Subtarget->hasFP32Denormals())
1573 SDValue LHS = Op.getOperand(0);
1574 SDValue RHS = Op.getOperand(1);
1576 SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS);
1578 const APFloat K0Val(BitsToFloat(0x6f800000));
1579 const SDValue K0 = DAG.getConstantFP(K0Val, SL, MVT::f32);
1581 const APFloat K1Val(BitsToFloat(0x2f800000));
1582 const SDValue K1 = DAG.getConstantFP(K1Val, SL, MVT::f32);
1584 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32);
1587 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f32);
1589 SDValue r2 = DAG.getSetCC(SL, SetCCVT, r1, K0, ISD::SETOGT);
1591 SDValue r3 = DAG.getNode(ISD::SELECT, SL, MVT::f32, r2, K1, One);
1593 // TODO: Should this propagate fast-math-flags?
1595 r1 = DAG.getNode(ISD::FMUL, SL, MVT::f32, RHS, r3);
1597 SDValue r0 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, r1);
1599 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, LHS, r0);
1601 return DAG.getNode(ISD::FMUL, SL, MVT::f32, r3, Mul);
1604 SDValue SITargetLowering::LowerFDIV64(SDValue Op, SelectionDAG &DAG) const {
1605 if (DAG.getTarget().Options.UnsafeFPMath)
1606 return LowerFastFDIV(Op, DAG);
1609 SDValue X = Op.getOperand(0);
1610 SDValue Y = Op.getOperand(1);
1612 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64);
1614 SDVTList ScaleVT = DAG.getVTList(MVT::f64, MVT::i1);
1616 SDValue DivScale0 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, Y, Y, X);
1618 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f64, DivScale0);
1620 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f64, DivScale0);
1622 SDValue Fma0 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Rcp, One);
1624 SDValue Fma1 = DAG.getNode(ISD::FMA, SL, MVT::f64, Rcp, Fma0, Rcp);
1626 SDValue Fma2 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Fma1, One);
1628 SDValue DivScale1 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, X, Y, X);
1630 SDValue Fma3 = DAG.getNode(ISD::FMA, SL, MVT::f64, Fma1, Fma2, Fma1);
1631 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, DivScale1, Fma3);
1633 SDValue Fma4 = DAG.getNode(ISD::FMA, SL, MVT::f64,
1634 NegDivScale0, Mul, DivScale1);
1638 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS) {
1639 // Workaround a hardware bug on SI where the condition output from div_scale
1642 const SDValue Hi = DAG.getConstant(1, SL, MVT::i32);
1644 // Figure out if the scale to use for div_fmas.
1645 SDValue NumBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
1646 SDValue DenBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Y);
1647 SDValue Scale0BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale0);
1648 SDValue Scale1BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale1);
1650 SDValue NumHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, NumBC, Hi);
1651 SDValue DenHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, DenBC, Hi);
1654 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Scale0BC, Hi);
1656 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Scale1BC, Hi);
1658 SDValue CmpDen = DAG.getSetCC(SL, MVT::i1, DenHi, Scale0Hi, ISD::SETEQ);
1659 SDValue CmpNum = DAG.getSetCC(SL, MVT::i1, NumHi, Scale1Hi, ISD::SETEQ);
1660 Scale = DAG.getNode(ISD::XOR, SL, MVT::i1, CmpNum, CmpDen);
1662 Scale = DivScale1.getValue(1);
1665 SDValue Fmas = DAG.getNode(AMDGPUISD::DIV_FMAS, SL, MVT::f64,
1666 Fma4, Fma3, Mul, Scale);
1668 return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f64, Fmas, Y, X);
1671 SDValue SITargetLowering::LowerFDIV(SDValue Op, SelectionDAG &DAG) const {
1672 EVT VT = Op.getValueType();
1675 return LowerFDIV32(Op, DAG);
1678 return LowerFDIV64(Op, DAG);
1680 llvm_unreachable("Unexpected type for fdiv");
1683 SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1685 StoreSDNode *Store = cast<StoreSDNode>(Op);
1686 EVT VT = Store->getMemoryVT();
1688 // These stores are legal.
1689 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) {
1690 if (VT.isVector() && VT.getVectorNumElements() > 4)
1691 return ScalarizeVectorStore(Op, DAG);
1695 SDValue Ret = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
1699 if (VT.isVector() && VT.getVectorNumElements() >= 8)
1700 return SplitVectorStore(Op, DAG);
1703 return DAG.getTruncStore(Store->getChain(), DL,
1704 DAG.getSExtOrTrunc(Store->getValue(), DL, MVT::i32),
1705 Store->getBasePtr(), MVT::i1, Store->getMemOperand());
1710 SDValue SITargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
1712 EVT VT = Op.getValueType();
1713 SDValue Arg = Op.getOperand(0);
1714 // TODO: Should this propagate fast-math-flags?
1715 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, DL, VT,
1716 DAG.getNode(ISD::FMUL, DL, VT, Arg,
1717 DAG.getConstantFP(0.5/M_PI, DL,
1720 switch (Op.getOpcode()) {
1722 return DAG.getNode(AMDGPUISD::COS_HW, SDLoc(Op), VT, FractPart);
1724 return DAG.getNode(AMDGPUISD::SIN_HW, SDLoc(Op), VT, FractPart);
1726 llvm_unreachable("Wrong trig opcode");
1730 //===----------------------------------------------------------------------===//
1731 // Custom DAG optimizations
1732 //===----------------------------------------------------------------------===//
1734 SDValue SITargetLowering::performUCharToFloatCombine(SDNode *N,
1735 DAGCombinerInfo &DCI) const {
1736 EVT VT = N->getValueType(0);
1737 EVT ScalarVT = VT.getScalarType();
1738 if (ScalarVT != MVT::f32)
1741 SelectionDAG &DAG = DCI.DAG;
1744 SDValue Src = N->getOperand(0);
1745 EVT SrcVT = Src.getValueType();
1747 // TODO: We could try to match extracting the higher bytes, which would be
1748 // easier if i8 vectors weren't promoted to i32 vectors, particularly after
1749 // types are legalized. v4i8 -> v4f32 is probably the only case to worry
1750 // about in practice.
1751 if (DCI.isAfterLegalizeVectorOps() && SrcVT == MVT::i32) {
1752 if (DAG.MaskedValueIsZero(Src, APInt::getHighBitsSet(32, 24))) {
1753 SDValue Cvt = DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Src);
1754 DCI.AddToWorklist(Cvt.getNode());
1759 // We are primarily trying to catch operations on illegal vector types
1760 // before they are expanded.
1761 // For scalars, we can use the more flexible method of checking masked bits
1762 // after legalization.
1763 if (!DCI.isBeforeLegalize() ||
1764 !SrcVT.isVector() ||
1765 SrcVT.getVectorElementType() != MVT::i8) {
1769 assert(DCI.isBeforeLegalize() && "Unexpected legal type");
1771 // Weird sized vectors are a pain to handle, but we know 3 is really the same
1773 unsigned NElts = SrcVT.getVectorNumElements();
1774 if (!SrcVT.isSimple() && NElts != 3)
1777 // Handle v4i8 -> v4f32 extload. Replace the v4i8 with a legal i32 load to
1778 // prevent a mess from expanding to v4i32 and repacking.
1779 if (ISD::isNormalLoad(Src.getNode()) && Src.hasOneUse()) {
1780 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), SrcVT);
1781 EVT RegVT = getEquivalentLoadRegType(*DAG.getContext(), SrcVT);
1782 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f32, NElts);
1783 LoadSDNode *Load = cast<LoadSDNode>(Src);
1785 unsigned AS = Load->getAddressSpace();
1786 unsigned Align = Load->getAlignment();
1787 Type *Ty = LoadVT.getTypeForEVT(*DAG.getContext());
1788 unsigned ABIAlignment = DAG.getDataLayout().getABITypeAlignment(Ty);
1790 // Don't try to replace the load if we have to expand it due to alignment
1791 // problems. Otherwise we will end up scalarizing the load, and trying to
1792 // repack into the vector for no real reason.
1793 if (Align < ABIAlignment &&
1794 !allowsMisalignedMemoryAccesses(LoadVT, AS, Align, nullptr)) {
1798 SDValue NewLoad = DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegVT,
1802 Load->getMemOperand());
1804 // Make sure successors of the original load stay after it by updating
1805 // them to use the new Chain.
1806 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), NewLoad.getValue(1));
1808 SmallVector<SDValue, 4> Elts;
1809 if (RegVT.isVector())
1810 DAG.ExtractVectorElements(NewLoad, Elts);
1812 Elts.push_back(NewLoad);
1814 SmallVector<SDValue, 4> Ops;
1816 unsigned EltIdx = 0;
1817 for (SDValue Elt : Elts) {
1818 unsigned ComponentsInElt = std::min(4u, NElts - 4 * EltIdx);
1819 for (unsigned I = 0; I < ComponentsInElt; ++I) {
1820 unsigned Opc = AMDGPUISD::CVT_F32_UBYTE0 + I;
1821 SDValue Cvt = DAG.getNode(Opc, DL, MVT::f32, Elt);
1822 DCI.AddToWorklist(Cvt.getNode());
1829 assert(Ops.size() == NElts);
1831 return DAG.getNode(ISD::BUILD_VECTOR, DL, FloatVT, Ops);
1837 /// \brief Return true if the given offset Size in bytes can be folded into
1838 /// the immediate offsets of a memory instruction for the given address space.
1839 static bool canFoldOffset(unsigned OffsetSize, unsigned AS,
1840 const AMDGPUSubtarget &STI) {
1842 case AMDGPUAS::GLOBAL_ADDRESS: {
1843 // MUBUF instructions a 12-bit offset in bytes.
1844 return isUInt<12>(OffsetSize);
1846 case AMDGPUAS::CONSTANT_ADDRESS: {
1847 // SMRD instructions have an 8-bit offset in dwords on SI and
1848 // a 20-bit offset in bytes on VI.
1849 if (STI.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1850 return isUInt<20>(OffsetSize);
1852 return (OffsetSize % 4 == 0) && isUInt<8>(OffsetSize / 4);
1854 case AMDGPUAS::LOCAL_ADDRESS:
1855 case AMDGPUAS::REGION_ADDRESS: {
1856 // The single offset versions have a 16-bit offset in bytes.
1857 return isUInt<16>(OffsetSize);
1859 case AMDGPUAS::PRIVATE_ADDRESS:
1860 // Indirect register addressing does not use any offsets.
1866 // (shl (add x, c1), c2) -> add (shl x, c2), (shl c1, c2)
1868 // This is a variant of
1869 // (mul (add x, c1), c2) -> add (mul x, c2), (mul c1, c2),
1871 // The normal DAG combiner will do this, but only if the add has one use since
1872 // that would increase the number of instructions.
1874 // This prevents us from seeing a constant offset that can be folded into a
1875 // memory instruction's addressing mode. If we know the resulting add offset of
1876 // a pointer can be folded into an addressing offset, we can replace the pointer
1877 // operand with the add of new constant offset. This eliminates one of the uses,
1878 // and may allow the remaining use to also be simplified.
1880 SDValue SITargetLowering::performSHLPtrCombine(SDNode *N,
1882 DAGCombinerInfo &DCI) const {
1883 SDValue N0 = N->getOperand(0);
1884 SDValue N1 = N->getOperand(1);
1886 if (N0.getOpcode() != ISD::ADD)
1889 const ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(N1);
1893 const ConstantSDNode *CAdd = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1897 // If the resulting offset is too large, we can't fold it into the addressing
1899 APInt Offset = CAdd->getAPIntValue() << CN1->getAPIntValue();
1900 if (!canFoldOffset(Offset.getZExtValue(), AddrSpace, *Subtarget))
1903 SelectionDAG &DAG = DCI.DAG;
1905 EVT VT = N->getValueType(0);
1907 SDValue ShlX = DAG.getNode(ISD::SHL, SL, VT, N0.getOperand(0), N1);
1908 SDValue COffset = DAG.getConstant(Offset, SL, MVT::i32);
1910 return DAG.getNode(ISD::ADD, SL, VT, ShlX, COffset);
1913 SDValue SITargetLowering::performAndCombine(SDNode *N,
1914 DAGCombinerInfo &DCI) const {
1915 if (DCI.isBeforeLegalize())
1918 SelectionDAG &DAG = DCI.DAG;
1920 // (and (fcmp ord x, x), (fcmp une (fabs x), inf)) ->
1921 // fp_class x, ~(s_nan | q_nan | n_infinity | p_infinity)
1922 SDValue LHS = N->getOperand(0);
1923 SDValue RHS = N->getOperand(1);
1925 if (LHS.getOpcode() == ISD::SETCC &&
1926 RHS.getOpcode() == ISD::SETCC) {
1927 ISD::CondCode LCC = cast<CondCodeSDNode>(LHS.getOperand(2))->get();
1928 ISD::CondCode RCC = cast<CondCodeSDNode>(RHS.getOperand(2))->get();
1930 SDValue X = LHS.getOperand(0);
1931 SDValue Y = RHS.getOperand(0);
1932 if (Y.getOpcode() != ISD::FABS || Y.getOperand(0) != X)
1935 if (LCC == ISD::SETO) {
1936 if (X != LHS.getOperand(1))
1939 if (RCC == ISD::SETUNE) {
1940 const ConstantFPSDNode *C1 = dyn_cast<ConstantFPSDNode>(RHS.getOperand(1));
1941 if (!C1 || !C1->isInfinity() || C1->isNegative())
1944 const uint32_t Mask = SIInstrFlags::N_NORMAL |
1945 SIInstrFlags::N_SUBNORMAL |
1946 SIInstrFlags::N_ZERO |
1947 SIInstrFlags::P_ZERO |
1948 SIInstrFlags::P_SUBNORMAL |
1949 SIInstrFlags::P_NORMAL;
1951 static_assert(((~(SIInstrFlags::S_NAN |
1952 SIInstrFlags::Q_NAN |
1953 SIInstrFlags::N_INFINITY |
1954 SIInstrFlags::P_INFINITY)) & 0x3ff) == Mask,
1958 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, MVT::i1,
1959 X, DAG.getConstant(Mask, DL, MVT::i32));
1967 SDValue SITargetLowering::performOrCombine(SDNode *N,
1968 DAGCombinerInfo &DCI) const {
1969 SelectionDAG &DAG = DCI.DAG;
1970 SDValue LHS = N->getOperand(0);
1971 SDValue RHS = N->getOperand(1);
1973 // or (fp_class x, c1), (fp_class x, c2) -> fp_class x, (c1 | c2)
1974 if (LHS.getOpcode() == AMDGPUISD::FP_CLASS &&
1975 RHS.getOpcode() == AMDGPUISD::FP_CLASS) {
1976 SDValue Src = LHS.getOperand(0);
1977 if (Src != RHS.getOperand(0))
1980 const ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(LHS.getOperand(1));
1981 const ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(RHS.getOperand(1));
1985 // Only 10 bits are used.
1986 static const uint32_t MaxMask = 0x3ff;
1988 uint32_t NewMask = (CLHS->getZExtValue() | CRHS->getZExtValue()) & MaxMask;
1990 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, MVT::i1,
1991 Src, DAG.getConstant(NewMask, DL, MVT::i32));
1997 SDValue SITargetLowering::performClassCombine(SDNode *N,
1998 DAGCombinerInfo &DCI) const {
1999 SelectionDAG &DAG = DCI.DAG;
2000 SDValue Mask = N->getOperand(1);
2002 // fp_class x, 0 -> false
2003 if (const ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(Mask)) {
2004 if (CMask->isNullValue())
2005 return DAG.getConstant(0, SDLoc(N), MVT::i1);
2011 static unsigned minMaxOpcToMin3Max3Opc(unsigned Opc) {
2014 return AMDGPUISD::FMAX3;
2016 return AMDGPUISD::SMAX3;
2018 return AMDGPUISD::UMAX3;
2020 return AMDGPUISD::FMIN3;
2022 return AMDGPUISD::SMIN3;
2024 return AMDGPUISD::UMIN3;
2026 llvm_unreachable("Not a min/max opcode");
2030 SDValue SITargetLowering::performMin3Max3Combine(SDNode *N,
2031 DAGCombinerInfo &DCI) const {
2032 SelectionDAG &DAG = DCI.DAG;
2034 unsigned Opc = N->getOpcode();
2035 SDValue Op0 = N->getOperand(0);
2036 SDValue Op1 = N->getOperand(1);
2038 // Only do this if the inner op has one use since this will just increases
2039 // register pressure for no benefit.
2041 // max(max(a, b), c)
2042 if (Op0.getOpcode() == Opc && Op0.hasOneUse()) {
2044 return DAG.getNode(minMaxOpcToMin3Max3Opc(Opc),
2052 // max(a, max(b, c))
2053 if (Op1.getOpcode() == Opc && Op1.hasOneUse()) {
2055 return DAG.getNode(minMaxOpcToMin3Max3Opc(Opc),
2066 SDValue SITargetLowering::performSetCCCombine(SDNode *N,
2067 DAGCombinerInfo &DCI) const {
2068 SelectionDAG &DAG = DCI.DAG;
2071 SDValue LHS = N->getOperand(0);
2072 SDValue RHS = N->getOperand(1);
2073 EVT VT = LHS.getValueType();
2075 if (VT != MVT::f32 && VT != MVT::f64)
2078 // Match isinf pattern
2079 // (fcmp oeq (fabs x), inf) -> (fp_class x, (p_infinity | n_infinity))
2080 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
2081 if (CC == ISD::SETOEQ && LHS.getOpcode() == ISD::FABS) {
2082 const ConstantFPSDNode *CRHS = dyn_cast<ConstantFPSDNode>(RHS);
2086 const APFloat &APF = CRHS->getValueAPF();
2087 if (APF.isInfinity() && !APF.isNegative()) {
2088 unsigned Mask = SIInstrFlags::P_INFINITY | SIInstrFlags::N_INFINITY;
2089 return DAG.getNode(AMDGPUISD::FP_CLASS, SL, MVT::i1, LHS.getOperand(0),
2090 DAG.getConstant(Mask, SL, MVT::i32));
2097 SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
2098 DAGCombinerInfo &DCI) const {
2099 SelectionDAG &DAG = DCI.DAG;
2102 switch (N->getOpcode()) {
2104 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
2106 return performSetCCCombine(N, DCI);
2107 case ISD::FMAXNUM: // TODO: What about fmax_legacy?
2113 if (DCI.getDAGCombineLevel() >= AfterLegalizeDAG &&
2114 N->getValueType(0) != MVT::f64 &&
2115 getTargetMachine().getOptLevel() > CodeGenOpt::None)
2116 return performMin3Max3Combine(N, DCI);
2120 case AMDGPUISD::CVT_F32_UBYTE0:
2121 case AMDGPUISD::CVT_F32_UBYTE1:
2122 case AMDGPUISD::CVT_F32_UBYTE2:
2123 case AMDGPUISD::CVT_F32_UBYTE3: {
2124 unsigned Offset = N->getOpcode() - AMDGPUISD::CVT_F32_UBYTE0;
2126 SDValue Src = N->getOperand(0);
2127 APInt Demanded = APInt::getBitsSet(32, 8 * Offset, 8 * Offset + 8);
2129 APInt KnownZero, KnownOne;
2130 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
2131 !DCI.isBeforeLegalizeOps());
2132 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2133 if (TLO.ShrinkDemandedConstant(Src, Demanded) ||
2134 TLI.SimplifyDemandedBits(Src, Demanded, KnownZero, KnownOne, TLO)) {
2135 DCI.CommitTargetLoweringOpt(TLO);
2141 case ISD::UINT_TO_FP: {
2142 return performUCharToFloatCombine(N, DCI);
2145 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
2148 EVT VT = N->getValueType(0);
2152 // Only do this if we are not trying to support denormals. v_mad_f32 does
2153 // not support denormals ever.
2154 if (Subtarget->hasFP32Denormals())
2157 SDValue LHS = N->getOperand(0);
2158 SDValue RHS = N->getOperand(1);
2160 // These should really be instruction patterns, but writing patterns with
2161 // source modiifiers is a pain.
2163 // fadd (fadd (a, a), b) -> mad 2.0, a, b
2164 if (LHS.getOpcode() == ISD::FADD) {
2165 SDValue A = LHS.getOperand(0);
2166 if (A == LHS.getOperand(1)) {
2167 const SDValue Two = DAG.getConstantFP(2.0, DL, MVT::f32);
2168 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, RHS);
2172 // fadd (b, fadd (a, a)) -> mad 2.0, a, b
2173 if (RHS.getOpcode() == ISD::FADD) {
2174 SDValue A = RHS.getOperand(0);
2175 if (A == RHS.getOperand(1)) {
2176 const SDValue Two = DAG.getConstantFP(2.0, DL, MVT::f32);
2177 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, LHS);
2184 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
2187 EVT VT = N->getValueType(0);
2189 // Try to get the fneg to fold into the source modifier. This undoes generic
2190 // DAG combines and folds them into the mad.
2192 // Only do this if we are not trying to support denormals. v_mad_f32 does
2193 // not support denormals ever.
2194 if (VT == MVT::f32 &&
2195 !Subtarget->hasFP32Denormals()) {
2196 SDValue LHS = N->getOperand(0);
2197 SDValue RHS = N->getOperand(1);
2198 if (LHS.getOpcode() == ISD::FADD) {
2199 // (fsub (fadd a, a), c) -> mad 2.0, a, (fneg c)
2201 SDValue A = LHS.getOperand(0);
2202 if (A == LHS.getOperand(1)) {
2203 const SDValue Two = DAG.getConstantFP(2.0, DL, MVT::f32);
2204 SDValue NegRHS = DAG.getNode(ISD::FNEG, DL, VT, RHS);
2206 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, NegRHS);
2210 if (RHS.getOpcode() == ISD::FADD) {
2211 // (fsub c, (fadd a, a)) -> mad -2.0, a, c
2213 SDValue A = RHS.getOperand(0);
2214 if (A == RHS.getOperand(1)) {
2215 const SDValue NegTwo = DAG.getConstantFP(-2.0, DL, MVT::f32);
2216 return DAG.getNode(ISD::FMAD, DL, VT, NegTwo, A, LHS);
2227 case ISD::ATOMIC_LOAD:
2228 case ISD::ATOMIC_STORE:
2229 case ISD::ATOMIC_CMP_SWAP:
2230 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
2231 case ISD::ATOMIC_SWAP:
2232 case ISD::ATOMIC_LOAD_ADD:
2233 case ISD::ATOMIC_LOAD_SUB:
2234 case ISD::ATOMIC_LOAD_AND:
2235 case ISD::ATOMIC_LOAD_OR:
2236 case ISD::ATOMIC_LOAD_XOR:
2237 case ISD::ATOMIC_LOAD_NAND:
2238 case ISD::ATOMIC_LOAD_MIN:
2239 case ISD::ATOMIC_LOAD_MAX:
2240 case ISD::ATOMIC_LOAD_UMIN:
2241 case ISD::ATOMIC_LOAD_UMAX: { // TODO: Target mem intrinsics.
2242 if (DCI.isBeforeLegalize())
2245 MemSDNode *MemNode = cast<MemSDNode>(N);
2246 SDValue Ptr = MemNode->getBasePtr();
2248 // TODO: We could also do this for multiplies.
2249 unsigned AS = MemNode->getAddressSpace();
2250 if (Ptr.getOpcode() == ISD::SHL && AS != AMDGPUAS::PRIVATE_ADDRESS) {
2251 SDValue NewPtr = performSHLPtrCombine(Ptr.getNode(), AS, DCI);
2253 SmallVector<SDValue, 8> NewOps(MemNode->op_begin(), MemNode->op_end());
2255 NewOps[N->getOpcode() == ISD::STORE ? 2 : 1] = NewPtr;
2256 return SDValue(DAG.UpdateNodeOperands(MemNode, NewOps), 0);
2262 return performAndCombine(N, DCI);
2264 return performOrCombine(N, DCI);
2265 case AMDGPUISD::FP_CLASS:
2266 return performClassCombine(N, DCI);
2268 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
2271 /// \brief Analyze the possible immediate value Op
2273 /// Returns -1 if it isn't an immediate, 0 if it's and inline immediate
2274 /// and the immediate value if it's a literal immediate
2275 int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
2277 const SIInstrInfo *TII =
2278 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
2280 if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N)) {
2281 if (TII->isInlineConstant(Node->getAPIntValue()))
2284 uint64_t Val = Node->getZExtValue();
2285 return isUInt<32>(Val) ? Val : -1;
2288 if (const ConstantFPSDNode *Node = dyn_cast<ConstantFPSDNode>(N)) {
2289 if (TII->isInlineConstant(Node->getValueAPF().bitcastToAPInt()))
2292 if (Node->getValueType(0) == MVT::f32)
2293 return FloatToBits(Node->getValueAPF().convertToFloat());
2301 /// \brief Helper function for adjustWritemask
2302 static unsigned SubIdx2Lane(unsigned Idx) {
2305 case AMDGPU::sub0: return 0;
2306 case AMDGPU::sub1: return 1;
2307 case AMDGPU::sub2: return 2;
2308 case AMDGPU::sub3: return 3;
2312 /// \brief Adjust the writemask of MIMG instructions
2313 void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
2314 SelectionDAG &DAG) const {
2315 SDNode *Users[4] = { };
2317 unsigned OldDmask = Node->getConstantOperandVal(0);
2318 unsigned NewDmask = 0;
2320 // Try to figure out the used register components
2321 for (SDNode::use_iterator I = Node->use_begin(), E = Node->use_end();
2324 // Abort if we can't understand the usage
2325 if (!I->isMachineOpcode() ||
2326 I->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG)
2329 // Lane means which subreg of %VGPRa_VGPRb_VGPRc_VGPRd is used.
2330 // Note that subregs are packed, i.e. Lane==0 is the first bit set
2331 // in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit
2333 Lane = SubIdx2Lane(I->getConstantOperandVal(1));
2335 // Set which texture component corresponds to the lane.
2337 for (unsigned i = 0, Dmask = OldDmask; i <= Lane; i++) {
2339 Comp = countTrailingZeros(Dmask);
2340 Dmask &= ~(1 << Comp);
2343 // Abort if we have more than one user per component
2348 NewDmask |= 1 << Comp;
2351 // Abort if there's no change
2352 if (NewDmask == OldDmask)
2355 // Adjust the writemask in the node
2356 std::vector<SDValue> Ops;
2357 Ops.push_back(DAG.getTargetConstant(NewDmask, SDLoc(Node), MVT::i32));
2358 Ops.insert(Ops.end(), Node->op_begin() + 1, Node->op_end());
2359 Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops);
2361 // If we only got one lane, replace it with a copy
2362 // (if NewDmask has only one bit set...)
2363 if (NewDmask && (NewDmask & (NewDmask-1)) == 0) {
2364 SDValue RC = DAG.getTargetConstant(AMDGPU::VGPR_32RegClassID, SDLoc(),
2366 SDNode *Copy = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
2367 SDLoc(), Users[Lane]->getValueType(0),
2368 SDValue(Node, 0), RC);
2369 DAG.ReplaceAllUsesWith(Users[Lane], Copy);
2373 // Update the users of the node with the new indices
2374 for (unsigned i = 0, Idx = AMDGPU::sub0; i < 4; ++i) {
2376 SDNode *User = Users[i];
2380 SDValue Op = DAG.getTargetConstant(Idx, SDLoc(User), MVT::i32);
2381 DAG.UpdateNodeOperands(User, User->getOperand(0), Op);
2385 case AMDGPU::sub0: Idx = AMDGPU::sub1; break;
2386 case AMDGPU::sub1: Idx = AMDGPU::sub2; break;
2387 case AMDGPU::sub2: Idx = AMDGPU::sub3; break;
2392 static bool isFrameIndexOp(SDValue Op) {
2393 if (Op.getOpcode() == ISD::AssertZext)
2394 Op = Op.getOperand(0);
2396 return isa<FrameIndexSDNode>(Op);
2399 /// \brief Legalize target independent instructions (e.g. INSERT_SUBREG)
2400 /// with frame index operands.
2401 /// LLVM assumes that inputs are to these instructions are registers.
2402 void SITargetLowering::legalizeTargetIndependentNode(SDNode *Node,
2403 SelectionDAG &DAG) const {
2405 SmallVector<SDValue, 8> Ops;
2406 for (unsigned i = 0; i < Node->getNumOperands(); ++i) {
2407 if (!isFrameIndexOp(Node->getOperand(i))) {
2408 Ops.push_back(Node->getOperand(i));
2413 Ops.push_back(SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL,
2414 Node->getOperand(i).getValueType(),
2415 Node->getOperand(i)), 0));
2418 DAG.UpdateNodeOperands(Node, Ops);
2421 /// \brief Fold the instructions after selecting them.
2422 SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
2423 SelectionDAG &DAG) const {
2424 const SIInstrInfo *TII =
2425 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
2427 if (TII->isMIMG(Node->getMachineOpcode()))
2428 adjustWritemask(Node, DAG);
2430 if (Node->getMachineOpcode() == AMDGPU::INSERT_SUBREG ||
2431 Node->getMachineOpcode() == AMDGPU::REG_SEQUENCE) {
2432 legalizeTargetIndependentNode(Node, DAG);
2438 /// \brief Assign the register class depending on the number of
2439 /// bits set in the writemask
2440 void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
2441 SDNode *Node) const {
2442 const SIInstrInfo *TII =
2443 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
2445 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
2447 if (TII->isVOP3(MI->getOpcode())) {
2448 // Make sure constant bus requirements are respected.
2449 TII->legalizeOperandsVOP3(MRI, MI);
2453 if (TII->isMIMG(*MI)) {
2454 unsigned VReg = MI->getOperand(0).getReg();
2455 unsigned Writemask = MI->getOperand(1).getImm();
2456 unsigned BitsSet = 0;
2457 for (unsigned i = 0; i < 4; ++i)
2458 BitsSet += Writemask & (1 << i) ? 1 : 0;
2460 const TargetRegisterClass *RC;
2463 case 1: RC = &AMDGPU::VGPR_32RegClass; break;
2464 case 2: RC = &AMDGPU::VReg_64RegClass; break;
2465 case 3: RC = &AMDGPU::VReg_96RegClass; break;
2468 unsigned NewOpcode = TII->getMaskedMIMGOp(MI->getOpcode(), BitsSet);
2469 MI->setDesc(TII->get(NewOpcode));
2470 MRI.setRegClass(VReg, RC);
2474 // Replace unused atomics with the no return version.
2475 int NoRetAtomicOp = AMDGPU::getAtomicNoRetOp(MI->getOpcode());
2476 if (NoRetAtomicOp != -1) {
2477 if (!Node->hasAnyUseOfValue(0)) {
2478 MI->setDesc(TII->get(NoRetAtomicOp));
2479 MI->RemoveOperand(0);
2486 static SDValue buildSMovImm32(SelectionDAG &DAG, SDLoc DL, uint64_t Val) {
2487 SDValue K = DAG.getTargetConstant(Val, DL, MVT::i32);
2488 return SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, K), 0);
2491 MachineSDNode *SITargetLowering::wrapAddr64Rsrc(SelectionDAG &DAG,
2493 SDValue Ptr) const {
2494 const SIInstrInfo *TII =
2495 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
2497 // Build the half of the subregister with the constants before building the
2498 // full 128-bit register. If we are building multiple resource descriptors,
2499 // this will allow CSEing of the 2-component register.
2500 const SDValue Ops0[] = {
2501 DAG.getTargetConstant(AMDGPU::SGPR_64RegClassID, DL, MVT::i32),
2502 buildSMovImm32(DAG, DL, 0),
2503 DAG.getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
2504 buildSMovImm32(DAG, DL, TII->getDefaultRsrcDataFormat() >> 32),
2505 DAG.getTargetConstant(AMDGPU::sub1, DL, MVT::i32)
2508 SDValue SubRegHi = SDValue(DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL,
2509 MVT::v2i32, Ops0), 0);
2511 // Combine the constants and the pointer.
2512 const SDValue Ops1[] = {
2513 DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32),
2515 DAG.getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32),
2517 DAG.getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32)
2520 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops1);
2523 /// \brief Return a resource descriptor with the 'Add TID' bit enabled
2524 /// The TID (Thread ID) is multiplied by the stride value (bits [61:48]
2525 /// of the resource descriptor) to create an offset, which is added to
2526 /// the resource pointer.
2527 MachineSDNode *SITargetLowering::buildRSRC(SelectionDAG &DAG,
2530 uint32_t RsrcDword1,
2531 uint64_t RsrcDword2And3) const {
2532 SDValue PtrLo = DAG.getTargetExtractSubreg(AMDGPU::sub0, DL, MVT::i32, Ptr);
2533 SDValue PtrHi = DAG.getTargetExtractSubreg(AMDGPU::sub1, DL, MVT::i32, Ptr);
2535 PtrHi = SDValue(DAG.getMachineNode(AMDGPU::S_OR_B32, DL, MVT::i32, PtrHi,
2536 DAG.getConstant(RsrcDword1, DL, MVT::i32)),
2540 SDValue DataLo = buildSMovImm32(DAG, DL,
2541 RsrcDword2And3 & UINT64_C(0xFFFFFFFF));
2542 SDValue DataHi = buildSMovImm32(DAG, DL, RsrcDword2And3 >> 32);
2544 const SDValue Ops[] = {
2545 DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32),
2547 DAG.getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
2549 DAG.getTargetConstant(AMDGPU::sub1, DL, MVT::i32),
2551 DAG.getTargetConstant(AMDGPU::sub2, DL, MVT::i32),
2553 DAG.getTargetConstant(AMDGPU::sub3, DL, MVT::i32)
2556 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops);
2559 SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2560 const TargetRegisterClass *RC,
2561 unsigned Reg, EVT VT) const {
2562 SDValue VReg = AMDGPUTargetLowering::CreateLiveInRegister(DAG, RC, Reg, VT);
2564 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(DAG.getEntryNode()),
2565 cast<RegisterSDNode>(VReg)->getReg(), VT);
2568 //===----------------------------------------------------------------------===//
2569 // SI Inline Assembly Support
2570 //===----------------------------------------------------------------------===//
2572 std::pair<unsigned, const TargetRegisterClass *>
2573 SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
2574 StringRef Constraint,
2577 if (Constraint.size() == 1) {
2578 switch (Constraint[0]) {
2581 switch (VT.getSizeInBits()) {
2583 return std::make_pair(0U, nullptr);
2585 return std::make_pair(0U, &AMDGPU::SGPR_32RegClass);
2587 return std::make_pair(0U, &AMDGPU::SGPR_64RegClass);
2589 return std::make_pair(0U, &AMDGPU::SReg_128RegClass);
2591 return std::make_pair(0U, &AMDGPU::SReg_256RegClass);
2595 switch (VT.getSizeInBits()) {
2597 return std::make_pair(0U, nullptr);
2599 return std::make_pair(0U, &AMDGPU::VGPR_32RegClass);
2601 return std::make_pair(0U, &AMDGPU::VReg_64RegClass);
2603 return std::make_pair(0U, &AMDGPU::VReg_96RegClass);
2605 return std::make_pair(0U, &AMDGPU::VReg_128RegClass);
2607 return std::make_pair(0U, &AMDGPU::VReg_256RegClass);
2609 return std::make_pair(0U, &AMDGPU::VReg_512RegClass);
2614 if (Constraint.size() > 1) {
2615 const TargetRegisterClass *RC = nullptr;
2616 if (Constraint[1] == 'v') {
2617 RC = &AMDGPU::VGPR_32RegClass;
2618 } else if (Constraint[1] == 's') {
2619 RC = &AMDGPU::SGPR_32RegClass;
2624 bool Failed = Constraint.substr(2).getAsInteger(10, Idx);
2625 if (!Failed && Idx < RC->getNumRegs())
2626 return std::make_pair(RC->getRegister(Idx), RC);
2629 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
2632 SITargetLowering::ConstraintType
2633 SITargetLowering::getConstraintType(StringRef Constraint) const {
2634 if (Constraint.size() == 1) {
2635 switch (Constraint[0]) {
2639 return C_RegisterClass;
2642 return TargetLowering::getConstraintType(Constraint);