1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "ScheduleDAGSDNodes.h"
17 #include "SelectionDAGBuilder.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/TargetTransformInfo.h"
23 #include "llvm/CodeGen/FastISel.h"
24 #include "llvm/CodeGen/FunctionLoweringInfo.h"
25 #include "llvm/CodeGen/GCMetadata.h"
26 #include "llvm/CodeGen/GCStrategy.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
33 #include "llvm/CodeGen/SchedulerRegistry.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/DebugInfo.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/InlineAsm.h"
39 #include "llvm/IR/Instructions.h"
40 #include "llvm/IR/IntrinsicInst.h"
41 #include "llvm/IR/Intrinsics.h"
42 #include "llvm/IR/LLVMContext.h"
43 #include "llvm/IR/Module.h"
44 #include "llvm/Support/Compiler.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/Timer.h"
48 #include "llvm/Support/raw_ostream.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetIntrinsicInfo.h"
51 #include "llvm/Target/TargetLibraryInfo.h"
52 #include "llvm/Target/TargetLowering.h"
53 #include "llvm/Target/TargetMachine.h"
54 #include "llvm/Target/TargetOptions.h"
55 #include "llvm/Target/TargetRegisterInfo.h"
56 #include "llvm/Target/TargetSubtargetInfo.h"
57 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
61 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
62 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
63 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
64 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
65 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
69 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
70 cl::desc("Enable extra verbose messages in the \"fast\" "
71 "instruction selector"));
73 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
74 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
75 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
76 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
77 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
78 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
79 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
81 // Standard binary operators...
82 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
83 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
84 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
85 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
86 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
87 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
88 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
89 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
90 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
91 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
92 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
93 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
95 // Logical operators...
96 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
97 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
98 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
100 // Memory instructions...
101 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
102 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
103 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
104 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
105 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
106 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
107 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
109 // Convert instructions...
110 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
111 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
112 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
113 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
114 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
115 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
116 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
117 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
118 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
119 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
120 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
121 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
123 // Other instructions...
124 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
125 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
126 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
127 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
128 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
129 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
130 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
131 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
132 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
133 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
134 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
135 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
136 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
137 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
138 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
142 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
143 cl::desc("Enable verbose messages in the \"fast\" "
144 "instruction selector"));
146 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
147 cl::desc("Enable abort calls when \"fast\" instruction fails"));
149 EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden,
150 cl::desc("Enable abort calls when \"fast\" instruction fails to "
151 "lower formal arguments"));
155 cl::desc("use Machine Branch Probability Info"),
156 cl::init(true), cl::Hidden);
160 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
161 cl::desc("Pop up a window to show dags before the first "
162 "dag combine pass"));
164 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
165 cl::desc("Pop up a window to show dags before legalize types"));
167 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
168 cl::desc("Pop up a window to show dags before legalize"));
170 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
171 cl::desc("Pop up a window to show dags before the second "
172 "dag combine pass"));
174 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
175 cl::desc("Pop up a window to show dags before the post legalize types"
176 " dag combine pass"));
178 ViewISelDAGs("view-isel-dags", cl::Hidden,
179 cl::desc("Pop up a window to show isel dags as they are selected"));
181 ViewSchedDAGs("view-sched-dags", cl::Hidden,
182 cl::desc("Pop up a window to show sched dags as they are processed"));
184 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
185 cl::desc("Pop up a window to show SUnit dags after they are processed"));
187 static const bool ViewDAGCombine1 = false,
188 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
189 ViewDAGCombine2 = false,
190 ViewDAGCombineLT = false,
191 ViewISelDAGs = false, ViewSchedDAGs = false,
192 ViewSUnitDAGs = false;
195 //===---------------------------------------------------------------------===//
197 /// RegisterScheduler class - Track the registration of instruction schedulers.
199 //===---------------------------------------------------------------------===//
200 MachinePassRegistry RegisterScheduler::Registry;
202 //===---------------------------------------------------------------------===//
204 /// ISHeuristic command line option for instruction schedulers.
206 //===---------------------------------------------------------------------===//
207 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
208 RegisterPassParser<RegisterScheduler> >
209 ISHeuristic("pre-RA-sched",
210 cl::init(&createDefaultScheduler),
211 cl::desc("Instruction schedulers available (before register"
214 static RegisterScheduler
215 defaultListDAGScheduler("default", "Best scheduler for the target",
216 createDefaultScheduler);
219 //===--------------------------------------------------------------------===//
220 /// createDefaultScheduler - This creates an instruction scheduler appropriate
222 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
223 CodeGenOpt::Level OptLevel) {
224 const TargetLowering &TLI = IS->getTargetLowering();
225 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>();
227 if (OptLevel == CodeGenOpt::None || ST.enableMachineScheduler() ||
228 TLI.getSchedulingPreference() == Sched::Source)
229 return createSourceListDAGScheduler(IS, OptLevel);
230 if (TLI.getSchedulingPreference() == Sched::RegPressure)
231 return createBURRListDAGScheduler(IS, OptLevel);
232 if (TLI.getSchedulingPreference() == Sched::Hybrid)
233 return createHybridListDAGScheduler(IS, OptLevel);
234 if (TLI.getSchedulingPreference() == Sched::VLIW)
235 return createVLIWDAGScheduler(IS, OptLevel);
236 assert(TLI.getSchedulingPreference() == Sched::ILP &&
237 "Unknown sched type!");
238 return createILPListDAGScheduler(IS, OptLevel);
242 // EmitInstrWithCustomInserter - This method should be implemented by targets
243 // that mark instructions with the 'usesCustomInserter' flag. These
244 // instructions are special in various ways, which require special support to
245 // insert. The specified MachineInstr is created but not inserted into any
246 // basic blocks, and this method is called to expand it into a sequence of
247 // instructions, potentially also creating new basic blocks and control flow.
248 // When new basic blocks are inserted and the edges from MBB to its successors
249 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
252 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
253 MachineBasicBlock *MBB) const {
255 dbgs() << "If a target marks an instruction with "
256 "'usesCustomInserter', it must implement "
257 "TargetLowering::EmitInstrWithCustomInserter!";
262 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
263 SDNode *Node) const {
264 assert(!MI->hasPostISelHook() &&
265 "If a target marks an instruction with 'hasPostISelHook', "
266 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
269 //===----------------------------------------------------------------------===//
270 // SelectionDAGISel code
271 //===----------------------------------------------------------------------===//
273 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm,
274 CodeGenOpt::Level OL) :
275 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
276 FuncInfo(new FunctionLoweringInfo(TLI)),
277 CurDAG(new SelectionDAG(tm, OL)),
278 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
282 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
283 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
284 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
285 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry());
288 SelectionDAGISel::~SelectionDAGISel() {
294 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
295 AU.addRequired<AliasAnalysis>();
296 AU.addPreserved<AliasAnalysis>();
297 AU.addRequired<GCModuleInfo>();
298 AU.addPreserved<GCModuleInfo>();
299 AU.addRequired<TargetLibraryInfo>();
300 if (UseMBPI && OptLevel != CodeGenOpt::None)
301 AU.addRequired<BranchProbabilityInfo>();
302 MachineFunctionPass::getAnalysisUsage(AU);
305 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
306 /// may trap on it. In this case we have to split the edge so that the path
307 /// through the predecessor block that doesn't go to the phi block doesn't
308 /// execute the possibly trapping instruction.
310 /// This is required for correctness, so it must be done at -O0.
312 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
313 // Loop for blocks with phi nodes.
314 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
315 PHINode *PN = dyn_cast<PHINode>(BB->begin());
316 if (PN == 0) continue;
319 // For each block with a PHI node, check to see if any of the input values
320 // are potentially trapping constant expressions. Constant expressions are
321 // the only potentially trapping value that can occur as the argument to a
323 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
324 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
325 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
326 if (CE == 0 || !CE->canTrap()) continue;
328 // The only case we have to worry about is when the edge is critical.
329 // Since this block has a PHI Node, we assume it has multiple input
330 // edges: check to see if the pred has multiple successors.
331 BasicBlock *Pred = PN->getIncomingBlock(i);
332 if (Pred->getTerminator()->getNumSuccessors() == 1)
335 // Okay, we have to split this edge.
336 SplitCriticalEdge(Pred->getTerminator(),
337 GetSuccessorNumber(Pred, BB), SDISel, true);
343 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
344 // Do some sanity-checking on the command-line options.
345 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
346 "-fast-isel-verbose requires -fast-isel");
347 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
348 "-fast-isel-abort requires -fast-isel");
350 const Function &Fn = *mf.getFunction();
351 const TargetInstrInfo &TII = *TM.getInstrInfo();
352 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
355 RegInfo = &MF->getRegInfo();
356 AA = &getAnalysis<AliasAnalysis>();
357 LibInfo = &getAnalysis<TargetLibraryInfo>();
358 TTI = getAnalysisIfAvailable<TargetTransformInfo>();
359 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
361 TargetSubtargetInfo &ST =
362 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>());
363 ST.resetSubtargetFeatures(MF);
365 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
367 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
369 CurDAG->init(*MF, TTI);
370 FuncInfo->set(Fn, *MF);
372 if (UseMBPI && OptLevel != CodeGenOpt::None)
373 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
377 SDB->init(GFI, *AA, LibInfo);
379 MF->setHasMSInlineAsm(false);
380 SelectAllBasicBlocks(Fn);
382 // If the first basic block in the function has live ins that need to be
383 // copied into vregs, emit the copies into the top of the block before
384 // emitting the code for the block.
385 MachineBasicBlock *EntryMBB = MF->begin();
386 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
388 DenseMap<unsigned, unsigned> LiveInMap;
389 if (!FuncInfo->ArgDbgValues.empty())
390 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
391 E = RegInfo->livein_end(); LI != E; ++LI)
393 LiveInMap.insert(std::make_pair(LI->first, LI->second));
395 // Insert DBG_VALUE instructions for function arguments to the entry block.
396 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
397 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
398 unsigned Reg = MI->getOperand(0).getReg();
399 if (TargetRegisterInfo::isPhysicalRegister(Reg))
400 EntryMBB->insert(EntryMBB->begin(), MI);
402 MachineInstr *Def = RegInfo->getVRegDef(Reg);
403 MachineBasicBlock::iterator InsertPos = Def;
404 // FIXME: VR def may not be in entry block.
405 Def->getParent()->insert(llvm::next(InsertPos), MI);
408 // If Reg is live-in then update debug info to track its copy in a vreg.
409 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
410 if (LDI != LiveInMap.end()) {
411 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
412 MachineBasicBlock::iterator InsertPos = Def;
413 const MDNode *Variable =
414 MI->getOperand(MI->getNumOperands()-1).getMetadata();
415 unsigned Offset = MI->getOperand(1).getImm();
416 // Def is never a terminator here, so it is ok to increment InsertPos.
417 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
418 TII.get(TargetOpcode::DBG_VALUE))
419 .addReg(LDI->second, RegState::Debug)
420 .addImm(Offset).addMetadata(Variable);
422 // If this vreg is directly copied into an exported register then
423 // that COPY instructions also need DBG_VALUE, if it is the only
424 // user of LDI->second.
425 MachineInstr *CopyUseMI = NULL;
426 for (MachineRegisterInfo::use_iterator
427 UI = RegInfo->use_begin(LDI->second);
428 MachineInstr *UseMI = UI.skipInstruction();) {
429 if (UseMI->isDebugValue()) continue;
430 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
431 CopyUseMI = UseMI; continue;
433 // Otherwise this is another use or second copy use.
434 CopyUseMI = NULL; break;
437 MachineInstr *NewMI =
438 BuildMI(*MF, CopyUseMI->getDebugLoc(),
439 TII.get(TargetOpcode::DBG_VALUE))
440 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
441 .addImm(Offset).addMetadata(Variable);
442 MachineBasicBlock::iterator Pos = CopyUseMI;
443 EntryMBB->insertAfter(Pos, NewMI);
448 // Determine if there are any calls in this machine function.
449 MachineFrameInfo *MFI = MF->getFrameInfo();
450 for (MachineFunction::const_iterator I = MF->begin(), E = MF->end(); I != E;
453 if (MFI->hasCalls() && MF->hasMSInlineAsm())
456 const MachineBasicBlock *MBB = I;
457 for (MachineBasicBlock::const_iterator II = MBB->begin(), IE = MBB->end();
459 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
460 if ((MCID.isCall() && !MCID.isReturn()) ||
461 II->isStackAligningInlineAsm()) {
462 MFI->setHasCalls(true);
464 if (II->isMSInlineAsm()) {
465 MF->setHasMSInlineAsm(true);
470 // Determine if there is a call to setjmp in the machine function.
471 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
473 // Replace forward-declared registers with the registers containing
474 // the desired value.
475 MachineRegisterInfo &MRI = MF->getRegInfo();
476 for (DenseMap<unsigned, unsigned>::iterator
477 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
479 unsigned From = I->first;
480 unsigned To = I->second;
481 // If To is also scheduled to be replaced, find what its ultimate
484 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
489 MRI.replaceRegWith(From, To);
492 // Freeze the set of reserved registers now that MachineFrameInfo has been
493 // set up. All the information required by getReservedRegs() should be
495 MRI.freezeReservedRegs(*MF);
497 // Release function-specific state. SDB and CurDAG are already cleared
504 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
505 BasicBlock::const_iterator End,
507 // Lower all of the non-terminator instructions. If a call is emitted
508 // as a tail call, cease emitting nodes for this block. Terminators
509 // are handled below.
510 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
513 // Make sure the root of the DAG is up-to-date.
514 CurDAG->setRoot(SDB->getControlRoot());
515 HadTailCall = SDB->HasTailCall;
518 // Final step, emit the lowered DAG as machine code.
522 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
523 SmallPtrSet<SDNode*, 128> VisitedNodes;
524 SmallVector<SDNode*, 128> Worklist;
526 Worklist.push_back(CurDAG->getRoot().getNode());
532 SDNode *N = Worklist.pop_back_val();
534 // If we've already seen this node, ignore it.
535 if (!VisitedNodes.insert(N))
538 // Otherwise, add all chain operands to the worklist.
539 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
540 if (N->getOperand(i).getValueType() == MVT::Other)
541 Worklist.push_back(N->getOperand(i).getNode());
543 // If this is a CopyToReg with a vreg dest, process it.
544 if (N->getOpcode() != ISD::CopyToReg)
547 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
548 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
551 // Ignore non-scalar or non-integer values.
552 SDValue Src = N->getOperand(2);
553 EVT SrcVT = Src.getValueType();
554 if (!SrcVT.isInteger() || SrcVT.isVector())
557 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
558 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne);
559 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
560 } while (!Worklist.empty());
563 void SelectionDAGISel::CodeGenAndEmitDAG() {
564 std::string GroupName;
565 if (TimePassesIsEnabled)
566 GroupName = "Instruction Selection and Scheduling";
567 std::string BlockName;
568 int BlockNumber = -1;
571 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
572 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
576 BlockNumber = FuncInfo->MBB->getNumber();
577 BlockName = MF->getName().str() + ":" +
578 FuncInfo->MBB->getBasicBlock()->getName().str();
580 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
581 << " '" << BlockName << "'\n"; CurDAG->dump());
583 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
585 // Run the DAG combiner in pre-legalize mode.
587 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
588 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
591 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
592 << " '" << BlockName << "'\n"; CurDAG->dump());
594 // Second step, hack on the DAG until it only uses operations and types that
595 // the target supports.
596 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
601 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
602 Changed = CurDAG->LegalizeTypes();
605 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
606 << " '" << BlockName << "'\n"; CurDAG->dump());
609 if (ViewDAGCombineLT)
610 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
612 // Run the DAG combiner in post-type-legalize mode.
614 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
615 TimePassesIsEnabled);
616 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
619 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
620 << " '" << BlockName << "'\n"; CurDAG->dump());
624 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
625 Changed = CurDAG->LegalizeVectors();
630 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
631 CurDAG->LegalizeTypes();
634 if (ViewDAGCombineLT)
635 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
637 // Run the DAG combiner in post-type-legalize mode.
639 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
640 TimePassesIsEnabled);
641 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
644 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
645 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
648 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
651 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
655 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
656 << " '" << BlockName << "'\n"; CurDAG->dump());
658 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
660 // Run the DAG combiner in post-legalize mode.
662 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
663 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
666 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
667 << " '" << BlockName << "'\n"; CurDAG->dump());
669 if (OptLevel != CodeGenOpt::None)
670 ComputeLiveOutVRegInfo();
672 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
674 // Third, instruction select all of the operations to machine code, adding the
675 // code to the MachineBasicBlock.
677 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
678 DoInstructionSelection();
681 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
682 << " '" << BlockName << "'\n"; CurDAG->dump());
684 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
686 // Schedule machine code.
687 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
689 NamedRegionTimer T("Instruction Scheduling", GroupName,
690 TimePassesIsEnabled);
691 Scheduler->Run(CurDAG, FuncInfo->MBB);
694 if (ViewSUnitDAGs) Scheduler->viewGraph();
696 // Emit machine code to BB. This can change 'BB' to the last block being
698 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
700 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
702 // FuncInfo->InsertPt is passed by reference and set to the end of the
703 // scheduled instructions.
704 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
707 // If the block was split, make sure we update any references that are used to
708 // update PHI nodes later on.
709 if (FirstMBB != LastMBB)
710 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
712 // Free the scheduler state.
714 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
715 TimePassesIsEnabled);
719 // Free the SelectionDAG state, now that we're finished with it.
724 /// ISelUpdater - helper class to handle updates of the instruction selection
726 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
727 SelectionDAG::allnodes_iterator &ISelPosition;
729 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
730 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
732 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
733 /// deleted is the current ISelPosition node, update ISelPosition.
735 virtual void NodeDeleted(SDNode *N, SDNode *E) {
736 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
740 } // end anonymous namespace
742 void SelectionDAGISel::DoInstructionSelection() {
743 DEBUG(errs() << "===== Instruction selection begins: BB#"
744 << FuncInfo->MBB->getNumber()
745 << " '" << FuncInfo->MBB->getName() << "'\n");
749 // Select target instructions for the DAG.
751 // Number all nodes with a topological order and set DAGSize.
752 DAGSize = CurDAG->AssignTopologicalOrder();
754 // Create a dummy node (which is not added to allnodes), that adds
755 // a reference to the root node, preventing it from being deleted,
756 // and tracking any changes of the root.
757 HandleSDNode Dummy(CurDAG->getRoot());
758 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
761 // Make sure that ISelPosition gets properly updated when nodes are deleted
762 // in calls made from this function.
763 ISelUpdater ISU(*CurDAG, ISelPosition);
765 // The AllNodes list is now topological-sorted. Visit the
766 // nodes by starting at the end of the list (the root of the
767 // graph) and preceding back toward the beginning (the entry
769 while (ISelPosition != CurDAG->allnodes_begin()) {
770 SDNode *Node = --ISelPosition;
771 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
772 // but there are currently some corner cases that it misses. Also, this
773 // makes it theoretically possible to disable the DAGCombiner.
774 if (Node->use_empty())
777 SDNode *ResNode = Select(Node);
779 // FIXME: This is pretty gross. 'Select' should be changed to not return
780 // anything at all and this code should be nuked with a tactical strike.
782 // If node should not be replaced, continue with the next one.
783 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
787 ReplaceUses(Node, ResNode);
789 // If after the replacement this node is not used any more,
790 // remove this dead node.
791 if (Node->use_empty()) // Don't delete EntryToken, etc.
792 CurDAG->RemoveDeadNode(Node);
795 CurDAG->setRoot(Dummy.getValue());
798 DEBUG(errs() << "===== Instruction selection ends:\n");
800 PostprocessISelDAG();
803 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
804 /// do other setup for EH landing-pad blocks.
805 void SelectionDAGISel::PrepareEHLandingPad() {
806 MachineBasicBlock *MBB = FuncInfo->MBB;
808 // Add a label to mark the beginning of the landing pad. Deletion of the
809 // landing pad can thus be detected via the MachineModuleInfo.
810 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
812 // Assign the call site to the landing pad's begin label.
813 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
815 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
816 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
819 // Mark exception register as live in.
820 unsigned Reg = TLI.getExceptionPointerRegister();
821 if (Reg) MBB->addLiveIn(Reg);
823 // Mark exception selector register as live in.
824 Reg = TLI.getExceptionSelectorRegister();
825 if (Reg) MBB->addLiveIn(Reg);
828 /// TryToFoldFastISelLoad - We're checking to see if we can fold the specified
829 /// load into the specified FoldInst. Note that we could have a sequence where
830 /// multiple LLVM IR instructions are folded into the same machineinstr. For
831 /// example we could have:
832 /// A: x = load i32 *P
833 /// B: y = icmp A, 42
836 /// In this scenario, LI is "A", and FoldInst is "C". We know about "B" (and
837 /// any other folded instructions) because it is between A and C.
839 /// If we succeed in folding the load into the operation, return true.
841 bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI,
842 const Instruction *FoldInst,
844 // We know that the load has a single use, but don't know what it is. If it
845 // isn't one of the folded instructions, then we can't succeed here. Handle
846 // this by scanning the single-use users of the load until we get to FoldInst.
847 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
849 const Instruction *TheUser = LI->use_back();
850 while (TheUser != FoldInst && // Scan up until we find FoldInst.
851 // Stay in the right block.
852 TheUser->getParent() == FoldInst->getParent() &&
853 --MaxUsers) { // Don't scan too far.
854 // If there are multiple or no uses of this instruction, then bail out.
855 if (!TheUser->hasOneUse())
858 TheUser = TheUser->use_back();
861 // If we didn't find the fold instruction, then we failed to collapse the
863 if (TheUser != FoldInst)
866 // Don't try to fold volatile loads. Target has to deal with alignment
868 if (LI->isVolatile()) return false;
870 // Figure out which vreg this is going into. If there is no assigned vreg yet
871 // then there actually was no reference to it. Perhaps the load is referenced
872 // by a dead instruction.
873 unsigned LoadReg = FastIS->getRegForValue(LI);
877 // Check to see what the uses of this vreg are. If it has no uses, or more
878 // than one use (at the machine instr level) then we can't fold it.
879 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg);
880 if (RI == RegInfo->reg_end())
883 // See if there is exactly one use of the vreg. If there are multiple uses,
884 // then the instruction got lowered to multiple machine instructions or the
885 // use of the loaded value ended up being multiple operands of the result, in
886 // either case, we can't fold this.
887 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI;
888 if (PostRI != RegInfo->reg_end())
891 assert(RI.getOperand().isUse() &&
892 "The only use of the vreg must be a use, we haven't emitted the def!");
894 MachineInstr *User = &*RI;
896 // Set the insertion point properly. Folding the load can cause generation of
897 // other random instructions (like sign extends) for addressing modes, make
898 // sure they get inserted in a logical place before the new instruction.
899 FuncInfo->InsertPt = User;
900 FuncInfo->MBB = User->getParent();
902 // Ask the target to try folding the load.
903 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI);
906 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
907 /// side-effect free and is either dead or folded into a generated instruction.
908 /// Return false if it needs to be emitted.
909 static bool isFoldedOrDeadInstruction(const Instruction *I,
910 FunctionLoweringInfo *FuncInfo) {
911 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
912 !isa<TerminatorInst>(I) && // Terminators aren't folded.
913 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
914 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
915 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
919 // Collect per Instruction statistics for fast-isel misses. Only those
920 // instructions that cause the bail are accounted for. It does not account for
921 // instructions higher in the block. Thus, summing the per instructions stats
922 // will not add up to what is reported by NumFastIselFailures.
923 static void collectFailStats(const Instruction *I) {
924 switch (I->getOpcode()) {
925 default: assert (0 && "<Invalid operator> ");
928 case Instruction::Ret: NumFastIselFailRet++; return;
929 case Instruction::Br: NumFastIselFailBr++; return;
930 case Instruction::Switch: NumFastIselFailSwitch++; return;
931 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
932 case Instruction::Invoke: NumFastIselFailInvoke++; return;
933 case Instruction::Resume: NumFastIselFailResume++; return;
934 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
936 // Standard binary operators...
937 case Instruction::Add: NumFastIselFailAdd++; return;
938 case Instruction::FAdd: NumFastIselFailFAdd++; return;
939 case Instruction::Sub: NumFastIselFailSub++; return;
940 case Instruction::FSub: NumFastIselFailFSub++; return;
941 case Instruction::Mul: NumFastIselFailMul++; return;
942 case Instruction::FMul: NumFastIselFailFMul++; return;
943 case Instruction::UDiv: NumFastIselFailUDiv++; return;
944 case Instruction::SDiv: NumFastIselFailSDiv++; return;
945 case Instruction::FDiv: NumFastIselFailFDiv++; return;
946 case Instruction::URem: NumFastIselFailURem++; return;
947 case Instruction::SRem: NumFastIselFailSRem++; return;
948 case Instruction::FRem: NumFastIselFailFRem++; return;
950 // Logical operators...
951 case Instruction::And: NumFastIselFailAnd++; return;
952 case Instruction::Or: NumFastIselFailOr++; return;
953 case Instruction::Xor: NumFastIselFailXor++; return;
955 // Memory instructions...
956 case Instruction::Alloca: NumFastIselFailAlloca++; return;
957 case Instruction::Load: NumFastIselFailLoad++; return;
958 case Instruction::Store: NumFastIselFailStore++; return;
959 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
960 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
961 case Instruction::Fence: NumFastIselFailFence++; return;
962 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
964 // Convert instructions...
965 case Instruction::Trunc: NumFastIselFailTrunc++; return;
966 case Instruction::ZExt: NumFastIselFailZExt++; return;
967 case Instruction::SExt: NumFastIselFailSExt++; return;
968 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
969 case Instruction::FPExt: NumFastIselFailFPExt++; return;
970 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
971 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
972 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
973 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
974 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
975 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
976 case Instruction::BitCast: NumFastIselFailBitCast++; return;
978 // Other instructions...
979 case Instruction::ICmp: NumFastIselFailICmp++; return;
980 case Instruction::FCmp: NumFastIselFailFCmp++; return;
981 case Instruction::PHI: NumFastIselFailPHI++; return;
982 case Instruction::Select: NumFastIselFailSelect++; return;
983 case Instruction::Call: NumFastIselFailCall++; return;
984 case Instruction::Shl: NumFastIselFailShl++; return;
985 case Instruction::LShr: NumFastIselFailLShr++; return;
986 case Instruction::AShr: NumFastIselFailAShr++; return;
987 case Instruction::VAArg: NumFastIselFailVAArg++; return;
988 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
989 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
990 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
991 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
992 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
993 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
998 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
999 // Initialize the Fast-ISel state, if needed.
1000 FastISel *FastIS = 0;
1001 if (TM.Options.EnableFastISel)
1002 FastIS = TLI.createFastISel(*FuncInfo, LibInfo);
1004 // Iterate over all basic blocks in the function.
1005 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
1006 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
1007 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
1008 const BasicBlock *LLVMBB = *I;
1010 if (OptLevel != CodeGenOpt::None) {
1011 bool AllPredsVisited = true;
1012 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1014 if (!FuncInfo->VisitedBBs.count(*PI)) {
1015 AllPredsVisited = false;
1020 if (AllPredsVisited) {
1021 for (BasicBlock::const_iterator I = LLVMBB->begin();
1022 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1023 FuncInfo->ComputePHILiveOutRegInfo(PN);
1025 for (BasicBlock::const_iterator I = LLVMBB->begin();
1026 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1027 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1030 FuncInfo->VisitedBBs.insert(LLVMBB);
1033 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1034 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1036 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1037 BasicBlock::const_iterator const End = LLVMBB->end();
1038 BasicBlock::const_iterator BI = End;
1040 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1042 // Setup an EH landing-pad block.
1043 if (FuncInfo->MBB->isLandingPad())
1044 PrepareEHLandingPad();
1046 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1048 FastIS->startNewBlock();
1050 // Emit code for any incoming arguments. This must happen before
1051 // beginning FastISel on the entry block.
1052 if (LLVMBB == &Fn.getEntryBlock()) {
1053 // Lower any arguments needed in this block if this is the entry block.
1054 if (!FastIS->LowerArguments()) {
1056 if (EnableFastISelAbortArgs)
1057 // The "fast" selector couldn't lower these arguments. For the
1058 // purpose of debugging, just abort.
1059 llvm_unreachable("FastISel didn't lower all arguments");
1061 // Call target indepedent SDISel argument lowering code if the target
1062 // specific routine is not successful.
1063 LowerArguments(LLVMBB);
1064 CurDAG->setRoot(SDB->getControlRoot());
1066 CodeGenAndEmitDAG();
1069 // If we inserted any instructions at the beginning, make a note of
1070 // where they are, so we can be sure to emit subsequent instructions
1072 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1073 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
1075 FastIS->setLastLocalValue(0);
1078 unsigned NumFastIselRemaining = std::distance(Begin, End);
1079 // Do FastISel on as many instructions as possible.
1080 for (; BI != Begin; --BI) {
1081 const Instruction *Inst = llvm::prior(BI);
1083 // If we no longer require this instruction, skip it.
1084 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1085 --NumFastIselRemaining;
1089 // Bottom-up: reset the insert pos at the top, after any local-value
1091 FastIS->recomputeInsertPt();
1093 // Try to select the instruction with FastISel.
1094 if (FastIS->SelectInstruction(Inst)) {
1095 --NumFastIselRemaining;
1096 ++NumFastIselSuccess;
1097 // If fast isel succeeded, skip over all the folded instructions, and
1098 // then see if there is a load right before the selected instructions.
1099 // Try to fold the load if so.
1100 const Instruction *BeforeInst = Inst;
1101 while (BeforeInst != Begin) {
1102 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst));
1103 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1106 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1107 BeforeInst->hasOneUse() &&
1108 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS)) {
1109 // If we succeeded, don't re-select the load.
1110 BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
1111 --NumFastIselRemaining;
1112 ++NumFastIselSuccess;
1118 if (EnableFastISelVerbose2)
1119 collectFailStats(Inst);
1122 // Then handle certain instructions as single-LLVM-Instruction blocks.
1123 if (isa<CallInst>(Inst)) {
1125 if (EnableFastISelVerbose || EnableFastISelAbort) {
1126 dbgs() << "FastISel missed call: ";
1130 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1131 unsigned &R = FuncInfo->ValueMap[Inst];
1133 R = FuncInfo->CreateRegs(Inst->getType());
1136 bool HadTailCall = false;
1137 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1138 SelectBasicBlock(Inst, BI, HadTailCall);
1140 // If the call was emitted as a tail call, we're done with the block.
1141 // We also need to delete any previously emitted instructions.
1143 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1148 // Recompute NumFastIselRemaining as Selection DAG instruction
1149 // selection may have handled the call, input args, etc.
1150 unsigned RemainingNow = std::distance(Begin, BI);
1151 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1152 NumFastIselRemaining = RemainingNow;
1156 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
1157 // Don't abort, and use a different message for terminator misses.
1158 NumFastIselFailures += NumFastIselRemaining;
1159 if (EnableFastISelVerbose || EnableFastISelAbort) {
1160 dbgs() << "FastISel missed terminator: ";
1164 NumFastIselFailures += NumFastIselRemaining;
1165 if (EnableFastISelVerbose || EnableFastISelAbort) {
1166 dbgs() << "FastISel miss: ";
1169 if (EnableFastISelAbort)
1170 // The "fast" selector couldn't handle something and bailed.
1171 // For the purpose of debugging, just abort.
1172 llvm_unreachable("FastISel didn't select the entire block");
1177 FastIS->recomputeInsertPt();
1179 // Lower any arguments needed in this block if this is the entry block.
1180 if (LLVMBB == &Fn.getEntryBlock())
1181 LowerArguments(LLVMBB);
1187 ++NumFastIselBlocks;
1190 // Run SelectionDAG instruction selection on the remainder of the block
1191 // not handled by FastISel. If FastISel is not run, this is the entire
1194 SelectBasicBlock(Begin, BI, HadTailCall);
1198 FuncInfo->PHINodesToUpdate.clear();
1202 SDB->clearDanglingDebugInfo();
1206 SelectionDAGISel::FinishBasicBlock() {
1208 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1209 << FuncInfo->PHINodesToUpdate.size() << "\n";
1210 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1211 dbgs() << "Node " << i << " : ("
1212 << FuncInfo->PHINodesToUpdate[i].first
1213 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1215 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1216 // PHI nodes in successors.
1217 if (SDB->SwitchCases.empty() &&
1218 SDB->JTCases.empty() &&
1219 SDB->BitTestCases.empty()) {
1220 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1221 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1222 assert(PHI->isPHI() &&
1223 "This is not a machine PHI node that we are updating!");
1224 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1226 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1231 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1232 // Lower header first, if it wasn't already lowered
1233 if (!SDB->BitTestCases[i].Emitted) {
1234 // Set the current basic block to the mbb we wish to insert the code into
1235 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1236 FuncInfo->InsertPt = FuncInfo->MBB->end();
1238 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1239 CurDAG->setRoot(SDB->getRoot());
1241 CodeGenAndEmitDAG();
1244 uint32_t UnhandledWeight = 0;
1245 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1246 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1248 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1249 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1250 // Set the current basic block to the mbb we wish to insert the code into
1251 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1252 FuncInfo->InsertPt = FuncInfo->MBB->end();
1255 SDB->visitBitTestCase(SDB->BitTestCases[i],
1256 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1258 SDB->BitTestCases[i].Reg,
1259 SDB->BitTestCases[i].Cases[j],
1262 SDB->visitBitTestCase(SDB->BitTestCases[i],
1263 SDB->BitTestCases[i].Default,
1265 SDB->BitTestCases[i].Reg,
1266 SDB->BitTestCases[i].Cases[j],
1270 CurDAG->setRoot(SDB->getRoot());
1272 CodeGenAndEmitDAG();
1276 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1278 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1279 MachineBasicBlock *PHIBB = PHI->getParent();
1280 assert(PHI->isPHI() &&
1281 "This is not a machine PHI node that we are updating!");
1282 // This is "default" BB. We have two jumps to it. From "header" BB and
1283 // from last "case" BB.
1284 if (PHIBB == SDB->BitTestCases[i].Default)
1285 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1286 .addMBB(SDB->BitTestCases[i].Parent)
1287 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1288 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1289 // One of "cases" BB.
1290 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1292 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1293 if (cBB->isSuccessor(PHIBB))
1294 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1298 SDB->BitTestCases.clear();
1300 // If the JumpTable record is filled in, then we need to emit a jump table.
1301 // Updating the PHI nodes is tricky in this case, since we need to determine
1302 // whether the PHI is a successor of the range check MBB or the jump table MBB
1303 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1304 // Lower header first, if it wasn't already lowered
1305 if (!SDB->JTCases[i].first.Emitted) {
1306 // Set the current basic block to the mbb we wish to insert the code into
1307 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1308 FuncInfo->InsertPt = FuncInfo->MBB->end();
1310 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1312 CurDAG->setRoot(SDB->getRoot());
1314 CodeGenAndEmitDAG();
1317 // Set the current basic block to the mbb we wish to insert the code into
1318 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1319 FuncInfo->InsertPt = FuncInfo->MBB->end();
1321 SDB->visitJumpTable(SDB->JTCases[i].second);
1322 CurDAG->setRoot(SDB->getRoot());
1324 CodeGenAndEmitDAG();
1327 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1329 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1330 MachineBasicBlock *PHIBB = PHI->getParent();
1331 assert(PHI->isPHI() &&
1332 "This is not a machine PHI node that we are updating!");
1333 // "default" BB. We can go there only from header BB.
1334 if (PHIBB == SDB->JTCases[i].second.Default)
1335 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1336 .addMBB(SDB->JTCases[i].first.HeaderBB);
1337 // JT BB. Just iterate over successors here
1338 if (FuncInfo->MBB->isSuccessor(PHIBB))
1339 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1342 SDB->JTCases.clear();
1344 // If the switch block involved a branch to one of the actual successors, we
1345 // need to update PHI nodes in that block.
1346 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1347 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1348 assert(PHI->isPHI() &&
1349 "This is not a machine PHI node that we are updating!");
1350 if (FuncInfo->MBB->isSuccessor(PHI->getParent()))
1351 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1354 // If we generated any switch lowering information, build and codegen any
1355 // additional DAGs necessary.
1356 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1357 // Set the current basic block to the mbb we wish to insert the code into
1358 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1359 FuncInfo->InsertPt = FuncInfo->MBB->end();
1361 // Determine the unique successors.
1362 SmallVector<MachineBasicBlock *, 2> Succs;
1363 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1364 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1365 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1367 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1368 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1369 CurDAG->setRoot(SDB->getRoot());
1371 CodeGenAndEmitDAG();
1373 // Remember the last block, now that any splitting is done, for use in
1374 // populating PHI nodes in successors.
1375 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1377 // Handle any PHI nodes in successors of this chunk, as if we were coming
1378 // from the original BB before switch expansion. Note that PHI nodes can
1379 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1380 // handle them the right number of times.
1381 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1382 FuncInfo->MBB = Succs[i];
1383 FuncInfo->InsertPt = FuncInfo->MBB->end();
1384 // FuncInfo->MBB may have been removed from the CFG if a branch was
1386 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1387 for (MachineBasicBlock::iterator
1388 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1389 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1390 MachineInstrBuilder PHI(*MF, MBBI);
1391 // This value for this PHI node is recorded in PHINodesToUpdate.
1392 for (unsigned pn = 0; ; ++pn) {
1393 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1394 "Didn't find PHI entry!");
1395 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1396 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1404 SDB->SwitchCases.clear();
1408 /// Create the scheduler. If a specific scheduler was specified
1409 /// via the SchedulerRegistry, use it, otherwise select the
1410 /// one preferred by the target.
1412 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1413 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1417 RegisterScheduler::setDefault(Ctor);
1420 return Ctor(this, OptLevel);
1423 //===----------------------------------------------------------------------===//
1424 // Helper functions used by the generated instruction selector.
1425 //===----------------------------------------------------------------------===//
1426 // Calls to these methods are generated by tblgen.
1428 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1429 /// the dag combiner simplified the 255, we still want to match. RHS is the
1430 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1431 /// specified in the .td file (e.g. 255).
1432 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1433 int64_t DesiredMaskS) const {
1434 const APInt &ActualMask = RHS->getAPIntValue();
1435 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1437 // If the actual mask exactly matches, success!
1438 if (ActualMask == DesiredMask)
1441 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1442 if (ActualMask.intersects(~DesiredMask))
1445 // Otherwise, the DAG Combiner may have proven that the value coming in is
1446 // either already zero or is not demanded. Check for known zero input bits.
1447 APInt NeededMask = DesiredMask & ~ActualMask;
1448 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1451 // TODO: check to see if missing bits are just not demanded.
1453 // Otherwise, this pattern doesn't match.
1457 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1458 /// the dag combiner simplified the 255, we still want to match. RHS is the
1459 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1460 /// specified in the .td file (e.g. 255).
1461 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1462 int64_t DesiredMaskS) const {
1463 const APInt &ActualMask = RHS->getAPIntValue();
1464 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1466 // If the actual mask exactly matches, success!
1467 if (ActualMask == DesiredMask)
1470 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1471 if (ActualMask.intersects(~DesiredMask))
1474 // Otherwise, the DAG Combiner may have proven that the value coming in is
1475 // either already zero or is not demanded. Check for known zero input bits.
1476 APInt NeededMask = DesiredMask & ~ActualMask;
1478 APInt KnownZero, KnownOne;
1479 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne);
1481 // If all the missing bits in the or are already known to be set, match!
1482 if ((NeededMask & KnownOne) == NeededMask)
1485 // TODO: check to see if missing bits are just not demanded.
1487 // Otherwise, this pattern doesn't match.
1492 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1493 /// by tblgen. Others should not call it.
1494 void SelectionDAGISel::
1495 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1496 std::vector<SDValue> InOps;
1497 std::swap(InOps, Ops);
1499 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1500 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1501 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1502 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1504 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1505 if (InOps[e-1].getValueType() == MVT::Glue)
1506 --e; // Don't process a glue operand if it is here.
1509 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1510 if (!InlineAsm::isMemKind(Flags)) {
1511 // Just skip over this operand, copying the operands verbatim.
1512 Ops.insert(Ops.end(), InOps.begin()+i,
1513 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1514 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1516 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1517 "Memory operand with multiple values?");
1518 // Otherwise, this is a memory operand. Ask the target to select it.
1519 std::vector<SDValue> SelOps;
1520 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1521 report_fatal_error("Could not match memory address. Inline asm"
1524 // Add this to the output node.
1526 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1527 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1528 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1533 // Add the glue input back if present.
1534 if (e != InOps.size())
1535 Ops.push_back(InOps.back());
1538 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1541 static SDNode *findGlueUse(SDNode *N) {
1542 unsigned FlagResNo = N->getNumValues()-1;
1543 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1544 SDUse &Use = I.getUse();
1545 if (Use.getResNo() == FlagResNo)
1546 return Use.getUser();
1551 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1552 /// This function recursively traverses up the operand chain, ignoring
1554 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1555 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1556 bool IgnoreChains) {
1557 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1558 // greater than all of its (recursive) operands. If we scan to a point where
1559 // 'use' is smaller than the node we're scanning for, then we know we will
1562 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1563 // happen because we scan down to newly selected nodes in the case of glue
1565 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1568 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1569 // won't fail if we scan it again.
1570 if (!Visited.insert(Use))
1573 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1574 // Ignore chain uses, they are validated by HandleMergeInputChains.
1575 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1578 SDNode *N = Use->getOperand(i).getNode();
1580 if (Use == ImmedUse || Use == Root)
1581 continue; // We are not looking for immediate use.
1586 // Traverse up the operand chain.
1587 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1593 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1594 /// operand node N of U during instruction selection that starts at Root.
1595 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1596 SDNode *Root) const {
1597 if (OptLevel == CodeGenOpt::None) return false;
1598 return N.hasOneUse();
1601 /// IsLegalToFold - Returns true if the specific operand node N of
1602 /// U can be folded during instruction selection that starts at Root.
1603 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1604 CodeGenOpt::Level OptLevel,
1605 bool IgnoreChains) {
1606 if (OptLevel == CodeGenOpt::None) return false;
1608 // If Root use can somehow reach N through a path that that doesn't contain
1609 // U then folding N would create a cycle. e.g. In the following
1610 // diagram, Root can reach N through X. If N is folded into into Root, then
1611 // X is both a predecessor and a successor of U.
1622 // * indicates nodes to be folded together.
1624 // If Root produces glue, then it gets (even more) interesting. Since it
1625 // will be "glued" together with its glue use in the scheduler, we need to
1626 // check if it might reach N.
1645 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1646 // (call it Fold), then X is a predecessor of GU and a successor of
1647 // Fold. But since Fold and GU are glued together, this will create
1648 // a cycle in the scheduling graph.
1650 // If the node has glue, walk down the graph to the "lowest" node in the
1652 EVT VT = Root->getValueType(Root->getNumValues()-1);
1653 while (VT == MVT::Glue) {
1654 SDNode *GU = findGlueUse(Root);
1658 VT = Root->getValueType(Root->getNumValues()-1);
1660 // If our query node has a glue result with a use, we've walked up it. If
1661 // the user (which has already been selected) has a chain or indirectly uses
1662 // the chain, our WalkChainUsers predicate will not consider it. Because of
1663 // this, we cannot ignore chains in this predicate.
1664 IgnoreChains = false;
1668 SmallPtrSet<SDNode*, 16> Visited;
1669 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1672 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1673 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1674 SelectInlineAsmMemoryOperands(Ops);
1676 std::vector<EVT> VTs;
1677 VTs.push_back(MVT::Other);
1678 VTs.push_back(MVT::Glue);
1679 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1680 VTs, &Ops[0], Ops.size());
1682 return New.getNode();
1685 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1686 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1689 /// GetVBR - decode a vbr encoding whose top bit is set.
1690 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1691 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1692 assert(Val >= 128 && "Not a VBR");
1693 Val &= 127; // Remove first vbr bit.
1698 NextBits = MatcherTable[Idx++];
1699 Val |= (NextBits&127) << Shift;
1701 } while (NextBits & 128);
1707 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1708 /// interior glue and chain results to use the new glue and chain results.
1709 void SelectionDAGISel::
1710 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1711 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1713 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1714 bool isMorphNodeTo) {
1715 SmallVector<SDNode*, 4> NowDeadNodes;
1717 // Now that all the normal results are replaced, we replace the chain and
1718 // glue results if present.
1719 if (!ChainNodesMatched.empty()) {
1720 assert(InputChain.getNode() != 0 &&
1721 "Matched input chains but didn't produce a chain");
1722 // Loop over all of the nodes we matched that produced a chain result.
1723 // Replace all the chain results with the final chain we ended up with.
1724 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1725 SDNode *ChainNode = ChainNodesMatched[i];
1727 // If this node was already deleted, don't look at it.
1728 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1731 // Don't replace the results of the root node if we're doing a
1733 if (ChainNode == NodeToMatch && isMorphNodeTo)
1736 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1737 if (ChainVal.getValueType() == MVT::Glue)
1738 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1739 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1740 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
1742 // If the node became dead and we haven't already seen it, delete it.
1743 if (ChainNode->use_empty() &&
1744 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1745 NowDeadNodes.push_back(ChainNode);
1749 // If the result produces glue, update any glue results in the matched
1750 // pattern with the glue result.
1751 if (InputGlue.getNode() != 0) {
1752 // Handle any interior nodes explicitly marked.
1753 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1754 SDNode *FRN = GlueResultNodesMatched[i];
1756 // If this node was already deleted, don't look at it.
1757 if (FRN->getOpcode() == ISD::DELETED_NODE)
1760 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1761 "Doesn't have a glue result");
1762 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1765 // If the node became dead and we haven't already seen it, delete it.
1766 if (FRN->use_empty() &&
1767 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1768 NowDeadNodes.push_back(FRN);
1772 if (!NowDeadNodes.empty())
1773 CurDAG->RemoveDeadNodes(NowDeadNodes);
1775 DEBUG(errs() << "ISEL: Match complete!\n");
1781 CR_LeadsToInteriorNode
1784 /// WalkChainUsers - Walk down the users of the specified chained node that is
1785 /// part of the pattern we're matching, looking at all of the users we find.
1786 /// This determines whether something is an interior node, whether we have a
1787 /// non-pattern node in between two pattern nodes (which prevent folding because
1788 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1789 /// between pattern nodes (in which case the TF becomes part of the pattern).
1791 /// The walk we do here is guaranteed to be small because we quickly get down to
1792 /// already selected nodes "below" us.
1794 WalkChainUsers(const SDNode *ChainedNode,
1795 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1796 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1797 ChainResult Result = CR_Simple;
1799 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1800 E = ChainedNode->use_end(); UI != E; ++UI) {
1801 // Make sure the use is of the chain, not some other value we produce.
1802 if (UI.getUse().getValueType() != MVT::Other) continue;
1806 // If we see an already-selected machine node, then we've gone beyond the
1807 // pattern that we're selecting down into the already selected chunk of the
1809 if (User->isMachineOpcode() ||
1810 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1813 unsigned UserOpcode = User->getOpcode();
1814 if (UserOpcode == ISD::CopyToReg ||
1815 UserOpcode == ISD::CopyFromReg ||
1816 UserOpcode == ISD::INLINEASM ||
1817 UserOpcode == ISD::EH_LABEL ||
1818 UserOpcode == ISD::LIFETIME_START ||
1819 UserOpcode == ISD::LIFETIME_END) {
1820 // If their node ID got reset to -1 then they've already been selected.
1821 // Treat them like a MachineOpcode.
1822 if (User->getNodeId() == -1)
1826 // If we have a TokenFactor, we handle it specially.
1827 if (User->getOpcode() != ISD::TokenFactor) {
1828 // If the node isn't a token factor and isn't part of our pattern, then it
1829 // must be a random chained node in between two nodes we're selecting.
1830 // This happens when we have something like:
1835 // Because we structurally match the load/store as a read/modify/write,
1836 // but the call is chained between them. We cannot fold in this case
1837 // because it would induce a cycle in the graph.
1838 if (!std::count(ChainedNodesInPattern.begin(),
1839 ChainedNodesInPattern.end(), User))
1840 return CR_InducesCycle;
1842 // Otherwise we found a node that is part of our pattern. For example in:
1846 // This would happen when we're scanning down from the load and see the
1847 // store as a user. Record that there is a use of ChainedNode that is
1848 // part of the pattern and keep scanning uses.
1849 Result = CR_LeadsToInteriorNode;
1850 InteriorChainedNodes.push_back(User);
1854 // If we found a TokenFactor, there are two cases to consider: first if the
1855 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1856 // uses of the TF are in our pattern) we just want to ignore it. Second,
1857 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1863 // | \ DAG's like cheese
1866 // [TokenFactor] [Op]
1873 // In this case, the TokenFactor becomes part of our match and we rewrite it
1874 // as a new TokenFactor.
1876 // To distinguish these two cases, do a recursive walk down the uses.
1877 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1879 // If the uses of the TokenFactor are just already-selected nodes, ignore
1880 // it, it is "below" our pattern.
1882 case CR_InducesCycle:
1883 // If the uses of the TokenFactor lead to nodes that are not part of our
1884 // pattern that are not selected, folding would turn this into a cycle,
1886 return CR_InducesCycle;
1887 case CR_LeadsToInteriorNode:
1888 break; // Otherwise, keep processing.
1891 // Okay, we know we're in the interesting interior case. The TokenFactor
1892 // is now going to be considered part of the pattern so that we rewrite its
1893 // uses (it may have uses that are not part of the pattern) with the
1894 // ultimate chain result of the generated code. We will also add its chain
1895 // inputs as inputs to the ultimate TokenFactor we create.
1896 Result = CR_LeadsToInteriorNode;
1897 ChainedNodesInPattern.push_back(User);
1898 InteriorChainedNodes.push_back(User);
1905 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1906 /// operation for when the pattern matched at least one node with a chains. The
1907 /// input vector contains a list of all of the chained nodes that we match. We
1908 /// must determine if this is a valid thing to cover (i.e. matching it won't
1909 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1910 /// be used as the input node chain for the generated nodes.
1912 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1913 SelectionDAG *CurDAG) {
1914 // Walk all of the chained nodes we've matched, recursively scanning down the
1915 // users of the chain result. This adds any TokenFactor nodes that are caught
1916 // in between chained nodes to the chained and interior nodes list.
1917 SmallVector<SDNode*, 3> InteriorChainedNodes;
1918 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1919 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1920 InteriorChainedNodes) == CR_InducesCycle)
1921 return SDValue(); // Would induce a cycle.
1924 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1925 // that we are interested in. Form our input TokenFactor node.
1926 SmallVector<SDValue, 3> InputChains;
1927 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1928 // Add the input chain of this node to the InputChains list (which will be
1929 // the operands of the generated TokenFactor) if it's not an interior node.
1930 SDNode *N = ChainNodesMatched[i];
1931 if (N->getOpcode() != ISD::TokenFactor) {
1932 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1935 // Otherwise, add the input chain.
1936 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1937 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1938 InputChains.push_back(InChain);
1942 // If we have a token factor, we want to add all inputs of the token factor
1943 // that are not part of the pattern we're matching.
1944 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1945 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1946 N->getOperand(op).getNode()))
1947 InputChains.push_back(N->getOperand(op));
1952 if (InputChains.size() == 1)
1953 return InputChains[0];
1954 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1955 MVT::Other, &InputChains[0], InputChains.size());
1958 /// MorphNode - Handle morphing a node in place for the selector.
1959 SDNode *SelectionDAGISel::
1960 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1961 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1962 // It is possible we're using MorphNodeTo to replace a node with no
1963 // normal results with one that has a normal result (or we could be
1964 // adding a chain) and the input could have glue and chains as well.
1965 // In this case we need to shift the operands down.
1966 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1967 // than the old isel though.
1968 int OldGlueResultNo = -1, OldChainResultNo = -1;
1970 unsigned NTMNumResults = Node->getNumValues();
1971 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
1972 OldGlueResultNo = NTMNumResults-1;
1973 if (NTMNumResults != 1 &&
1974 Node->getValueType(NTMNumResults-2) == MVT::Other)
1975 OldChainResultNo = NTMNumResults-2;
1976 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1977 OldChainResultNo = NTMNumResults-1;
1979 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1980 // that this deletes operands of the old node that become dead.
1981 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1983 // MorphNodeTo can operate in two ways: if an existing node with the
1984 // specified operands exists, it can just return it. Otherwise, it
1985 // updates the node in place to have the requested operands.
1987 // If we updated the node in place, reset the node ID. To the isel,
1988 // this should be just like a newly allocated machine node.
1992 unsigned ResNumResults = Res->getNumValues();
1993 // Move the glue if needed.
1994 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
1995 (unsigned)OldGlueResultNo != ResNumResults-1)
1996 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
1997 SDValue(Res, ResNumResults-1));
1999 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
2002 // Move the chain reference if needed.
2003 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
2004 (unsigned)OldChainResultNo != ResNumResults-1)
2005 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2006 SDValue(Res, ResNumResults-1));
2008 // Otherwise, no replacement happened because the node already exists. Replace
2009 // Uses of the old node with the new one.
2011 CurDAG->ReplaceAllUsesWith(Node, Res);
2016 /// CheckSame - Implements OP_CheckSame.
2017 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2018 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2020 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2021 // Accept if it is exactly the same as a previously recorded node.
2022 unsigned RecNo = MatcherTable[MatcherIndex++];
2023 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2024 return N == RecordedNodes[RecNo].first;
2027 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2028 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2029 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2030 const SelectionDAGISel &SDISel) {
2031 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2034 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2035 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2036 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2037 const SelectionDAGISel &SDISel, SDNode *N) {
2038 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2041 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2042 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2044 uint16_t Opc = MatcherTable[MatcherIndex++];
2045 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2046 return N->getOpcode() == Opc;
2049 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2050 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2051 SDValue N, const TargetLowering &TLI) {
2052 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2053 if (N.getValueType() == VT) return true;
2055 // Handle the case when VT is iPTR.
2056 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
2059 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2060 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2061 SDValue N, const TargetLowering &TLI,
2063 if (ChildNo >= N.getNumOperands())
2064 return false; // Match fails if out of range child #.
2065 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2069 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2070 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2072 return cast<CondCodeSDNode>(N)->get() ==
2073 (ISD::CondCode)MatcherTable[MatcherIndex++];
2076 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2077 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2078 SDValue N, const TargetLowering &TLI) {
2079 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2080 if (cast<VTSDNode>(N)->getVT() == VT)
2083 // Handle the case when VT is iPTR.
2084 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
2087 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2088 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2090 int64_t Val = MatcherTable[MatcherIndex++];
2092 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2094 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2095 return C != 0 && C->getSExtValue() == Val;
2098 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2099 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2100 SDValue N, const SelectionDAGISel &SDISel) {
2101 int64_t Val = MatcherTable[MatcherIndex++];
2103 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2105 if (N->getOpcode() != ISD::AND) return false;
2107 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2108 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2111 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2112 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2113 SDValue N, const SelectionDAGISel &SDISel) {
2114 int64_t Val = MatcherTable[MatcherIndex++];
2116 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2118 if (N->getOpcode() != ISD::OR) return false;
2120 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2121 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2124 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2125 /// scope, evaluate the current node. If the current predicate is known to
2126 /// fail, set Result=true and return anything. If the current predicate is
2127 /// known to pass, set Result=false and return the MatcherIndex to continue
2128 /// with. If the current predicate is unknown, set Result=false and return the
2129 /// MatcherIndex to continue with.
2130 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2131 unsigned Index, SDValue N,
2133 const SelectionDAGISel &SDISel,
2134 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2135 switch (Table[Index++]) {
2138 return Index-1; // Could not evaluate this predicate.
2139 case SelectionDAGISel::OPC_CheckSame:
2140 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2142 case SelectionDAGISel::OPC_CheckPatternPredicate:
2143 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2145 case SelectionDAGISel::OPC_CheckPredicate:
2146 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2148 case SelectionDAGISel::OPC_CheckOpcode:
2149 Result = !::CheckOpcode(Table, Index, N.getNode());
2151 case SelectionDAGISel::OPC_CheckType:
2152 Result = !::CheckType(Table, Index, N, SDISel.TLI);
2154 case SelectionDAGISel::OPC_CheckChild0Type:
2155 case SelectionDAGISel::OPC_CheckChild1Type:
2156 case SelectionDAGISel::OPC_CheckChild2Type:
2157 case SelectionDAGISel::OPC_CheckChild3Type:
2158 case SelectionDAGISel::OPC_CheckChild4Type:
2159 case SelectionDAGISel::OPC_CheckChild5Type:
2160 case SelectionDAGISel::OPC_CheckChild6Type:
2161 case SelectionDAGISel::OPC_CheckChild7Type:
2162 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
2163 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
2165 case SelectionDAGISel::OPC_CheckCondCode:
2166 Result = !::CheckCondCode(Table, Index, N);
2168 case SelectionDAGISel::OPC_CheckValueType:
2169 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2171 case SelectionDAGISel::OPC_CheckInteger:
2172 Result = !::CheckInteger(Table, Index, N);
2174 case SelectionDAGISel::OPC_CheckAndImm:
2175 Result = !::CheckAndImm(Table, Index, N, SDISel);
2177 case SelectionDAGISel::OPC_CheckOrImm:
2178 Result = !::CheckOrImm(Table, Index, N, SDISel);
2186 /// FailIndex - If this match fails, this is the index to continue with.
2189 /// NodeStack - The node stack when the scope was formed.
2190 SmallVector<SDValue, 4> NodeStack;
2192 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2193 unsigned NumRecordedNodes;
2195 /// NumMatchedMemRefs - The number of matched memref entries.
2196 unsigned NumMatchedMemRefs;
2198 /// InputChain/InputGlue - The current chain/glue
2199 SDValue InputChain, InputGlue;
2201 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2202 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2207 SDNode *SelectionDAGISel::
2208 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2209 unsigned TableSize) {
2210 // FIXME: Should these even be selected? Handle these cases in the caller?
2211 switch (NodeToMatch->getOpcode()) {
2214 case ISD::EntryToken: // These nodes remain the same.
2215 case ISD::BasicBlock:
2217 case ISD::RegisterMask:
2218 //case ISD::VALUETYPE:
2219 //case ISD::CONDCODE:
2220 case ISD::HANDLENODE:
2221 case ISD::MDNODE_SDNODE:
2222 case ISD::TargetConstant:
2223 case ISD::TargetConstantFP:
2224 case ISD::TargetConstantPool:
2225 case ISD::TargetFrameIndex:
2226 case ISD::TargetExternalSymbol:
2227 case ISD::TargetBlockAddress:
2228 case ISD::TargetJumpTable:
2229 case ISD::TargetGlobalTLSAddress:
2230 case ISD::TargetGlobalAddress:
2231 case ISD::TokenFactor:
2232 case ISD::CopyFromReg:
2233 case ISD::CopyToReg:
2235 case ISD::LIFETIME_START:
2236 case ISD::LIFETIME_END:
2237 NodeToMatch->setNodeId(-1); // Mark selected.
2239 case ISD::AssertSext:
2240 case ISD::AssertZext:
2241 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2242 NodeToMatch->getOperand(0));
2244 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2245 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2248 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2250 // Set up the node stack with NodeToMatch as the only node on the stack.
2251 SmallVector<SDValue, 8> NodeStack;
2252 SDValue N = SDValue(NodeToMatch, 0);
2253 NodeStack.push_back(N);
2255 // MatchScopes - Scopes used when matching, if a match failure happens, this
2256 // indicates where to continue checking.
2257 SmallVector<MatchScope, 8> MatchScopes;
2259 // RecordedNodes - This is the set of nodes that have been recorded by the
2260 // state machine. The second value is the parent of the node, or null if the
2261 // root is recorded.
2262 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2264 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2266 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2268 // These are the current input chain and glue for use when generating nodes.
2269 // Various Emit operations change these. For example, emitting a copytoreg
2270 // uses and updates these.
2271 SDValue InputChain, InputGlue;
2273 // ChainNodesMatched - If a pattern matches nodes that have input/output
2274 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2275 // which ones they are. The result is captured into this list so that we can
2276 // update the chain results when the pattern is complete.
2277 SmallVector<SDNode*, 3> ChainNodesMatched;
2278 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2280 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2281 NodeToMatch->dump(CurDAG);
2284 // Determine where to start the interpreter. Normally we start at opcode #0,
2285 // but if the state machine starts with an OPC_SwitchOpcode, then we
2286 // accelerate the first lookup (which is guaranteed to be hot) with the
2287 // OpcodeOffset table.
2288 unsigned MatcherIndex = 0;
2290 if (!OpcodeOffset.empty()) {
2291 // Already computed the OpcodeOffset table, just index into it.
2292 if (N.getOpcode() < OpcodeOffset.size())
2293 MatcherIndex = OpcodeOffset[N.getOpcode()];
2294 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2296 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2297 // Otherwise, the table isn't computed, but the state machine does start
2298 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2299 // is the first time we're selecting an instruction.
2302 // Get the size of this case.
2303 unsigned CaseSize = MatcherTable[Idx++];
2305 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2306 if (CaseSize == 0) break;
2308 // Get the opcode, add the index to the table.
2309 uint16_t Opc = MatcherTable[Idx++];
2310 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2311 if (Opc >= OpcodeOffset.size())
2312 OpcodeOffset.resize((Opc+1)*2);
2313 OpcodeOffset[Opc] = Idx;
2317 // Okay, do the lookup for the first opcode.
2318 if (N.getOpcode() < OpcodeOffset.size())
2319 MatcherIndex = OpcodeOffset[N.getOpcode()];
2323 assert(MatcherIndex < TableSize && "Invalid index");
2325 unsigned CurrentOpcodeIndex = MatcherIndex;
2327 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2330 // Okay, the semantics of this operation are that we should push a scope
2331 // then evaluate the first child. However, pushing a scope only to have
2332 // the first check fail (which then pops it) is inefficient. If we can
2333 // determine immediately that the first check (or first several) will
2334 // immediately fail, don't even bother pushing a scope for them.
2338 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2339 if (NumToSkip & 128)
2340 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2341 // Found the end of the scope with no match.
2342 if (NumToSkip == 0) {
2347 FailIndex = MatcherIndex+NumToSkip;
2349 unsigned MatcherIndexOfPredicate = MatcherIndex;
2350 (void)MatcherIndexOfPredicate; // silence warning.
2352 // If we can't evaluate this predicate without pushing a scope (e.g. if
2353 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2354 // push the scope and evaluate the full predicate chain.
2356 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2357 Result, *this, RecordedNodes);
2361 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2362 << "index " << MatcherIndexOfPredicate
2363 << ", continuing at " << FailIndex << "\n");
2364 ++NumDAGIselRetries;
2366 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2367 // move to the next case.
2368 MatcherIndex = FailIndex;
2371 // If the whole scope failed to match, bail.
2372 if (FailIndex == 0) break;
2374 // Push a MatchScope which indicates where to go if the first child fails
2376 MatchScope NewEntry;
2377 NewEntry.FailIndex = FailIndex;
2378 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2379 NewEntry.NumRecordedNodes = RecordedNodes.size();
2380 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2381 NewEntry.InputChain = InputChain;
2382 NewEntry.InputGlue = InputGlue;
2383 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2384 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2385 MatchScopes.push_back(NewEntry);
2388 case OPC_RecordNode: {
2389 // Remember this node, it may end up being an operand in the pattern.
2391 if (NodeStack.size() > 1)
2392 Parent = NodeStack[NodeStack.size()-2].getNode();
2393 RecordedNodes.push_back(std::make_pair(N, Parent));
2397 case OPC_RecordChild0: case OPC_RecordChild1:
2398 case OPC_RecordChild2: case OPC_RecordChild3:
2399 case OPC_RecordChild4: case OPC_RecordChild5:
2400 case OPC_RecordChild6: case OPC_RecordChild7: {
2401 unsigned ChildNo = Opcode-OPC_RecordChild0;
2402 if (ChildNo >= N.getNumOperands())
2403 break; // Match fails if out of range child #.
2405 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2409 case OPC_RecordMemRef:
2410 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2413 case OPC_CaptureGlueInput:
2414 // If the current node has an input glue, capture it in InputGlue.
2415 if (N->getNumOperands() != 0 &&
2416 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2417 InputGlue = N->getOperand(N->getNumOperands()-1);
2420 case OPC_MoveChild: {
2421 unsigned ChildNo = MatcherTable[MatcherIndex++];
2422 if (ChildNo >= N.getNumOperands())
2423 break; // Match fails if out of range child #.
2424 N = N.getOperand(ChildNo);
2425 NodeStack.push_back(N);
2429 case OPC_MoveParent:
2430 // Pop the current node off the NodeStack.
2431 NodeStack.pop_back();
2432 assert(!NodeStack.empty() && "Node stack imbalance!");
2433 N = NodeStack.back();
2437 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2439 case OPC_CheckPatternPredicate:
2440 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2442 case OPC_CheckPredicate:
2443 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2447 case OPC_CheckComplexPat: {
2448 unsigned CPNum = MatcherTable[MatcherIndex++];
2449 unsigned RecNo = MatcherTable[MatcherIndex++];
2450 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2451 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2452 RecordedNodes[RecNo].first, CPNum,
2457 case OPC_CheckOpcode:
2458 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2462 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2465 case OPC_SwitchOpcode: {
2466 unsigned CurNodeOpcode = N.getOpcode();
2467 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2470 // Get the size of this case.
2471 CaseSize = MatcherTable[MatcherIndex++];
2473 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2474 if (CaseSize == 0) break;
2476 uint16_t Opc = MatcherTable[MatcherIndex++];
2477 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2479 // If the opcode matches, then we will execute this case.
2480 if (CurNodeOpcode == Opc)
2483 // Otherwise, skip over this case.
2484 MatcherIndex += CaseSize;
2487 // If no cases matched, bail out.
2488 if (CaseSize == 0) break;
2490 // Otherwise, execute the case we found.
2491 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2492 << " to " << MatcherIndex << "\n");
2496 case OPC_SwitchType: {
2497 MVT CurNodeVT = N.getValueType().getSimpleVT();
2498 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2501 // Get the size of this case.
2502 CaseSize = MatcherTable[MatcherIndex++];
2504 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2505 if (CaseSize == 0) break;
2507 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2508 if (CaseVT == MVT::iPTR)
2509 CaseVT = TLI.getPointerTy();
2511 // If the VT matches, then we will execute this case.
2512 if (CurNodeVT == CaseVT)
2515 // Otherwise, skip over this case.
2516 MatcherIndex += CaseSize;
2519 // If no cases matched, bail out.
2520 if (CaseSize == 0) break;
2522 // Otherwise, execute the case we found.
2523 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2524 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2527 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2528 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2529 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2530 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2531 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2532 Opcode-OPC_CheckChild0Type))
2535 case OPC_CheckCondCode:
2536 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2538 case OPC_CheckValueType:
2539 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2541 case OPC_CheckInteger:
2542 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2544 case OPC_CheckAndImm:
2545 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2547 case OPC_CheckOrImm:
2548 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2551 case OPC_CheckFoldableChainNode: {
2552 assert(NodeStack.size() != 1 && "No parent node");
2553 // Verify that all intermediate nodes between the root and this one have
2555 bool HasMultipleUses = false;
2556 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2557 if (!NodeStack[i].hasOneUse()) {
2558 HasMultipleUses = true;
2561 if (HasMultipleUses) break;
2563 // Check to see that the target thinks this is profitable to fold and that
2564 // we can fold it without inducing cycles in the graph.
2565 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2567 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2568 NodeToMatch, OptLevel,
2569 true/*We validate our own chains*/))
2574 case OPC_EmitInteger: {
2575 MVT::SimpleValueType VT =
2576 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2577 int64_t Val = MatcherTable[MatcherIndex++];
2579 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2580 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2581 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2584 case OPC_EmitRegister: {
2585 MVT::SimpleValueType VT =
2586 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2587 unsigned RegNo = MatcherTable[MatcherIndex++];
2588 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2589 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2592 case OPC_EmitRegister2: {
2593 // For targets w/ more than 256 register names, the register enum
2594 // values are stored in two bytes in the matcher table (just like
2596 MVT::SimpleValueType VT =
2597 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2598 unsigned RegNo = MatcherTable[MatcherIndex++];
2599 RegNo |= MatcherTable[MatcherIndex++] << 8;
2600 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2601 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2605 case OPC_EmitConvertToTarget: {
2606 // Convert from IMM/FPIMM to target version.
2607 unsigned RecNo = MatcherTable[MatcherIndex++];
2608 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2609 SDValue Imm = RecordedNodes[RecNo].first;
2611 if (Imm->getOpcode() == ISD::Constant) {
2612 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2613 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2614 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2615 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2616 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2619 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2623 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2624 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2625 // These are space-optimized forms of OPC_EmitMergeInputChains.
2626 assert(InputChain.getNode() == 0 &&
2627 "EmitMergeInputChains should be the first chain producing node");
2628 assert(ChainNodesMatched.empty() &&
2629 "Should only have one EmitMergeInputChains per match");
2631 // Read all of the chained nodes.
2632 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2633 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2634 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2636 // FIXME: What if other value results of the node have uses not matched
2638 if (ChainNodesMatched.back() != NodeToMatch &&
2639 !RecordedNodes[RecNo].first.hasOneUse()) {
2640 ChainNodesMatched.clear();
2644 // Merge the input chains if they are not intra-pattern references.
2645 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2647 if (InputChain.getNode() == 0)
2648 break; // Failed to merge.
2652 case OPC_EmitMergeInputChains: {
2653 assert(InputChain.getNode() == 0 &&
2654 "EmitMergeInputChains should be the first chain producing node");
2655 // This node gets a list of nodes we matched in the input that have
2656 // chains. We want to token factor all of the input chains to these nodes
2657 // together. However, if any of the input chains is actually one of the
2658 // nodes matched in this pattern, then we have an intra-match reference.
2659 // Ignore these because the newly token factored chain should not refer to
2661 unsigned NumChains = MatcherTable[MatcherIndex++];
2662 assert(NumChains != 0 && "Can't TF zero chains");
2664 assert(ChainNodesMatched.empty() &&
2665 "Should only have one EmitMergeInputChains per match");
2667 // Read all of the chained nodes.
2668 for (unsigned i = 0; i != NumChains; ++i) {
2669 unsigned RecNo = MatcherTable[MatcherIndex++];
2670 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2671 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2673 // FIXME: What if other value results of the node have uses not matched
2675 if (ChainNodesMatched.back() != NodeToMatch &&
2676 !RecordedNodes[RecNo].first.hasOneUse()) {
2677 ChainNodesMatched.clear();
2682 // If the inner loop broke out, the match fails.
2683 if (ChainNodesMatched.empty())
2686 // Merge the input chains if they are not intra-pattern references.
2687 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2689 if (InputChain.getNode() == 0)
2690 break; // Failed to merge.
2695 case OPC_EmitCopyToReg: {
2696 unsigned RecNo = MatcherTable[MatcherIndex++];
2697 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2698 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2700 if (InputChain.getNode() == 0)
2701 InputChain = CurDAG->getEntryNode();
2703 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2704 DestPhysReg, RecordedNodes[RecNo].first,
2707 InputGlue = InputChain.getValue(1);
2711 case OPC_EmitNodeXForm: {
2712 unsigned XFormNo = MatcherTable[MatcherIndex++];
2713 unsigned RecNo = MatcherTable[MatcherIndex++];
2714 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2715 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2716 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2721 case OPC_MorphNodeTo: {
2722 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2723 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2724 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2725 // Get the result VT list.
2726 unsigned NumVTs = MatcherTable[MatcherIndex++];
2727 SmallVector<EVT, 4> VTs;
2728 for (unsigned i = 0; i != NumVTs; ++i) {
2729 MVT::SimpleValueType VT =
2730 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2731 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2735 if (EmitNodeInfo & OPFL_Chain)
2736 VTs.push_back(MVT::Other);
2737 if (EmitNodeInfo & OPFL_GlueOutput)
2738 VTs.push_back(MVT::Glue);
2740 // This is hot code, so optimize the two most common cases of 1 and 2
2743 if (VTs.size() == 1)
2744 VTList = CurDAG->getVTList(VTs[0]);
2745 else if (VTs.size() == 2)
2746 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2748 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2750 // Get the operand list.
2751 unsigned NumOps = MatcherTable[MatcherIndex++];
2752 SmallVector<SDValue, 8> Ops;
2753 for (unsigned i = 0; i != NumOps; ++i) {
2754 unsigned RecNo = MatcherTable[MatcherIndex++];
2756 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2758 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2759 Ops.push_back(RecordedNodes[RecNo].first);
2762 // If there are variadic operands to add, handle them now.
2763 if (EmitNodeInfo & OPFL_VariadicInfo) {
2764 // Determine the start index to copy from.
2765 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2766 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2767 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2768 "Invalid variadic node");
2769 // Copy all of the variadic operands, not including a potential glue
2771 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2773 SDValue V = NodeToMatch->getOperand(i);
2774 if (V.getValueType() == MVT::Glue) break;
2779 // If this has chain/glue inputs, add them.
2780 if (EmitNodeInfo & OPFL_Chain)
2781 Ops.push_back(InputChain);
2782 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2783 Ops.push_back(InputGlue);
2787 if (Opcode != OPC_MorphNodeTo) {
2788 // If this is a normal EmitNode command, just create the new node and
2789 // add the results to the RecordedNodes list.
2790 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2791 VTList, Ops.data(), Ops.size());
2793 // Add all the non-glue/non-chain results to the RecordedNodes list.
2794 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2795 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2796 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2800 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
2801 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2804 // NodeToMatch was eliminated by CSE when the target changed the DAG.
2805 // We will visit the equivalent node later.
2806 DEBUG(dbgs() << "Node was eliminated by CSE\n");
2810 // If the node had chain/glue results, update our notion of the current
2812 if (EmitNodeInfo & OPFL_GlueOutput) {
2813 InputGlue = SDValue(Res, VTs.size()-1);
2814 if (EmitNodeInfo & OPFL_Chain)
2815 InputChain = SDValue(Res, VTs.size()-2);
2816 } else if (EmitNodeInfo & OPFL_Chain)
2817 InputChain = SDValue(Res, VTs.size()-1);
2819 // If the OPFL_MemRefs glue is set on this node, slap all of the
2820 // accumulated memrefs onto it.
2822 // FIXME: This is vastly incorrect for patterns with multiple outputs
2823 // instructions that access memory and for ComplexPatterns that match
2825 if (EmitNodeInfo & OPFL_MemRefs) {
2826 // Only attach load or store memory operands if the generated
2827 // instruction may load or store.
2828 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc);
2829 bool mayLoad = MCID.mayLoad();
2830 bool mayStore = MCID.mayStore();
2832 unsigned NumMemRefs = 0;
2833 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2834 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2835 if ((*I)->isLoad()) {
2838 } else if ((*I)->isStore()) {
2846 MachineSDNode::mmo_iterator MemRefs =
2847 MF->allocateMemRefsArray(NumMemRefs);
2849 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
2850 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2851 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2852 if ((*I)->isLoad()) {
2855 } else if ((*I)->isStore()) {
2863 cast<MachineSDNode>(Res)
2864 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
2868 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2869 << " node: "; Res->dump(CurDAG); errs() << "\n");
2871 // If this was a MorphNodeTo then we're completely done!
2872 if (Opcode == OPC_MorphNodeTo) {
2873 // Update chain and glue uses.
2874 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2875 InputGlue, GlueResultNodesMatched, true);
2882 case OPC_MarkGlueResults: {
2883 unsigned NumNodes = MatcherTable[MatcherIndex++];
2885 // Read and remember all the glue-result nodes.
2886 for (unsigned i = 0; i != NumNodes; ++i) {
2887 unsigned RecNo = MatcherTable[MatcherIndex++];
2889 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2891 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2892 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2897 case OPC_CompleteMatch: {
2898 // The match has been completed, and any new nodes (if any) have been
2899 // created. Patch up references to the matched dag to use the newly
2901 unsigned NumResults = MatcherTable[MatcherIndex++];
2903 for (unsigned i = 0; i != NumResults; ++i) {
2904 unsigned ResSlot = MatcherTable[MatcherIndex++];
2906 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2908 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2909 SDValue Res = RecordedNodes[ResSlot].first;
2911 assert(i < NodeToMatch->getNumValues() &&
2912 NodeToMatch->getValueType(i) != MVT::Other &&
2913 NodeToMatch->getValueType(i) != MVT::Glue &&
2914 "Invalid number of results to complete!");
2915 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2916 NodeToMatch->getValueType(i) == MVT::iPTR ||
2917 Res.getValueType() == MVT::iPTR ||
2918 NodeToMatch->getValueType(i).getSizeInBits() ==
2919 Res.getValueType().getSizeInBits()) &&
2920 "invalid replacement");
2921 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2924 // If the root node defines glue, add it to the glue nodes to update list.
2925 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
2926 GlueResultNodesMatched.push_back(NodeToMatch);
2928 // Update chain and glue uses.
2929 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2930 InputGlue, GlueResultNodesMatched, false);
2932 assert(NodeToMatch->use_empty() &&
2933 "Didn't replace all uses of the node?");
2935 // FIXME: We just return here, which interacts correctly with SelectRoot
2936 // above. We should fix this to not return an SDNode* anymore.
2941 // If the code reached this point, then the match failed. See if there is
2942 // another child to try in the current 'Scope', otherwise pop it until we
2943 // find a case to check.
2944 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2945 ++NumDAGIselRetries;
2947 if (MatchScopes.empty()) {
2948 CannotYetSelect(NodeToMatch);
2952 // Restore the interpreter state back to the point where the scope was
2954 MatchScope &LastScope = MatchScopes.back();
2955 RecordedNodes.resize(LastScope.NumRecordedNodes);
2957 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2958 N = NodeStack.back();
2960 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2961 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2962 MatcherIndex = LastScope.FailIndex;
2964 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2966 InputChain = LastScope.InputChain;
2967 InputGlue = LastScope.InputGlue;
2968 if (!LastScope.HasChainNodesMatched)
2969 ChainNodesMatched.clear();
2970 if (!LastScope.HasGlueResultNodesMatched)
2971 GlueResultNodesMatched.clear();
2973 // Check to see what the offset is at the new MatcherIndex. If it is zero
2974 // we have reached the end of this scope, otherwise we have another child
2975 // in the current scope to try.
2976 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2977 if (NumToSkip & 128)
2978 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2980 // If we have another child in this scope to match, update FailIndex and
2982 if (NumToSkip != 0) {
2983 LastScope.FailIndex = MatcherIndex+NumToSkip;
2987 // End of this scope, pop it and try the next child in the containing
2989 MatchScopes.pop_back();
2996 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2998 raw_string_ostream Msg(msg);
2999 Msg << "Cannot select: ";
3001 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
3002 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
3003 N->getOpcode() != ISD::INTRINSIC_VOID) {
3004 N->printrFull(Msg, CurDAG);
3005 Msg << "\nIn function: " << MF->getName();
3007 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3009 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3010 if (iid < Intrinsic::num_intrinsics)
3011 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3012 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3013 Msg << "target intrinsic %" << TII->getName(iid);
3015 Msg << "unknown intrinsic #" << iid;
3017 report_fatal_error(Msg.str());
3020 char SelectionDAGISel::ID = 0;