1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/GCStrategy.h"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/PostOrderIterator.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/CFG.h"
22 #include "llvm/Analysis/EHPersonalities.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/CodeGen/Analysis.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/GCMetadata.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
34 #include "llvm/CodeGen/SchedulerRegistry.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/SelectionDAGISel.h"
37 #include "llvm/CodeGen/WinEHFuncInfo.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DebugInfo.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/InlineAsm.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/IntrinsicInst.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/IR/LLVMContext.h"
46 #include "llvm/IR/Module.h"
47 #include "llvm/MC/MCAsmInfo.h"
48 #include "llvm/Support/Compiler.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/Timer.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/Target/TargetInstrInfo.h"
54 #include "llvm/Target/TargetIntrinsicInfo.h"
55 #include "llvm/Target/TargetLowering.h"
56 #include "llvm/Target/TargetMachine.h"
57 #include "llvm/Target/TargetOptions.h"
58 #include "llvm/Target/TargetRegisterInfo.h"
59 #include "llvm/Target/TargetSubtargetInfo.h"
60 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
64 #define DEBUG_TYPE "isel"
66 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
67 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
68 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
69 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
70 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
71 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
72 STATISTIC(NumFastIselFailLowerArguments,
73 "Number of entry blocks where fast isel failed to lower arguments");
77 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
78 cl::desc("Enable extra verbose messages in the \"fast\" "
79 "instruction selector"));
82 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
83 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
84 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
85 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
86 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
87 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
88 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
90 // Standard binary operators...
91 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
92 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
93 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
94 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
95 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
96 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
97 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
98 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
99 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
100 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
101 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
102 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
104 // Logical operators...
105 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
106 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
107 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
109 // Memory instructions...
110 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
111 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
112 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
113 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
114 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
115 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
116 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
118 // Convert instructions...
119 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
120 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
121 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
122 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
123 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
124 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
125 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
126 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
127 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
128 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
129 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
130 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
132 // Other instructions...
133 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
134 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
135 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
136 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
137 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
138 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
139 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
140 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
141 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
142 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
143 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
144 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
145 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
146 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
147 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
149 // Intrinsic instructions...
150 STATISTIC(NumFastIselFailIntrinsicCall, "Fast isel fails on Intrinsic call");
151 STATISTIC(NumFastIselFailSAddWithOverflow,
152 "Fast isel fails on sadd.with.overflow");
153 STATISTIC(NumFastIselFailUAddWithOverflow,
154 "Fast isel fails on uadd.with.overflow");
155 STATISTIC(NumFastIselFailSSubWithOverflow,
156 "Fast isel fails on ssub.with.overflow");
157 STATISTIC(NumFastIselFailUSubWithOverflow,
158 "Fast isel fails on usub.with.overflow");
159 STATISTIC(NumFastIselFailSMulWithOverflow,
160 "Fast isel fails on smul.with.overflow");
161 STATISTIC(NumFastIselFailUMulWithOverflow,
162 "Fast isel fails on umul.with.overflow");
163 STATISTIC(NumFastIselFailFrameaddress, "Fast isel fails on Frameaddress");
164 STATISTIC(NumFastIselFailSqrt, "Fast isel fails on sqrt call");
165 STATISTIC(NumFastIselFailStackMap, "Fast isel fails on StackMap call");
166 STATISTIC(NumFastIselFailPatchPoint, "Fast isel fails on PatchPoint call");
170 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
171 cl::desc("Enable verbose messages in the \"fast\" "
172 "instruction selector"));
173 static cl::opt<int> EnableFastISelAbort(
174 "fast-isel-abort", cl::Hidden,
175 cl::desc("Enable abort calls when \"fast\" instruction selection "
176 "fails to lower an instruction: 0 disable the abort, 1 will "
177 "abort but for args, calls and terminators, 2 will also "
178 "abort for argument lowering, and 3 will never fallback "
179 "to SelectionDAG."));
183 cl::desc("use Machine Branch Probability Info"),
184 cl::init(true), cl::Hidden);
187 static cl::opt<std::string>
188 FilterDAGBasicBlockName("filter-view-dags", cl::Hidden,
189 cl::desc("Only display the basic block whose name "
190 "matches this for all view-*-dags options"));
192 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
193 cl::desc("Pop up a window to show dags before the first "
194 "dag combine pass"));
196 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
197 cl::desc("Pop up a window to show dags before legalize types"));
199 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
200 cl::desc("Pop up a window to show dags before legalize"));
202 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
203 cl::desc("Pop up a window to show dags before the second "
204 "dag combine pass"));
206 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
207 cl::desc("Pop up a window to show dags before the post legalize types"
208 " dag combine pass"));
210 ViewISelDAGs("view-isel-dags", cl::Hidden,
211 cl::desc("Pop up a window to show isel dags as they are selected"));
213 ViewSchedDAGs("view-sched-dags", cl::Hidden,
214 cl::desc("Pop up a window to show sched dags as they are processed"));
216 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
217 cl::desc("Pop up a window to show SUnit dags after they are processed"));
219 static const bool ViewDAGCombine1 = false,
220 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
221 ViewDAGCombine2 = false,
222 ViewDAGCombineLT = false,
223 ViewISelDAGs = false, ViewSchedDAGs = false,
224 ViewSUnitDAGs = false;
227 //===---------------------------------------------------------------------===//
229 /// RegisterScheduler class - Track the registration of instruction schedulers.
231 //===---------------------------------------------------------------------===//
232 MachinePassRegistry RegisterScheduler::Registry;
234 //===---------------------------------------------------------------------===//
236 /// ISHeuristic command line option for instruction schedulers.
238 //===---------------------------------------------------------------------===//
239 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
240 RegisterPassParser<RegisterScheduler> >
241 ISHeuristic("pre-RA-sched",
242 cl::init(&createDefaultScheduler), cl::Hidden,
243 cl::desc("Instruction schedulers available (before register"
246 static RegisterScheduler
247 defaultListDAGScheduler("default", "Best scheduler for the target",
248 createDefaultScheduler);
251 //===--------------------------------------------------------------------===//
252 /// \brief This class is used by SelectionDAGISel to temporarily override
253 /// the optimization level on a per-function basis.
254 class OptLevelChanger {
255 SelectionDAGISel &IS;
256 CodeGenOpt::Level SavedOptLevel;
260 OptLevelChanger(SelectionDAGISel &ISel,
261 CodeGenOpt::Level NewOptLevel) : IS(ISel) {
262 SavedOptLevel = IS.OptLevel;
263 if (NewOptLevel == SavedOptLevel)
265 IS.OptLevel = NewOptLevel;
266 IS.TM.setOptLevel(NewOptLevel);
267 DEBUG(dbgs() << "\nChanging optimization level for Function "
268 << IS.MF->getFunction()->getName() << "\n");
269 DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel
270 << " ; After: -O" << NewOptLevel << "\n");
271 SavedFastISel = IS.TM.Options.EnableFastISel;
272 if (NewOptLevel == CodeGenOpt::None) {
273 IS.TM.setFastISel(IS.TM.getO0WantsFastISel());
274 DEBUG(dbgs() << "\tFastISel is "
275 << (IS.TM.Options.EnableFastISel ? "enabled" : "disabled")
281 if (IS.OptLevel == SavedOptLevel)
283 DEBUG(dbgs() << "\nRestoring optimization level for Function "
284 << IS.MF->getFunction()->getName() << "\n");
285 DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel
286 << " ; After: -O" << SavedOptLevel << "\n");
287 IS.OptLevel = SavedOptLevel;
288 IS.TM.setOptLevel(SavedOptLevel);
289 IS.TM.setFastISel(SavedFastISel);
293 //===--------------------------------------------------------------------===//
294 /// createDefaultScheduler - This creates an instruction scheduler appropriate
296 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
297 CodeGenOpt::Level OptLevel) {
298 const TargetLowering *TLI = IS->TLI;
299 const TargetSubtargetInfo &ST = IS->MF->getSubtarget();
301 // Try first to see if the Target has its own way of selecting a scheduler
302 if (auto *SchedulerCtor = ST.getDAGScheduler(OptLevel)) {
303 return SchedulerCtor(IS, OptLevel);
306 if (OptLevel == CodeGenOpt::None ||
307 (ST.enableMachineScheduler() && ST.enableMachineSchedDefaultSched()) ||
308 TLI->getSchedulingPreference() == Sched::Source)
309 return createSourceListDAGScheduler(IS, OptLevel);
310 if (TLI->getSchedulingPreference() == Sched::RegPressure)
311 return createBURRListDAGScheduler(IS, OptLevel);
312 if (TLI->getSchedulingPreference() == Sched::Hybrid)
313 return createHybridListDAGScheduler(IS, OptLevel);
314 if (TLI->getSchedulingPreference() == Sched::VLIW)
315 return createVLIWDAGScheduler(IS, OptLevel);
316 assert(TLI->getSchedulingPreference() == Sched::ILP &&
317 "Unknown sched type!");
318 return createILPListDAGScheduler(IS, OptLevel);
322 // EmitInstrWithCustomInserter - This method should be implemented by targets
323 // that mark instructions with the 'usesCustomInserter' flag. These
324 // instructions are special in various ways, which require special support to
325 // insert. The specified MachineInstr is created but not inserted into any
326 // basic blocks, and this method is called to expand it into a sequence of
327 // instructions, potentially also creating new basic blocks and control flow.
328 // When new basic blocks are inserted and the edges from MBB to its successors
329 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
332 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
333 MachineBasicBlock *MBB) const {
335 dbgs() << "If a target marks an instruction with "
336 "'usesCustomInserter', it must implement "
337 "TargetLowering::EmitInstrWithCustomInserter!";
339 llvm_unreachable(nullptr);
342 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
343 SDNode *Node) const {
344 assert(!MI->hasPostISelHook() &&
345 "If a target marks an instruction with 'hasPostISelHook', "
346 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
349 //===----------------------------------------------------------------------===//
350 // SelectionDAGISel code
351 //===----------------------------------------------------------------------===//
353 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
354 CodeGenOpt::Level OL) :
355 MachineFunctionPass(ID), TM(tm),
356 FuncInfo(new FunctionLoweringInfo()),
357 CurDAG(new SelectionDAG(tm, OL)),
358 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
362 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
363 initializeBranchProbabilityInfoWrapperPassPass(
364 *PassRegistry::getPassRegistry());
365 initializeAAResultsWrapperPassPass(*PassRegistry::getPassRegistry());
366 initializeTargetLibraryInfoWrapperPassPass(
367 *PassRegistry::getPassRegistry());
370 SelectionDAGISel::~SelectionDAGISel() {
376 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
377 AU.addRequired<AAResultsWrapperPass>();
378 AU.addRequired<GCModuleInfo>();
379 AU.addPreserved<GCModuleInfo>();
380 AU.addRequired<TargetLibraryInfoWrapperPass>();
381 if (UseMBPI && OptLevel != CodeGenOpt::None)
382 AU.addRequired<BranchProbabilityInfoWrapperPass>();
383 MachineFunctionPass::getAnalysisUsage(AU);
386 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
387 /// may trap on it. In this case we have to split the edge so that the path
388 /// through the predecessor block that doesn't go to the phi block doesn't
389 /// execute the possibly trapping instruction.
391 /// This is required for correctness, so it must be done at -O0.
393 static void SplitCriticalSideEffectEdges(Function &Fn) {
394 // Loop for blocks with phi nodes.
395 for (BasicBlock &BB : Fn) {
396 PHINode *PN = dyn_cast<PHINode>(BB.begin());
400 // For each block with a PHI node, check to see if any of the input values
401 // are potentially trapping constant expressions. Constant expressions are
402 // the only potentially trapping value that can occur as the argument to a
404 for (BasicBlock::iterator I = BB.begin(); (PN = dyn_cast<PHINode>(I)); ++I)
405 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
406 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
407 if (!CE || !CE->canTrap()) continue;
409 // The only case we have to worry about is when the edge is critical.
410 // Since this block has a PHI Node, we assume it has multiple input
411 // edges: check to see if the pred has multiple successors.
412 BasicBlock *Pred = PN->getIncomingBlock(i);
413 if (Pred->getTerminator()->getNumSuccessors() == 1)
416 // Okay, we have to split this edge.
418 Pred->getTerminator(), GetSuccessorNumber(Pred, &BB),
419 CriticalEdgeSplittingOptions().setMergeIdenticalEdges());
425 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
426 // Do some sanity-checking on the command-line options.
427 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
428 "-fast-isel-verbose requires -fast-isel");
429 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
430 "-fast-isel-abort > 0 requires -fast-isel");
432 const Function &Fn = *mf.getFunction();
435 // Reset the target options before resetting the optimization
437 // FIXME: This is a horrible hack and should be processed via
438 // codegen looking at the optimization level explicitly when
439 // it wants to look at it.
440 TM.resetTargetOptions(Fn);
441 // Reset OptLevel to None for optnone functions.
442 CodeGenOpt::Level NewOptLevel = OptLevel;
443 if (Fn.hasFnAttribute(Attribute::OptimizeNone))
444 NewOptLevel = CodeGenOpt::None;
445 OptLevelChanger OLC(*this, NewOptLevel);
447 TII = MF->getSubtarget().getInstrInfo();
448 TLI = MF->getSubtarget().getTargetLowering();
449 RegInfo = &MF->getRegInfo();
450 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
451 LibInfo = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI();
452 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : nullptr;
454 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
456 SplitCriticalSideEffectEdges(const_cast<Function &>(Fn));
459 FuncInfo->set(Fn, *MF, CurDAG);
461 if (UseMBPI && OptLevel != CodeGenOpt::None)
462 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfoWrapperPass>().getBPI();
464 FuncInfo->BPI = nullptr;
466 SDB->init(GFI, *AA, LibInfo);
468 MF->setHasInlineAsm(false);
470 FuncInfo->SplitCSR = false;
471 SmallVector<MachineBasicBlock*, 4> Returns;
473 // We split CSR if the target supports it for the given function
474 // and the function has only return exits.
475 if (TLI->supportSplitCSR(MF)) {
476 FuncInfo->SplitCSR = true;
478 // Collect all the return blocks.
479 for (const BasicBlock &BB : Fn) {
480 if (!succ_empty(&BB))
483 const TerminatorInst *Term = BB.getTerminator();
484 if (isa<UnreachableInst>(Term))
486 if (isa<ReturnInst>(Term)) {
487 Returns.push_back(FuncInfo->MBBMap[&BB]);
491 // Bail out if the exit block is not Return nor Unreachable.
492 FuncInfo->SplitCSR = false;
497 MachineBasicBlock *EntryMBB = &MF->front();
498 if (FuncInfo->SplitCSR)
499 // This performs initialization so lowering for SplitCSR will be correct.
500 TLI->initializeSplitCSR(EntryMBB);
502 SelectAllBasicBlocks(Fn);
504 // If the first basic block in the function has live ins that need to be
505 // copied into vregs, emit the copies into the top of the block before
506 // emitting the code for the block.
507 const TargetRegisterInfo &TRI = *MF->getSubtarget().getRegisterInfo();
508 RegInfo->EmitLiveInCopies(EntryMBB, TRI, *TII);
510 // Insert copies in the entry block and the return blocks.
511 if (FuncInfo->SplitCSR)
512 TLI->insertCopiesSplitCSR(EntryMBB, Returns);
514 DenseMap<unsigned, unsigned> LiveInMap;
515 if (!FuncInfo->ArgDbgValues.empty())
516 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
517 E = RegInfo->livein_end(); LI != E; ++LI)
519 LiveInMap.insert(std::make_pair(LI->first, LI->second));
521 // Insert DBG_VALUE instructions for function arguments to the entry block.
522 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
523 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
524 bool hasFI = MI->getOperand(0).isFI();
526 hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
527 if (TargetRegisterInfo::isPhysicalRegister(Reg))
528 EntryMBB->insert(EntryMBB->begin(), MI);
530 MachineInstr *Def = RegInfo->getVRegDef(Reg);
532 MachineBasicBlock::iterator InsertPos = Def;
533 // FIXME: VR def may not be in entry block.
534 Def->getParent()->insert(std::next(InsertPos), MI);
536 DEBUG(dbgs() << "Dropping debug info for dead vreg"
537 << TargetRegisterInfo::virtReg2Index(Reg) << "\n");
540 // If Reg is live-in then update debug info to track its copy in a vreg.
541 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
542 if (LDI != LiveInMap.end()) {
543 assert(!hasFI && "There's no handling of frame pointer updating here yet "
545 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
546 MachineBasicBlock::iterator InsertPos = Def;
547 const MDNode *Variable = MI->getDebugVariable();
548 const MDNode *Expr = MI->getDebugExpression();
549 DebugLoc DL = MI->getDebugLoc();
550 bool IsIndirect = MI->isIndirectDebugValue();
551 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
552 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
553 "Expected inlined-at fields to agree");
554 // Def is never a terminator here, so it is ok to increment InsertPos.
555 BuildMI(*EntryMBB, ++InsertPos, DL, TII->get(TargetOpcode::DBG_VALUE),
556 IsIndirect, LDI->second, Offset, Variable, Expr);
558 // If this vreg is directly copied into an exported register then
559 // that COPY instructions also need DBG_VALUE, if it is the only
560 // user of LDI->second.
561 MachineInstr *CopyUseMI = nullptr;
562 for (MachineRegisterInfo::use_instr_iterator
563 UI = RegInfo->use_instr_begin(LDI->second),
564 E = RegInfo->use_instr_end(); UI != E; ) {
565 MachineInstr *UseMI = &*(UI++);
566 if (UseMI->isDebugValue()) continue;
567 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
568 CopyUseMI = UseMI; continue;
570 // Otherwise this is another use or second copy use.
571 CopyUseMI = nullptr; break;
574 // Use MI's debug location, which describes where Variable was
575 // declared, rather than whatever is attached to CopyUseMI.
576 MachineInstr *NewMI =
577 BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
578 CopyUseMI->getOperand(0).getReg(), Offset, Variable, Expr);
579 MachineBasicBlock::iterator Pos = CopyUseMI;
580 EntryMBB->insertAfter(Pos, NewMI);
585 // Determine if there are any calls in this machine function.
586 MachineFrameInfo *MFI = MF->getFrameInfo();
587 for (const auto &MBB : *MF) {
588 if (MFI->hasCalls() && MF->hasInlineAsm())
591 for (const auto &MI : MBB) {
592 const MCInstrDesc &MCID = TII->get(MI.getOpcode());
593 if ((MCID.isCall() && !MCID.isReturn()) ||
594 MI.isStackAligningInlineAsm()) {
595 MFI->setHasCalls(true);
597 if (MI.isInlineAsm()) {
598 MF->setHasInlineAsm(true);
603 // Determine if there is a call to setjmp in the machine function.
604 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
606 // Replace forward-declared registers with the registers containing
607 // the desired value.
608 MachineRegisterInfo &MRI = MF->getRegInfo();
609 for (DenseMap<unsigned, unsigned>::iterator
610 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
612 unsigned From = I->first;
613 unsigned To = I->second;
614 // If To is also scheduled to be replaced, find what its ultimate
617 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
621 // Make sure the new register has a sufficiently constrained register class.
622 if (TargetRegisterInfo::isVirtualRegister(From) &&
623 TargetRegisterInfo::isVirtualRegister(To))
624 MRI.constrainRegClass(To, MRI.getRegClass(From));
628 // Replacing one register with another won't touch the kill flags.
629 // We need to conservatively clear the kill flags as a kill on the old
630 // register might dominate existing uses of the new register.
631 if (!MRI.use_empty(To))
632 MRI.clearKillFlags(From);
633 MRI.replaceRegWith(From, To);
636 if (TLI->hasCopyImplyingStackAdjustment(MF))
637 MFI->setHasCopyImplyingStackAdjustment(true);
639 // Freeze the set of reserved registers now that MachineFrameInfo has been
640 // set up. All the information required by getReservedRegs() should be
642 MRI.freezeReservedRegs(*MF);
644 // Release function-specific state. SDB and CurDAG are already cleared
648 // XXX-update: Right after instruction selection, check through the
649 // intentionally added fake conditional branches and mark them as unremovable.
650 for (auto& MBB : *MF) {
651 // Check whether MBB has two successors which only contains an unconditional
652 // branch to the same destination.
653 if (MBB.succ_size() != 2 ||
654 !MBB.getLastNonDebugInstr()->isUnconditionalBranch()) {
657 auto MBBSuccIter = MBB.succ_begin();
658 auto* Succ1 = *MBBSuccIter;
660 auto* Succ2 = *MBBSuccIter;
662 MachineBasicBlock* Succ1Succ = nullptr;
663 MachineBasicBlock* Succ2Succ = nullptr;
664 if ((Succ1->size() == 1 && Succ1->begin()->isUnconditionalBranch()) ||
665 (Succ1->size() == 0)) {
666 if (Succ1->succ_size()) {
667 Succ1Succ = *Succ1->succ_begin();
670 if ((Succ2->size() == 1 && Succ2->begin()->isUnconditionalBranch()) ||
671 (Succ2->size() == 0)) {
672 if (Succ1->succ_size()) {
673 Succ2Succ = *Succ2->succ_begin();
677 bool HasCommonDest = Succ1Succ && Succ1Succ == Succ2Succ;
679 auto MBBIter = MBB.end();
680 std::advance(MBBIter, -2);
681 assert(MBBIter->isConditionalBranch());
682 MBB.disableCanEliminateMachineBB();
683 Succ1->disableCanEliminateMachineBB();
684 Succ2->disableCanEliminateMachineBB();
685 Succ1Succ->disableCanEliminateMachineBB();
686 DEBUG(dbgs() << "Mark as unremovable machine basic block: " << MBB
687 << "\nMark as unremovable branch instruction: " << *MBBIter
692 DEBUG(dbgs() << "*** MachineFunction at end of ISel ***\n");
693 DEBUG(MF->print(dbgs()));
698 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
699 BasicBlock::const_iterator End,
701 // Lower the instructions. If a call is emitted as a tail call, cease emitting
702 // nodes for this block.
703 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
706 // Make sure the root of the DAG is up-to-date.
707 CurDAG->setRoot(SDB->getControlRoot());
708 HadTailCall = SDB->HasTailCall;
711 // Final step, emit the lowered DAG as machine code.
715 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
716 SmallPtrSet<SDNode*, 128> VisitedNodes;
717 SmallVector<SDNode*, 128> Worklist;
719 Worklist.push_back(CurDAG->getRoot().getNode());
725 SDNode *N = Worklist.pop_back_val();
727 // If we've already seen this node, ignore it.
728 if (!VisitedNodes.insert(N).second)
731 // Otherwise, add all chain operands to the worklist.
732 for (const SDValue &Op : N->op_values())
733 if (Op.getValueType() == MVT::Other)
734 Worklist.push_back(Op.getNode());
736 // If this is a CopyToReg with a vreg dest, process it.
737 if (N->getOpcode() != ISD::CopyToReg)
740 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
741 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
744 // Ignore non-scalar or non-integer values.
745 SDValue Src = N->getOperand(2);
746 EVT SrcVT = Src.getValueType();
747 if (!SrcVT.isInteger() || SrcVT.isVector())
750 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
751 CurDAG->computeKnownBits(Src, KnownZero, KnownOne);
752 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
753 } while (!Worklist.empty());
756 void SelectionDAGISel::CodeGenAndEmitDAG() {
757 std::string GroupName;
758 if (TimePassesIsEnabled)
759 GroupName = "Instruction Selection and Scheduling";
760 std::string BlockName;
761 int BlockNumber = -1;
763 bool MatchFilterBB = false; (void)MatchFilterBB;
765 MatchFilterBB = (FilterDAGBasicBlockName.empty() ||
766 FilterDAGBasicBlockName ==
767 FuncInfo->MBB->getBasicBlock()->getName().str());
770 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
771 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
775 BlockNumber = FuncInfo->MBB->getNumber();
777 (MF->getName() + ":" + FuncInfo->MBB->getBasicBlock()->getName()).str();
779 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
780 << " '" << BlockName << "'\n"; CurDAG->dump());
782 if (ViewDAGCombine1 && MatchFilterBB)
783 CurDAG->viewGraph("dag-combine1 input for " + BlockName);
785 // Run the DAG combiner in pre-legalize mode.
787 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
788 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
791 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
792 << " '" << BlockName << "'\n"; CurDAG->dump());
794 // Second step, hack on the DAG until it only uses operations and types that
795 // the target supports.
796 if (ViewLegalizeTypesDAGs && MatchFilterBB)
797 CurDAG->viewGraph("legalize-types input for " + BlockName);
801 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
802 Changed = CurDAG->LegalizeTypes();
805 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
806 << " '" << BlockName << "'\n"; CurDAG->dump());
808 CurDAG->NewNodesMustHaveLegalTypes = true;
811 if (ViewDAGCombineLT && MatchFilterBB)
812 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
814 // Run the DAG combiner in post-type-legalize mode.
816 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
817 TimePassesIsEnabled);
818 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
821 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
822 << " '" << BlockName << "'\n"; CurDAG->dump());
827 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
828 Changed = CurDAG->LegalizeVectors();
833 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
834 CurDAG->LegalizeTypes();
837 if (ViewDAGCombineLT && MatchFilterBB)
838 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
840 // Run the DAG combiner in post-type-legalize mode.
842 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
843 TimePassesIsEnabled);
844 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
847 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
848 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
851 if (ViewLegalizeDAGs && MatchFilterBB)
852 CurDAG->viewGraph("legalize input for " + BlockName);
855 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
859 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
860 << " '" << BlockName << "'\n"; CurDAG->dump());
862 if (ViewDAGCombine2 && MatchFilterBB)
863 CurDAG->viewGraph("dag-combine2 input for " + BlockName);
865 // Run the DAG combiner in post-legalize mode.
867 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
868 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
871 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
872 << " '" << BlockName << "'\n"; CurDAG->dump());
874 if (OptLevel != CodeGenOpt::None)
875 ComputeLiveOutVRegInfo();
877 if (ViewISelDAGs && MatchFilterBB)
878 CurDAG->viewGraph("isel input for " + BlockName);
880 // Third, instruction select all of the operations to machine code, adding the
881 // code to the MachineBasicBlock.
883 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
884 DoInstructionSelection();
887 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
888 << " '" << BlockName << "'\n"; CurDAG->dump());
890 if (ViewSchedDAGs && MatchFilterBB)
891 CurDAG->viewGraph("scheduler input for " + BlockName);
893 // Schedule machine code.
894 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
896 NamedRegionTimer T("Instruction Scheduling", GroupName,
897 TimePassesIsEnabled);
898 Scheduler->Run(CurDAG, FuncInfo->MBB);
901 if (ViewSUnitDAGs && MatchFilterBB) Scheduler->viewGraph();
903 // Emit machine code to BB. This can change 'BB' to the last block being
905 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
907 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
909 // FuncInfo->InsertPt is passed by reference and set to the end of the
910 // scheduled instructions.
911 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
914 // If the block was split, make sure we update any references that are used to
915 // update PHI nodes later on.
916 if (FirstMBB != LastMBB)
917 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
919 // Free the scheduler state.
921 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
922 TimePassesIsEnabled);
926 // Free the SelectionDAG state, now that we're finished with it.
931 /// ISelUpdater - helper class to handle updates of the instruction selection
933 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
934 SelectionDAG::allnodes_iterator &ISelPosition;
936 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
937 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
939 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
940 /// deleted is the current ISelPosition node, update ISelPosition.
942 void NodeDeleted(SDNode *N, SDNode *E) override {
943 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
947 } // end anonymous namespace
949 void SelectionDAGISel::DoInstructionSelection() {
950 DEBUG(dbgs() << "===== Instruction selection begins: BB#"
951 << FuncInfo->MBB->getNumber()
952 << " '" << FuncInfo->MBB->getName() << "'\n");
956 // Select target instructions for the DAG.
958 // Number all nodes with a topological order and set DAGSize.
959 DAGSize = CurDAG->AssignTopologicalOrder();
961 // Create a dummy node (which is not added to allnodes), that adds
962 // a reference to the root node, preventing it from being deleted,
963 // and tracking any changes of the root.
964 HandleSDNode Dummy(CurDAG->getRoot());
965 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
968 // Make sure that ISelPosition gets properly updated when nodes are deleted
969 // in calls made from this function.
970 ISelUpdater ISU(*CurDAG, ISelPosition);
972 // The AllNodes list is now topological-sorted. Visit the
973 // nodes by starting at the end of the list (the root of the
974 // graph) and preceding back toward the beginning (the entry
976 while (ISelPosition != CurDAG->allnodes_begin()) {
977 SDNode *Node = &*--ISelPosition;
978 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
979 // but there are currently some corner cases that it misses. Also, this
980 // makes it theoretically possible to disable the DAGCombiner.
981 if (Node->use_empty())
984 SDNode *ResNode = Select(Node);
986 // FIXME: This is pretty gross. 'Select' should be changed to not return
987 // anything at all and this code should be nuked with a tactical strike.
989 // If node should not be replaced, continue with the next one.
990 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
994 ReplaceUses(Node, ResNode);
997 // If after the replacement this node is not used any more,
998 // remove this dead node.
999 if (Node->use_empty()) // Don't delete EntryToken, etc.
1000 CurDAG->RemoveDeadNode(Node);
1003 CurDAG->setRoot(Dummy.getValue());
1006 DEBUG(dbgs() << "===== Instruction selection ends:\n");
1008 PostprocessISelDAG();
1011 static bool hasExceptionPointerOrCodeUser(const CatchPadInst *CPI) {
1012 for (const User *U : CPI->users()) {
1013 if (const IntrinsicInst *EHPtrCall = dyn_cast<IntrinsicInst>(U)) {
1014 Intrinsic::ID IID = EHPtrCall->getIntrinsicID();
1015 if (IID == Intrinsic::eh_exceptionpointer ||
1016 IID == Intrinsic::eh_exceptioncode)
1023 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
1024 /// do other setup for EH landing-pad blocks.
1025 bool SelectionDAGISel::PrepareEHLandingPad() {
1026 MachineBasicBlock *MBB = FuncInfo->MBB;
1027 const Constant *PersonalityFn = FuncInfo->Fn->getPersonalityFn();
1028 const BasicBlock *LLVMBB = MBB->getBasicBlock();
1029 const TargetRegisterClass *PtrRC =
1030 TLI->getRegClassFor(TLI->getPointerTy(CurDAG->getDataLayout()));
1032 // Catchpads have one live-in register, which typically holds the exception
1034 if (const auto *CPI = dyn_cast<CatchPadInst>(LLVMBB->getFirstNonPHI())) {
1035 if (hasExceptionPointerOrCodeUser(CPI)) {
1036 // Get or create the virtual register to hold the pointer or code. Mark
1037 // the live in physreg and copy into the vreg.
1038 MCPhysReg EHPhysReg = TLI->getExceptionPointerRegister(PersonalityFn);
1039 assert(EHPhysReg && "target lacks exception pointer register");
1040 MBB->addLiveIn(EHPhysReg);
1041 unsigned VReg = FuncInfo->getCatchPadExceptionPointerVReg(CPI, PtrRC);
1042 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(),
1043 TII->get(TargetOpcode::COPY), VReg)
1044 .addReg(EHPhysReg, RegState::Kill);
1049 if (!LLVMBB->isLandingPad())
1052 // Add a label to mark the beginning of the landing pad. Deletion of the
1053 // landing pad can thus be detected via the MachineModuleInfo.
1054 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
1056 // Assign the call site to the landing pad's begin label.
1057 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
1059 const MCInstrDesc &II = TII->get(TargetOpcode::EH_LABEL);
1060 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
1063 // Mark exception register as live in.
1064 if (unsigned Reg = TLI->getExceptionPointerRegister(PersonalityFn))
1065 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
1067 // Mark exception selector register as live in.
1068 if (unsigned Reg = TLI->getExceptionSelectorRegister(PersonalityFn))
1069 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC);
1074 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
1075 /// side-effect free and is either dead or folded into a generated instruction.
1076 /// Return false if it needs to be emitted.
1077 static bool isFoldedOrDeadInstruction(const Instruction *I,
1078 FunctionLoweringInfo *FuncInfo) {
1079 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
1080 !isa<TerminatorInst>(I) && // Terminators aren't folded.
1081 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
1082 !I->isEHPad() && // EH pad instructions aren't folded.
1083 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
1087 // Collect per Instruction statistics for fast-isel misses. Only those
1088 // instructions that cause the bail are accounted for. It does not account for
1089 // instructions higher in the block. Thus, summing the per instructions stats
1090 // will not add up to what is reported by NumFastIselFailures.
1091 static void collectFailStats(const Instruction *I) {
1092 switch (I->getOpcode()) {
1093 default: assert (0 && "<Invalid operator> ");
1096 case Instruction::Ret: NumFastIselFailRet++; return;
1097 case Instruction::Br: NumFastIselFailBr++; return;
1098 case Instruction::Switch: NumFastIselFailSwitch++; return;
1099 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
1100 case Instruction::Invoke: NumFastIselFailInvoke++; return;
1101 case Instruction::Resume: NumFastIselFailResume++; return;
1102 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
1104 // Standard binary operators...
1105 case Instruction::Add: NumFastIselFailAdd++; return;
1106 case Instruction::FAdd: NumFastIselFailFAdd++; return;
1107 case Instruction::Sub: NumFastIselFailSub++; return;
1108 case Instruction::FSub: NumFastIselFailFSub++; return;
1109 case Instruction::Mul: NumFastIselFailMul++; return;
1110 case Instruction::FMul: NumFastIselFailFMul++; return;
1111 case Instruction::UDiv: NumFastIselFailUDiv++; return;
1112 case Instruction::SDiv: NumFastIselFailSDiv++; return;
1113 case Instruction::FDiv: NumFastIselFailFDiv++; return;
1114 case Instruction::URem: NumFastIselFailURem++; return;
1115 case Instruction::SRem: NumFastIselFailSRem++; return;
1116 case Instruction::FRem: NumFastIselFailFRem++; return;
1118 // Logical operators...
1119 case Instruction::And: NumFastIselFailAnd++; return;
1120 case Instruction::Or: NumFastIselFailOr++; return;
1121 case Instruction::Xor: NumFastIselFailXor++; return;
1123 // Memory instructions...
1124 case Instruction::Alloca: NumFastIselFailAlloca++; return;
1125 case Instruction::Load: NumFastIselFailLoad++; return;
1126 case Instruction::Store: NumFastIselFailStore++; return;
1127 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
1128 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
1129 case Instruction::Fence: NumFastIselFailFence++; return;
1130 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
1132 // Convert instructions...
1133 case Instruction::Trunc: NumFastIselFailTrunc++; return;
1134 case Instruction::ZExt: NumFastIselFailZExt++; return;
1135 case Instruction::SExt: NumFastIselFailSExt++; return;
1136 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
1137 case Instruction::FPExt: NumFastIselFailFPExt++; return;
1138 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
1139 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
1140 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
1141 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
1142 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
1143 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
1144 case Instruction::BitCast: NumFastIselFailBitCast++; return;
1146 // Other instructions...
1147 case Instruction::ICmp: NumFastIselFailICmp++; return;
1148 case Instruction::FCmp: NumFastIselFailFCmp++; return;
1149 case Instruction::PHI: NumFastIselFailPHI++; return;
1150 case Instruction::Select: NumFastIselFailSelect++; return;
1151 case Instruction::Call: {
1152 if (auto const *Intrinsic = dyn_cast<IntrinsicInst>(I)) {
1153 switch (Intrinsic->getIntrinsicID()) {
1155 NumFastIselFailIntrinsicCall++; return;
1156 case Intrinsic::sadd_with_overflow:
1157 NumFastIselFailSAddWithOverflow++; return;
1158 case Intrinsic::uadd_with_overflow:
1159 NumFastIselFailUAddWithOverflow++; return;
1160 case Intrinsic::ssub_with_overflow:
1161 NumFastIselFailSSubWithOverflow++; return;
1162 case Intrinsic::usub_with_overflow:
1163 NumFastIselFailUSubWithOverflow++; return;
1164 case Intrinsic::smul_with_overflow:
1165 NumFastIselFailSMulWithOverflow++; return;
1166 case Intrinsic::umul_with_overflow:
1167 NumFastIselFailUMulWithOverflow++; return;
1168 case Intrinsic::frameaddress:
1169 NumFastIselFailFrameaddress++; return;
1170 case Intrinsic::sqrt:
1171 NumFastIselFailSqrt++; return;
1172 case Intrinsic::experimental_stackmap:
1173 NumFastIselFailStackMap++; return;
1174 case Intrinsic::experimental_patchpoint_void: // fall-through
1175 case Intrinsic::experimental_patchpoint_i64:
1176 NumFastIselFailPatchPoint++; return;
1179 NumFastIselFailCall++;
1182 case Instruction::Shl: NumFastIselFailShl++; return;
1183 case Instruction::LShr: NumFastIselFailLShr++; return;
1184 case Instruction::AShr: NumFastIselFailAShr++; return;
1185 case Instruction::VAArg: NumFastIselFailVAArg++; return;
1186 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
1187 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
1188 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
1189 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
1190 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
1191 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
1196 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
1197 // Initialize the Fast-ISel state, if needed.
1198 FastISel *FastIS = nullptr;
1199 if (TM.Options.EnableFastISel)
1200 FastIS = TLI->createFastISel(*FuncInfo, LibInfo);
1202 // Iterate over all basic blocks in the function.
1203 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
1204 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
1205 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
1206 const BasicBlock *LLVMBB = *I;
1208 if (OptLevel != CodeGenOpt::None) {
1209 bool AllPredsVisited = true;
1210 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1212 if (!FuncInfo->VisitedBBs.count(*PI)) {
1213 AllPredsVisited = false;
1218 if (AllPredsVisited) {
1219 for (BasicBlock::const_iterator I = LLVMBB->begin();
1220 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1221 FuncInfo->ComputePHILiveOutRegInfo(PN);
1223 for (BasicBlock::const_iterator I = LLVMBB->begin();
1224 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1225 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1228 FuncInfo->VisitedBBs.insert(LLVMBB);
1231 BasicBlock::const_iterator const Begin =
1232 LLVMBB->getFirstNonPHI()->getIterator();
1233 BasicBlock::const_iterator const End = LLVMBB->end();
1234 BasicBlock::const_iterator BI = End;
1236 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1238 continue; // Some blocks like catchpads have no code or MBB.
1239 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1241 // Setup an EH landing-pad block.
1242 FuncInfo->ExceptionPointerVirtReg = 0;
1243 FuncInfo->ExceptionSelectorVirtReg = 0;
1244 if (LLVMBB->isEHPad())
1245 if (!PrepareEHLandingPad())
1248 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1250 FastIS->startNewBlock();
1252 // Emit code for any incoming arguments. This must happen before
1253 // beginning FastISel on the entry block.
1254 if (LLVMBB == &Fn.getEntryBlock()) {
1257 // Lower any arguments needed in this block if this is the entry block.
1258 if (!FastIS->lowerArguments()) {
1259 // Fast isel failed to lower these arguments
1260 ++NumFastIselFailLowerArguments;
1261 if (EnableFastISelAbort > 1)
1262 report_fatal_error("FastISel didn't lower all arguments");
1264 // Use SelectionDAG argument lowering
1266 CurDAG->setRoot(SDB->getControlRoot());
1268 CodeGenAndEmitDAG();
1271 // If we inserted any instructions at the beginning, make a note of
1272 // where they are, so we can be sure to emit subsequent instructions
1274 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1275 FastIS->setLastLocalValue(std::prev(FuncInfo->InsertPt));
1277 FastIS->setLastLocalValue(nullptr);
1280 unsigned NumFastIselRemaining = std::distance(Begin, End);
1281 // Do FastISel on as many instructions as possible.
1282 for (; BI != Begin; --BI) {
1283 const Instruction *Inst = &*std::prev(BI);
1285 // If we no longer require this instruction, skip it.
1286 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1287 --NumFastIselRemaining;
1291 // Bottom-up: reset the insert pos at the top, after any local-value
1293 FastIS->recomputeInsertPt();
1295 // Try to select the instruction with FastISel.
1296 if (FastIS->selectInstruction(Inst)) {
1297 --NumFastIselRemaining;
1298 ++NumFastIselSuccess;
1299 // If fast isel succeeded, skip over all the folded instructions, and
1300 // then see if there is a load right before the selected instructions.
1301 // Try to fold the load if so.
1302 const Instruction *BeforeInst = Inst;
1303 while (BeforeInst != &*Begin) {
1304 BeforeInst = &*std::prev(BasicBlock::const_iterator(BeforeInst));
1305 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1308 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1309 BeforeInst->hasOneUse() &&
1310 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) {
1311 // If we succeeded, don't re-select the load.
1312 BI = std::next(BasicBlock::const_iterator(BeforeInst));
1313 --NumFastIselRemaining;
1314 ++NumFastIselSuccess;
1320 if (EnableFastISelVerbose2)
1321 collectFailStats(Inst);
1324 // Then handle certain instructions as single-LLVM-Instruction blocks.
1325 if (isa<CallInst>(Inst)) {
1327 if (EnableFastISelVerbose || EnableFastISelAbort) {
1328 dbgs() << "FastISel missed call: ";
1331 if (EnableFastISelAbort > 2)
1332 // FastISel selector couldn't handle something and bailed.
1333 // For the purpose of debugging, just abort.
1334 report_fatal_error("FastISel didn't select the entire block");
1336 if (!Inst->getType()->isVoidTy() && !Inst->getType()->isTokenTy() &&
1337 !Inst->use_empty()) {
1338 unsigned &R = FuncInfo->ValueMap[Inst];
1340 R = FuncInfo->CreateRegs(Inst->getType());
1343 bool HadTailCall = false;
1344 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1345 SelectBasicBlock(Inst->getIterator(), BI, HadTailCall);
1347 // If the call was emitted as a tail call, we're done with the block.
1348 // We also need to delete any previously emitted instructions.
1350 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1355 // Recompute NumFastIselRemaining as Selection DAG instruction
1356 // selection may have handled the call, input args, etc.
1357 unsigned RemainingNow = std::distance(Begin, BI);
1358 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1359 NumFastIselRemaining = RemainingNow;
1363 bool ShouldAbort = EnableFastISelAbort;
1364 if (EnableFastISelVerbose || EnableFastISelAbort) {
1365 if (isa<TerminatorInst>(Inst)) {
1366 // Use a different message for terminator misses.
1367 dbgs() << "FastISel missed terminator: ";
1368 // Don't abort unless for terminator unless the level is really high
1369 ShouldAbort = (EnableFastISelAbort > 2);
1371 dbgs() << "FastISel miss: ";
1376 // FastISel selector couldn't handle something and bailed.
1377 // For the purpose of debugging, just abort.
1378 report_fatal_error("FastISel didn't select the entire block");
1380 NumFastIselFailures += NumFastIselRemaining;
1384 FastIS->recomputeInsertPt();
1386 // Lower any arguments needed in this block if this is the entry block.
1387 if (LLVMBB == &Fn.getEntryBlock()) {
1396 ++NumFastIselBlocks;
1399 // Run SelectionDAG instruction selection on the remainder of the block
1400 // not handled by FastISel. If FastISel is not run, this is the entire
1403 SelectBasicBlock(Begin, BI, HadTailCall);
1407 FuncInfo->PHINodesToUpdate.clear();
1411 SDB->clearDanglingDebugInfo();
1412 SDB->SPDescriptor.resetPerFunctionState();
1415 /// Given that the input MI is before a partial terminator sequence TSeq, return
1416 /// true if M + TSeq also a partial terminator sequence.
1418 /// A Terminator sequence is a sequence of MachineInstrs which at this point in
1419 /// lowering copy vregs into physical registers, which are then passed into
1420 /// terminator instructors so we can satisfy ABI constraints. A partial
1421 /// terminator sequence is an improper subset of a terminator sequence (i.e. it
1422 /// may be the whole terminator sequence).
1423 static bool MIIsInTerminatorSequence(const MachineInstr *MI) {
1424 // If we do not have a copy or an implicit def, we return true if and only if
1425 // MI is a debug value.
1426 if (!MI->isCopy() && !MI->isImplicitDef())
1427 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the
1428 // physical registers if there is debug info associated with the terminator
1429 // of our mbb. We want to include said debug info in our terminator
1430 // sequence, so we return true in that case.
1431 return MI->isDebugValue();
1433 // We have left the terminator sequence if we are not doing one of the
1436 // 1. Copying a vreg into a physical register.
1437 // 2. Copying a vreg into a vreg.
1438 // 3. Defining a register via an implicit def.
1440 // OPI should always be a register definition...
1441 MachineInstr::const_mop_iterator OPI = MI->operands_begin();
1442 if (!OPI->isReg() || !OPI->isDef())
1445 // Defining any register via an implicit def is always ok.
1446 if (MI->isImplicitDef())
1449 // Grab the copy source...
1450 MachineInstr::const_mop_iterator OPI2 = OPI;
1452 assert(OPI2 != MI->operands_end()
1453 && "Should have a copy implying we should have 2 arguments.");
1455 // Make sure that the copy dest is not a vreg when the copy source is a
1456 // physical register.
1457 if (!OPI2->isReg() ||
1458 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) &&
1459 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg())))
1465 /// Find the split point at which to splice the end of BB into its success stack
1466 /// protector check machine basic block.
1468 /// On many platforms, due to ABI constraints, terminators, even before register
1469 /// allocation, use physical registers. This creates an issue for us since
1470 /// physical registers at this point can not travel across basic
1471 /// blocks. Luckily, selectiondag always moves physical registers into vregs
1472 /// when they enter functions and moves them through a sequence of copies back
1473 /// into the physical registers right before the terminator creating a
1474 /// ``Terminator Sequence''. This function is searching for the beginning of the
1475 /// terminator sequence so that we can ensure that we splice off not just the
1476 /// terminator, but additionally the copies that move the vregs into the
1477 /// physical registers.
1478 static MachineBasicBlock::iterator
1479 FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) {
1480 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator();
1482 if (SplitPoint == BB->begin())
1485 MachineBasicBlock::iterator Start = BB->begin();
1486 MachineBasicBlock::iterator Previous = SplitPoint;
1489 while (MIIsInTerminatorSequence(Previous)) {
1490 SplitPoint = Previous;
1491 if (Previous == Start)
1500 SelectionDAGISel::FinishBasicBlock() {
1502 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1503 << FuncInfo->PHINodesToUpdate.size() << "\n";
1504 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1505 dbgs() << "Node " << i << " : ("
1506 << FuncInfo->PHINodesToUpdate[i].first
1507 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1509 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1510 // PHI nodes in successors.
1511 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1512 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1513 assert(PHI->isPHI() &&
1514 "This is not a machine PHI node that we are updating!");
1515 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1517 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1520 // Handle stack protector.
1521 if (SDB->SPDescriptor.shouldEmitStackProtector()) {
1522 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB();
1523 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB();
1525 // Find the split point to split the parent mbb. At the same time copy all
1526 // physical registers used in the tail of parent mbb into virtual registers
1527 // before the split point and back into physical registers after the split
1528 // point. This prevents us needing to deal with Live-ins and many other
1529 // register allocation issues caused by us splitting the parent mbb. The
1530 // register allocator will clean up said virtual copies later on.
1531 MachineBasicBlock::iterator SplitPoint =
1532 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc());
1534 // Splice the terminator of ParentMBB into SuccessMBB.
1535 SuccessMBB->splice(SuccessMBB->end(), ParentMBB,
1539 // Add compare/jump on neq/jump to the parent BB.
1540 FuncInfo->MBB = ParentMBB;
1541 FuncInfo->InsertPt = ParentMBB->end();
1542 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB);
1543 CurDAG->setRoot(SDB->getRoot());
1545 CodeGenAndEmitDAG();
1547 // CodeGen Failure MBB if we have not codegened it yet.
1548 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB();
1549 if (!FailureMBB->size()) {
1550 FuncInfo->MBB = FailureMBB;
1551 FuncInfo->InsertPt = FailureMBB->end();
1552 SDB->visitSPDescriptorFailure(SDB->SPDescriptor);
1553 CurDAG->setRoot(SDB->getRoot());
1555 CodeGenAndEmitDAG();
1558 // Clear the Per-BB State.
1559 SDB->SPDescriptor.resetPerBBState();
1562 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1563 // Lower header first, if it wasn't already lowered
1564 if (!SDB->BitTestCases[i].Emitted) {
1565 // Set the current basic block to the mbb we wish to insert the code into
1566 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1567 FuncInfo->InsertPt = FuncInfo->MBB->end();
1569 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1570 CurDAG->setRoot(SDB->getRoot());
1572 CodeGenAndEmitDAG();
1575 BranchProbability UnhandledProb = SDB->BitTestCases[i].Prob;
1576 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1577 UnhandledProb -= SDB->BitTestCases[i].Cases[j].ExtraProb;
1578 // Set the current basic block to the mbb we wish to insert the code into
1579 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1580 FuncInfo->InsertPt = FuncInfo->MBB->end();
1583 // If all cases cover a contiguous range, it is not necessary to jump to
1584 // the default block after the last bit test fails. This is because the
1585 // range check during bit test header creation has guaranteed that every
1586 // case here doesn't go outside the range.
1587 MachineBasicBlock *NextMBB;
1588 if (SDB->BitTestCases[i].ContiguousRange && j + 2 == ej)
1589 NextMBB = SDB->BitTestCases[i].Cases[j + 1].TargetBB;
1590 else if (j + 1 != ej)
1591 NextMBB = SDB->BitTestCases[i].Cases[j + 1].ThisBB;
1593 NextMBB = SDB->BitTestCases[i].Default;
1595 SDB->visitBitTestCase(SDB->BitTestCases[i],
1598 SDB->BitTestCases[i].Reg,
1599 SDB->BitTestCases[i].Cases[j],
1602 CurDAG->setRoot(SDB->getRoot());
1604 CodeGenAndEmitDAG();
1606 if (SDB->BitTestCases[i].ContiguousRange && j + 2 == ej)
1611 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1613 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1614 MachineBasicBlock *PHIBB = PHI->getParent();
1615 assert(PHI->isPHI() &&
1616 "This is not a machine PHI node that we are updating!");
1617 // This is "default" BB. We have two jumps to it. From "header" BB and
1618 // from last "case" BB.
1619 if (PHIBB == SDB->BitTestCases[i].Default)
1620 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1621 .addMBB(SDB->BitTestCases[i].Parent)
1622 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1623 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1624 // One of "cases" BB.
1625 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1627 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1628 if (cBB->isSuccessor(PHIBB))
1629 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1633 SDB->BitTestCases.clear();
1635 // If the JumpTable record is filled in, then we need to emit a jump table.
1636 // Updating the PHI nodes is tricky in this case, since we need to determine
1637 // whether the PHI is a successor of the range check MBB or the jump table MBB
1638 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1639 // Lower header first, if it wasn't already lowered
1640 if (!SDB->JTCases[i].first.Emitted) {
1641 // Set the current basic block to the mbb we wish to insert the code into
1642 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1643 FuncInfo->InsertPt = FuncInfo->MBB->end();
1645 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1647 CurDAG->setRoot(SDB->getRoot());
1649 CodeGenAndEmitDAG();
1652 // Set the current basic block to the mbb we wish to insert the code into
1653 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1654 FuncInfo->InsertPt = FuncInfo->MBB->end();
1656 SDB->visitJumpTable(SDB->JTCases[i].second);
1657 CurDAG->setRoot(SDB->getRoot());
1659 CodeGenAndEmitDAG();
1662 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1664 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1665 MachineBasicBlock *PHIBB = PHI->getParent();
1666 assert(PHI->isPHI() &&
1667 "This is not a machine PHI node that we are updating!");
1668 // "default" BB. We can go there only from header BB.
1669 if (PHIBB == SDB->JTCases[i].second.Default)
1670 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1671 .addMBB(SDB->JTCases[i].first.HeaderBB);
1672 // JT BB. Just iterate over successors here
1673 if (FuncInfo->MBB->isSuccessor(PHIBB))
1674 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1677 SDB->JTCases.clear();
1679 // If we generated any switch lowering information, build and codegen any
1680 // additional DAGs necessary.
1681 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1682 // Set the current basic block to the mbb we wish to insert the code into
1683 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1684 FuncInfo->InsertPt = FuncInfo->MBB->end();
1686 // Determine the unique successors.
1687 SmallVector<MachineBasicBlock *, 2> Succs;
1688 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1689 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1690 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1692 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1693 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1694 CurDAG->setRoot(SDB->getRoot());
1696 CodeGenAndEmitDAG();
1698 // Remember the last block, now that any splitting is done, for use in
1699 // populating PHI nodes in successors.
1700 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1702 // Handle any PHI nodes in successors of this chunk, as if we were coming
1703 // from the original BB before switch expansion. Note that PHI nodes can
1704 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1705 // handle them the right number of times.
1706 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1707 FuncInfo->MBB = Succs[i];
1708 FuncInfo->InsertPt = FuncInfo->MBB->end();
1709 // FuncInfo->MBB may have been removed from the CFG if a branch was
1711 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1712 for (MachineBasicBlock::iterator
1713 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1714 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1715 MachineInstrBuilder PHI(*MF, MBBI);
1716 // This value for this PHI node is recorded in PHINodesToUpdate.
1717 for (unsigned pn = 0; ; ++pn) {
1718 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1719 "Didn't find PHI entry!");
1720 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1721 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1729 SDB->SwitchCases.clear();
1733 /// Create the scheduler. If a specific scheduler was specified
1734 /// via the SchedulerRegistry, use it, otherwise select the
1735 /// one preferred by the target.
1737 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1738 return ISHeuristic(this, OptLevel);
1741 //===----------------------------------------------------------------------===//
1742 // Helper functions used by the generated instruction selector.
1743 //===----------------------------------------------------------------------===//
1744 // Calls to these methods are generated by tblgen.
1746 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1747 /// the dag combiner simplified the 255, we still want to match. RHS is the
1748 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1749 /// specified in the .td file (e.g. 255).
1750 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1751 int64_t DesiredMaskS) const {
1752 const APInt &ActualMask = RHS->getAPIntValue();
1753 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1755 // If the actual mask exactly matches, success!
1756 if (ActualMask == DesiredMask)
1759 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1760 if (ActualMask.intersects(~DesiredMask))
1763 // Otherwise, the DAG Combiner may have proven that the value coming in is
1764 // either already zero or is not demanded. Check for known zero input bits.
1765 APInt NeededMask = DesiredMask & ~ActualMask;
1766 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1769 // TODO: check to see if missing bits are just not demanded.
1771 // Otherwise, this pattern doesn't match.
1775 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1776 /// the dag combiner simplified the 255, we still want to match. RHS is the
1777 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1778 /// specified in the .td file (e.g. 255).
1779 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1780 int64_t DesiredMaskS) const {
1781 const APInt &ActualMask = RHS->getAPIntValue();
1782 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1784 // If the actual mask exactly matches, success!
1785 if (ActualMask == DesiredMask)
1788 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1789 if (ActualMask.intersects(~DesiredMask))
1792 // Otherwise, the DAG Combiner may have proven that the value coming in is
1793 // either already zero or is not demanded. Check for known zero input bits.
1794 APInt NeededMask = DesiredMask & ~ActualMask;
1796 APInt KnownZero, KnownOne;
1797 CurDAG->computeKnownBits(LHS, KnownZero, KnownOne);
1799 // If all the missing bits in the or are already known to be set, match!
1800 if ((NeededMask & KnownOne) == NeededMask)
1803 // TODO: check to see if missing bits are just not demanded.
1805 // Otherwise, this pattern doesn't match.
1809 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1810 /// by tblgen. Others should not call it.
1811 void SelectionDAGISel::
1812 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, SDLoc DL) {
1813 std::vector<SDValue> InOps;
1814 std::swap(InOps, Ops);
1816 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1817 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1818 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1819 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1821 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1822 if (InOps[e-1].getValueType() == MVT::Glue)
1823 --e; // Don't process a glue operand if it is here.
1826 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1827 if (!InlineAsm::isMemKind(Flags)) {
1828 // Just skip over this operand, copying the operands verbatim.
1829 Ops.insert(Ops.end(), InOps.begin()+i,
1830 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1831 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1833 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1834 "Memory operand with multiple values?");
1836 unsigned TiedToOperand;
1837 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedToOperand)) {
1838 // We need the constraint ID from the operand this is tied to.
1839 unsigned CurOp = InlineAsm::Op_FirstOperand;
1840 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
1841 for (; TiedToOperand; --TiedToOperand) {
1842 CurOp += InlineAsm::getNumOperandRegisters(Flags)+1;
1843 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
1847 // Otherwise, this is a memory operand. Ask the target to select it.
1848 std::vector<SDValue> SelOps;
1849 if (SelectInlineAsmMemoryOperand(InOps[i+1],
1850 InlineAsm::getMemoryConstraintID(Flags),
1852 report_fatal_error("Could not match memory address. Inline asm"
1855 // Add this to the output node.
1857 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1858 Ops.push_back(CurDAG->getTargetConstant(NewFlags, DL, MVT::i32));
1859 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1864 // Add the glue input back if present.
1865 if (e != InOps.size())
1866 Ops.push_back(InOps.back());
1869 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1872 static SDNode *findGlueUse(SDNode *N) {
1873 unsigned FlagResNo = N->getNumValues()-1;
1874 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1875 SDUse &Use = I.getUse();
1876 if (Use.getResNo() == FlagResNo)
1877 return Use.getUser();
1882 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1883 /// This function recursively traverses up the operand chain, ignoring
1885 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1886 SDNode *Root, SmallPtrSetImpl<SDNode*> &Visited,
1887 bool IgnoreChains) {
1888 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1889 // greater than all of its (recursive) operands. If we scan to a point where
1890 // 'use' is smaller than the node we're scanning for, then we know we will
1893 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1894 // happen because we scan down to newly selected nodes in the case of glue
1896 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1899 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1900 // won't fail if we scan it again.
1901 if (!Visited.insert(Use).second)
1904 for (const SDValue &Op : Use->op_values()) {
1905 // Ignore chain uses, they are validated by HandleMergeInputChains.
1906 if (Op.getValueType() == MVT::Other && IgnoreChains)
1909 SDNode *N = Op.getNode();
1911 if (Use == ImmedUse || Use == Root)
1912 continue; // We are not looking for immediate use.
1917 // Traverse up the operand chain.
1918 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1924 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1925 /// operand node N of U during instruction selection that starts at Root.
1926 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1927 SDNode *Root) const {
1928 if (OptLevel == CodeGenOpt::None) return false;
1929 return N.hasOneUse();
1932 /// IsLegalToFold - Returns true if the specific operand node N of
1933 /// U can be folded during instruction selection that starts at Root.
1934 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1935 CodeGenOpt::Level OptLevel,
1936 bool IgnoreChains) {
1937 if (OptLevel == CodeGenOpt::None) return false;
1939 // If Root use can somehow reach N through a path that that doesn't contain
1940 // U then folding N would create a cycle. e.g. In the following
1941 // diagram, Root can reach N through X. If N is folded into into Root, then
1942 // X is both a predecessor and a successor of U.
1953 // * indicates nodes to be folded together.
1955 // If Root produces glue, then it gets (even more) interesting. Since it
1956 // will be "glued" together with its glue use in the scheduler, we need to
1957 // check if it might reach N.
1976 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1977 // (call it Fold), then X is a predecessor of GU and a successor of
1978 // Fold. But since Fold and GU are glued together, this will create
1979 // a cycle in the scheduling graph.
1981 // If the node has glue, walk down the graph to the "lowest" node in the
1983 EVT VT = Root->getValueType(Root->getNumValues()-1);
1984 while (VT == MVT::Glue) {
1985 SDNode *GU = findGlueUse(Root);
1989 VT = Root->getValueType(Root->getNumValues()-1);
1991 // If our query node has a glue result with a use, we've walked up it. If
1992 // the user (which has already been selected) has a chain or indirectly uses
1993 // the chain, our WalkChainUsers predicate will not consider it. Because of
1994 // this, we cannot ignore chains in this predicate.
1995 IgnoreChains = false;
1999 SmallPtrSet<SDNode*, 16> Visited;
2000 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
2003 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
2006 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
2007 SelectInlineAsmMemoryOperands(Ops, DL);
2009 const EVT VTs[] = {MVT::Other, MVT::Glue};
2010 SDValue New = CurDAG->getNode(ISD::INLINEASM, DL, VTs, Ops);
2012 return New.getNode();
2016 *SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) {
2018 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
2019 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
2021 TLI->getRegisterByName(RegStr->getString().data(), Op->getValueType(0),
2023 SDValue New = CurDAG->getCopyFromReg(
2024 Op->getOperand(0), dl, Reg, Op->getValueType(0));
2026 return New.getNode();
2030 *SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) {
2032 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
2033 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
2034 unsigned Reg = TLI->getRegisterByName(RegStr->getString().data(),
2035 Op->getOperand(2).getValueType(),
2037 SDValue New = CurDAG->getCopyToReg(
2038 Op->getOperand(0), dl, Reg, Op->getOperand(2));
2040 return New.getNode();
2045 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
2046 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
2049 /// GetVBR - decode a vbr encoding whose top bit is set.
2050 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline uint64_t
2051 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
2052 assert(Val >= 128 && "Not a VBR");
2053 Val &= 127; // Remove first vbr bit.
2058 NextBits = MatcherTable[Idx++];
2059 Val |= (NextBits&127) << Shift;
2061 } while (NextBits & 128);
2067 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
2068 /// interior glue and chain results to use the new glue and chain results.
2069 void SelectionDAGISel::
2070 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
2071 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
2073 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
2074 bool isMorphNodeTo) {
2075 SmallVector<SDNode*, 4> NowDeadNodes;
2077 // Now that all the normal results are replaced, we replace the chain and
2078 // glue results if present.
2079 if (!ChainNodesMatched.empty()) {
2080 assert(InputChain.getNode() &&
2081 "Matched input chains but didn't produce a chain");
2082 // Loop over all of the nodes we matched that produced a chain result.
2083 // Replace all the chain results with the final chain we ended up with.
2084 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2085 SDNode *ChainNode = ChainNodesMatched[i];
2087 // If this node was already deleted, don't look at it.
2088 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
2091 // Don't replace the results of the root node if we're doing a
2093 if (ChainNode == NodeToMatch && isMorphNodeTo)
2096 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
2097 if (ChainVal.getValueType() == MVT::Glue)
2098 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
2099 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
2100 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
2102 // If the node became dead and we haven't already seen it, delete it.
2103 if (ChainNode->use_empty() &&
2104 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
2105 NowDeadNodes.push_back(ChainNode);
2109 // If the result produces glue, update any glue results in the matched
2110 // pattern with the glue result.
2111 if (InputGlue.getNode()) {
2112 // Handle any interior nodes explicitly marked.
2113 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
2114 SDNode *FRN = GlueResultNodesMatched[i];
2116 // If this node was already deleted, don't look at it.
2117 if (FRN->getOpcode() == ISD::DELETED_NODE)
2120 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
2121 "Doesn't have a glue result");
2122 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
2125 // If the node became dead and we haven't already seen it, delete it.
2126 if (FRN->use_empty() &&
2127 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
2128 NowDeadNodes.push_back(FRN);
2132 if (!NowDeadNodes.empty())
2133 CurDAG->RemoveDeadNodes(NowDeadNodes);
2135 DEBUG(dbgs() << "ISEL: Match complete!\n");
2141 CR_LeadsToInteriorNode
2144 /// WalkChainUsers - Walk down the users of the specified chained node that is
2145 /// part of the pattern we're matching, looking at all of the users we find.
2146 /// This determines whether something is an interior node, whether we have a
2147 /// non-pattern node in between two pattern nodes (which prevent folding because
2148 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
2149 /// between pattern nodes (in which case the TF becomes part of the pattern).
2151 /// The walk we do here is guaranteed to be small because we quickly get down to
2152 /// already selected nodes "below" us.
2154 WalkChainUsers(const SDNode *ChainedNode,
2155 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
2156 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
2157 ChainResult Result = CR_Simple;
2159 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
2160 E = ChainedNode->use_end(); UI != E; ++UI) {
2161 // Make sure the use is of the chain, not some other value we produce.
2162 if (UI.getUse().getValueType() != MVT::Other) continue;
2166 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
2169 // If we see an already-selected machine node, then we've gone beyond the
2170 // pattern that we're selecting down into the already selected chunk of the
2172 unsigned UserOpcode = User->getOpcode();
2173 if (User->isMachineOpcode() ||
2174 UserOpcode == ISD::CopyToReg ||
2175 UserOpcode == ISD::CopyFromReg ||
2176 UserOpcode == ISD::INLINEASM ||
2177 UserOpcode == ISD::EH_LABEL ||
2178 UserOpcode == ISD::LIFETIME_START ||
2179 UserOpcode == ISD::LIFETIME_END) {
2180 // If their node ID got reset to -1 then they've already been selected.
2181 // Treat them like a MachineOpcode.
2182 if (User->getNodeId() == -1)
2186 // If we have a TokenFactor, we handle it specially.
2187 if (User->getOpcode() != ISD::TokenFactor) {
2188 // If the node isn't a token factor and isn't part of our pattern, then it
2189 // must be a random chained node in between two nodes we're selecting.
2190 // This happens when we have something like:
2195 // Because we structurally match the load/store as a read/modify/write,
2196 // but the call is chained between them. We cannot fold in this case
2197 // because it would induce a cycle in the graph.
2198 if (!std::count(ChainedNodesInPattern.begin(),
2199 ChainedNodesInPattern.end(), User))
2200 return CR_InducesCycle;
2202 // Otherwise we found a node that is part of our pattern. For example in:
2206 // This would happen when we're scanning down from the load and see the
2207 // store as a user. Record that there is a use of ChainedNode that is
2208 // part of the pattern and keep scanning uses.
2209 Result = CR_LeadsToInteriorNode;
2210 InteriorChainedNodes.push_back(User);
2214 // If we found a TokenFactor, there are two cases to consider: first if the
2215 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
2216 // uses of the TF are in our pattern) we just want to ignore it. Second,
2217 // the TokenFactor can be sandwiched in between two chained nodes, like so:
2223 // | \ DAG's like cheese
2226 // [TokenFactor] [Op]
2233 // In this case, the TokenFactor becomes part of our match and we rewrite it
2234 // as a new TokenFactor.
2236 // To distinguish these two cases, do a recursive walk down the uses.
2237 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
2239 // If the uses of the TokenFactor are just already-selected nodes, ignore
2240 // it, it is "below" our pattern.
2242 case CR_InducesCycle:
2243 // If the uses of the TokenFactor lead to nodes that are not part of our
2244 // pattern that are not selected, folding would turn this into a cycle,
2246 return CR_InducesCycle;
2247 case CR_LeadsToInteriorNode:
2248 break; // Otherwise, keep processing.
2251 // Okay, we know we're in the interesting interior case. The TokenFactor
2252 // is now going to be considered part of the pattern so that we rewrite its
2253 // uses (it may have uses that are not part of the pattern) with the
2254 // ultimate chain result of the generated code. We will also add its chain
2255 // inputs as inputs to the ultimate TokenFactor we create.
2256 Result = CR_LeadsToInteriorNode;
2257 ChainedNodesInPattern.push_back(User);
2258 InteriorChainedNodes.push_back(User);
2265 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
2266 /// operation for when the pattern matched at least one node with a chains. The
2267 /// input vector contains a list of all of the chained nodes that we match. We
2268 /// must determine if this is a valid thing to cover (i.e. matching it won't
2269 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
2270 /// be used as the input node chain for the generated nodes.
2272 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
2273 SelectionDAG *CurDAG) {
2274 // Walk all of the chained nodes we've matched, recursively scanning down the
2275 // users of the chain result. This adds any TokenFactor nodes that are caught
2276 // in between chained nodes to the chained and interior nodes list.
2277 SmallVector<SDNode*, 3> InteriorChainedNodes;
2278 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2279 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
2280 InteriorChainedNodes) == CR_InducesCycle)
2281 return SDValue(); // Would induce a cycle.
2284 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
2285 // that we are interested in. Form our input TokenFactor node.
2286 SmallVector<SDValue, 3> InputChains;
2287 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2288 // Add the input chain of this node to the InputChains list (which will be
2289 // the operands of the generated TokenFactor) if it's not an interior node.
2290 SDNode *N = ChainNodesMatched[i];
2291 if (N->getOpcode() != ISD::TokenFactor) {
2292 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
2295 // Otherwise, add the input chain.
2296 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
2297 assert(InChain.getValueType() == MVT::Other && "Not a chain");
2298 InputChains.push_back(InChain);
2302 // If we have a token factor, we want to add all inputs of the token factor
2303 // that are not part of the pattern we're matching.
2304 for (const SDValue &Op : N->op_values()) {
2305 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
2307 InputChains.push_back(Op);
2311 if (InputChains.size() == 1)
2312 return InputChains[0];
2313 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
2314 MVT::Other, InputChains);
2317 /// MorphNode - Handle morphing a node in place for the selector.
2318 SDNode *SelectionDAGISel::
2319 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
2320 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo) {
2321 // It is possible we're using MorphNodeTo to replace a node with no
2322 // normal results with one that has a normal result (or we could be
2323 // adding a chain) and the input could have glue and chains as well.
2324 // In this case we need to shift the operands down.
2325 // FIXME: This is a horrible hack and broken in obscure cases, no worse
2326 // than the old isel though.
2327 int OldGlueResultNo = -1, OldChainResultNo = -1;
2329 unsigned NTMNumResults = Node->getNumValues();
2330 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
2331 OldGlueResultNo = NTMNumResults-1;
2332 if (NTMNumResults != 1 &&
2333 Node->getValueType(NTMNumResults-2) == MVT::Other)
2334 OldChainResultNo = NTMNumResults-2;
2335 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
2336 OldChainResultNo = NTMNumResults-1;
2338 // Call the underlying SelectionDAG routine to do the transmogrification. Note
2339 // that this deletes operands of the old node that become dead.
2340 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops);
2342 // MorphNodeTo can operate in two ways: if an existing node with the
2343 // specified operands exists, it can just return it. Otherwise, it
2344 // updates the node in place to have the requested operands.
2346 // If we updated the node in place, reset the node ID. To the isel,
2347 // this should be just like a newly allocated machine node.
2351 unsigned ResNumResults = Res->getNumValues();
2352 // Move the glue if needed.
2353 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
2354 (unsigned)OldGlueResultNo != ResNumResults-1)
2355 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
2356 SDValue(Res, ResNumResults-1));
2358 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
2361 // Move the chain reference if needed.
2362 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
2363 (unsigned)OldChainResultNo != ResNumResults-1)
2364 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2365 SDValue(Res, ResNumResults-1));
2367 // Otherwise, no replacement happened because the node already exists. Replace
2368 // Uses of the old node with the new one.
2370 CurDAG->ReplaceAllUsesWith(Node, Res);
2375 /// CheckSame - Implements OP_CheckSame.
2376 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2377 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2379 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2380 // Accept if it is exactly the same as a previously recorded node.
2381 unsigned RecNo = MatcherTable[MatcherIndex++];
2382 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2383 return N == RecordedNodes[RecNo].first;
2386 /// CheckChildSame - Implements OP_CheckChildXSame.
2387 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2388 CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2390 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes,
2392 if (ChildNo >= N.getNumOperands())
2393 return false; // Match fails if out of range child #.
2394 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo),
2398 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2399 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2400 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2401 const SelectionDAGISel &SDISel) {
2402 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2405 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2406 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2407 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2408 const SelectionDAGISel &SDISel, SDNode *N) {
2409 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2412 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2413 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2415 uint16_t Opc = MatcherTable[MatcherIndex++];
2416 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2417 return N->getOpcode() == Opc;
2420 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2421 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N,
2422 const TargetLowering *TLI, const DataLayout &DL) {
2423 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2424 if (N.getValueType() == VT) return true;
2426 // Handle the case when VT is iPTR.
2427 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy(DL);
2430 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2431 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2432 SDValue N, const TargetLowering *TLI, const DataLayout &DL,
2434 if (ChildNo >= N.getNumOperands())
2435 return false; // Match fails if out of range child #.
2436 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI,
2440 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2441 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2443 return cast<CondCodeSDNode>(N)->get() ==
2444 (ISD::CondCode)MatcherTable[MatcherIndex++];
2447 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2448 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2449 SDValue N, const TargetLowering *TLI, const DataLayout &DL) {
2450 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2451 if (cast<VTSDNode>(N)->getVT() == VT)
2454 // Handle the case when VT is iPTR.
2455 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy(DL);
2458 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2459 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2461 int64_t Val = MatcherTable[MatcherIndex++];
2463 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2465 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2466 return C && C->getSExtValue() == Val;
2469 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2470 CheckChildInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2471 SDValue N, unsigned ChildNo) {
2472 if (ChildNo >= N.getNumOperands())
2473 return false; // Match fails if out of range child #.
2474 return ::CheckInteger(MatcherTable, MatcherIndex, N.getOperand(ChildNo));
2477 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2478 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2479 SDValue N, const SelectionDAGISel &SDISel) {
2480 int64_t Val = MatcherTable[MatcherIndex++];
2482 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2484 if (N->getOpcode() != ISD::AND) return false;
2486 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2487 return C && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2490 LLVM_ATTRIBUTE_ALWAYS_INLINE static inline bool
2491 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2492 SDValue N, const SelectionDAGISel &SDISel) {
2493 int64_t Val = MatcherTable[MatcherIndex++];
2495 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2497 if (N->getOpcode() != ISD::OR) return false;
2499 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2500 return C && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2503 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2504 /// scope, evaluate the current node. If the current predicate is known to
2505 /// fail, set Result=true and return anything. If the current predicate is
2506 /// known to pass, set Result=false and return the MatcherIndex to continue
2507 /// with. If the current predicate is unknown, set Result=false and return the
2508 /// MatcherIndex to continue with.
2509 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2510 unsigned Index, SDValue N,
2512 const SelectionDAGISel &SDISel,
2513 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2514 switch (Table[Index++]) {
2517 return Index-1; // Could not evaluate this predicate.
2518 case SelectionDAGISel::OPC_CheckSame:
2519 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2521 case SelectionDAGISel::OPC_CheckChild0Same:
2522 case SelectionDAGISel::OPC_CheckChild1Same:
2523 case SelectionDAGISel::OPC_CheckChild2Same:
2524 case SelectionDAGISel::OPC_CheckChild3Same:
2525 Result = !::CheckChildSame(Table, Index, N, RecordedNodes,
2526 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same);
2528 case SelectionDAGISel::OPC_CheckPatternPredicate:
2529 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2531 case SelectionDAGISel::OPC_CheckPredicate:
2532 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2534 case SelectionDAGISel::OPC_CheckOpcode:
2535 Result = !::CheckOpcode(Table, Index, N.getNode());
2537 case SelectionDAGISel::OPC_CheckType:
2538 Result = !::CheckType(Table, Index, N, SDISel.TLI,
2539 SDISel.CurDAG->getDataLayout());
2541 case SelectionDAGISel::OPC_CheckChild0Type:
2542 case SelectionDAGISel::OPC_CheckChild1Type:
2543 case SelectionDAGISel::OPC_CheckChild2Type:
2544 case SelectionDAGISel::OPC_CheckChild3Type:
2545 case SelectionDAGISel::OPC_CheckChild4Type:
2546 case SelectionDAGISel::OPC_CheckChild5Type:
2547 case SelectionDAGISel::OPC_CheckChild6Type:
2548 case SelectionDAGISel::OPC_CheckChild7Type:
2549 Result = !::CheckChildType(
2550 Table, Index, N, SDISel.TLI, SDISel.CurDAG->getDataLayout(),
2551 Table[Index - 1] - SelectionDAGISel::OPC_CheckChild0Type);
2553 case SelectionDAGISel::OPC_CheckCondCode:
2554 Result = !::CheckCondCode(Table, Index, N);
2556 case SelectionDAGISel::OPC_CheckValueType:
2557 Result = !::CheckValueType(Table, Index, N, SDISel.TLI,
2558 SDISel.CurDAG->getDataLayout());
2560 case SelectionDAGISel::OPC_CheckInteger:
2561 Result = !::CheckInteger(Table, Index, N);
2563 case SelectionDAGISel::OPC_CheckChild0Integer:
2564 case SelectionDAGISel::OPC_CheckChild1Integer:
2565 case SelectionDAGISel::OPC_CheckChild2Integer:
2566 case SelectionDAGISel::OPC_CheckChild3Integer:
2567 case SelectionDAGISel::OPC_CheckChild4Integer:
2568 Result = !::CheckChildInteger(Table, Index, N,
2569 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Integer);
2571 case SelectionDAGISel::OPC_CheckAndImm:
2572 Result = !::CheckAndImm(Table, Index, N, SDISel);
2574 case SelectionDAGISel::OPC_CheckOrImm:
2575 Result = !::CheckOrImm(Table, Index, N, SDISel);
2583 /// FailIndex - If this match fails, this is the index to continue with.
2586 /// NodeStack - The node stack when the scope was formed.
2587 SmallVector<SDValue, 4> NodeStack;
2589 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2590 unsigned NumRecordedNodes;
2592 /// NumMatchedMemRefs - The number of matched memref entries.
2593 unsigned NumMatchedMemRefs;
2595 /// InputChain/InputGlue - The current chain/glue
2596 SDValue InputChain, InputGlue;
2598 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2599 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2602 /// \\brief A DAG update listener to keep the matching state
2603 /// (i.e. RecordedNodes and MatchScope) uptodate if the target is allowed to
2604 /// change the DAG while matching. X86 addressing mode matcher is an example
2606 class MatchStateUpdater : public SelectionDAG::DAGUpdateListener
2608 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes;
2609 SmallVectorImpl<MatchScope> &MatchScopes;
2611 MatchStateUpdater(SelectionDAG &DAG,
2612 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RN,
2613 SmallVectorImpl<MatchScope> &MS) :
2614 SelectionDAG::DAGUpdateListener(DAG),
2615 RecordedNodes(RN), MatchScopes(MS) { }
2617 void NodeDeleted(SDNode *N, SDNode *E) override {
2618 // Some early-returns here to avoid the search if we deleted the node or
2619 // if the update comes from MorphNodeTo (MorphNodeTo is the last thing we
2620 // do, so it's unnecessary to update matching state at that point).
2621 // Neither of these can occur currently because we only install this
2622 // update listener during matching a complex patterns.
2623 if (!E || E->isMachineOpcode())
2625 // Performing linear search here does not matter because we almost never
2626 // run this code. You'd have to have a CSE during complex pattern
2628 for (auto &I : RecordedNodes)
2629 if (I.first.getNode() == N)
2632 for (auto &I : MatchScopes)
2633 for (auto &J : I.NodeStack)
2634 if (J.getNode() == N)
2640 SDNode *SelectionDAGISel::
2641 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2642 unsigned TableSize) {
2643 // FIXME: Should these even be selected? Handle these cases in the caller?
2644 switch (NodeToMatch->getOpcode()) {
2647 case ISD::EntryToken: // These nodes remain the same.
2648 case ISD::BasicBlock:
2650 case ISD::RegisterMask:
2651 case ISD::HANDLENODE:
2652 case ISD::MDNODE_SDNODE:
2653 case ISD::TargetConstant:
2654 case ISD::TargetConstantFP:
2655 case ISD::TargetConstantPool:
2656 case ISD::TargetFrameIndex:
2657 case ISD::TargetExternalSymbol:
2659 case ISD::TargetBlockAddress:
2660 case ISD::TargetJumpTable:
2661 case ISD::TargetGlobalTLSAddress:
2662 case ISD::TargetGlobalAddress:
2663 case ISD::TokenFactor:
2664 case ISD::CopyFromReg:
2665 case ISD::CopyToReg:
2667 case ISD::LIFETIME_START:
2668 case ISD::LIFETIME_END:
2669 NodeToMatch->setNodeId(-1); // Mark selected.
2671 case ISD::AssertSext:
2672 case ISD::AssertZext:
2673 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2674 NodeToMatch->getOperand(0));
2676 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2677 case ISD::READ_REGISTER: return Select_READ_REGISTER(NodeToMatch);
2678 case ISD::WRITE_REGISTER: return Select_WRITE_REGISTER(NodeToMatch);
2679 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2682 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2684 // Set up the node stack with NodeToMatch as the only node on the stack.
2685 SmallVector<SDValue, 8> NodeStack;
2686 SDValue N = SDValue(NodeToMatch, 0);
2687 NodeStack.push_back(N);
2689 // MatchScopes - Scopes used when matching, if a match failure happens, this
2690 // indicates where to continue checking.
2691 SmallVector<MatchScope, 8> MatchScopes;
2693 // RecordedNodes - This is the set of nodes that have been recorded by the
2694 // state machine. The second value is the parent of the node, or null if the
2695 // root is recorded.
2696 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2698 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2700 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2702 // These are the current input chain and glue for use when generating nodes.
2703 // Various Emit operations change these. For example, emitting a copytoreg
2704 // uses and updates these.
2705 SDValue InputChain, InputGlue;
2707 // ChainNodesMatched - If a pattern matches nodes that have input/output
2708 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2709 // which ones they are. The result is captured into this list so that we can
2710 // update the chain results when the pattern is complete.
2711 SmallVector<SDNode*, 3> ChainNodesMatched;
2712 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2714 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: ";
2715 NodeToMatch->dump(CurDAG);
2718 // Determine where to start the interpreter. Normally we start at opcode #0,
2719 // but if the state machine starts with an OPC_SwitchOpcode, then we
2720 // accelerate the first lookup (which is guaranteed to be hot) with the
2721 // OpcodeOffset table.
2722 unsigned MatcherIndex = 0;
2724 if (!OpcodeOffset.empty()) {
2725 // Already computed the OpcodeOffset table, just index into it.
2726 if (N.getOpcode() < OpcodeOffset.size())
2727 MatcherIndex = OpcodeOffset[N.getOpcode()];
2728 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n");
2730 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2731 // Otherwise, the table isn't computed, but the state machine does start
2732 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2733 // is the first time we're selecting an instruction.
2736 // Get the size of this case.
2737 unsigned CaseSize = MatcherTable[Idx++];
2739 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2740 if (CaseSize == 0) break;
2742 // Get the opcode, add the index to the table.
2743 uint16_t Opc = MatcherTable[Idx++];
2744 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2745 if (Opc >= OpcodeOffset.size())
2746 OpcodeOffset.resize((Opc+1)*2);
2747 OpcodeOffset[Opc] = Idx;
2751 // Okay, do the lookup for the first opcode.
2752 if (N.getOpcode() < OpcodeOffset.size())
2753 MatcherIndex = OpcodeOffset[N.getOpcode()];
2757 assert(MatcherIndex < TableSize && "Invalid index");
2759 unsigned CurrentOpcodeIndex = MatcherIndex;
2761 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2764 // Okay, the semantics of this operation are that we should push a scope
2765 // then evaluate the first child. However, pushing a scope only to have
2766 // the first check fail (which then pops it) is inefficient. If we can
2767 // determine immediately that the first check (or first several) will
2768 // immediately fail, don't even bother pushing a scope for them.
2772 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2773 if (NumToSkip & 128)
2774 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2775 // Found the end of the scope with no match.
2776 if (NumToSkip == 0) {
2781 FailIndex = MatcherIndex+NumToSkip;
2783 unsigned MatcherIndexOfPredicate = MatcherIndex;
2784 (void)MatcherIndexOfPredicate; // silence warning.
2786 // If we can't evaluate this predicate without pushing a scope (e.g. if
2787 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2788 // push the scope and evaluate the full predicate chain.
2790 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2791 Result, *this, RecordedNodes);
2795 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at "
2796 << "index " << MatcherIndexOfPredicate
2797 << ", continuing at " << FailIndex << "\n");
2798 ++NumDAGIselRetries;
2800 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2801 // move to the next case.
2802 MatcherIndex = FailIndex;
2805 // If the whole scope failed to match, bail.
2806 if (FailIndex == 0) break;
2808 // Push a MatchScope which indicates where to go if the first child fails
2810 MatchScope NewEntry;
2811 NewEntry.FailIndex = FailIndex;
2812 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2813 NewEntry.NumRecordedNodes = RecordedNodes.size();
2814 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2815 NewEntry.InputChain = InputChain;
2816 NewEntry.InputGlue = InputGlue;
2817 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2818 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2819 MatchScopes.push_back(NewEntry);
2822 case OPC_RecordNode: {
2823 // Remember this node, it may end up being an operand in the pattern.
2824 SDNode *Parent = nullptr;
2825 if (NodeStack.size() > 1)
2826 Parent = NodeStack[NodeStack.size()-2].getNode();
2827 RecordedNodes.push_back(std::make_pair(N, Parent));
2831 case OPC_RecordChild0: case OPC_RecordChild1:
2832 case OPC_RecordChild2: case OPC_RecordChild3:
2833 case OPC_RecordChild4: case OPC_RecordChild5:
2834 case OPC_RecordChild6: case OPC_RecordChild7: {
2835 unsigned ChildNo = Opcode-OPC_RecordChild0;
2836 if (ChildNo >= N.getNumOperands())
2837 break; // Match fails if out of range child #.
2839 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2843 case OPC_RecordMemRef:
2844 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2847 case OPC_CaptureGlueInput:
2848 // If the current node has an input glue, capture it in InputGlue.
2849 if (N->getNumOperands() != 0 &&
2850 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2851 InputGlue = N->getOperand(N->getNumOperands()-1);
2854 case OPC_MoveChild: {
2855 unsigned ChildNo = MatcherTable[MatcherIndex++];
2856 if (ChildNo >= N.getNumOperands())
2857 break; // Match fails if out of range child #.
2858 N = N.getOperand(ChildNo);
2859 NodeStack.push_back(N);
2863 case OPC_MoveParent:
2864 // Pop the current node off the NodeStack.
2865 NodeStack.pop_back();
2866 assert(!NodeStack.empty() && "Node stack imbalance!");
2867 N = NodeStack.back();
2871 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2874 case OPC_CheckChild0Same: case OPC_CheckChild1Same:
2875 case OPC_CheckChild2Same: case OPC_CheckChild3Same:
2876 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes,
2877 Opcode-OPC_CheckChild0Same))
2881 case OPC_CheckPatternPredicate:
2882 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2884 case OPC_CheckPredicate:
2885 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2889 case OPC_CheckComplexPat: {
2890 unsigned CPNum = MatcherTable[MatcherIndex++];
2891 unsigned RecNo = MatcherTable[MatcherIndex++];
2892 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2894 // If target can modify DAG during matching, keep the matching state
2896 std::unique_ptr<MatchStateUpdater> MSU;
2897 if (ComplexPatternFuncMutatesDAG())
2898 MSU.reset(new MatchStateUpdater(*CurDAG, RecordedNodes,
2901 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2902 RecordedNodes[RecNo].first, CPNum,
2907 case OPC_CheckOpcode:
2908 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2912 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI,
2913 CurDAG->getDataLayout()))
2917 case OPC_SwitchOpcode: {
2918 unsigned CurNodeOpcode = N.getOpcode();
2919 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2922 // Get the size of this case.
2923 CaseSize = MatcherTable[MatcherIndex++];
2925 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2926 if (CaseSize == 0) break;
2928 uint16_t Opc = MatcherTable[MatcherIndex++];
2929 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2931 // If the opcode matches, then we will execute this case.
2932 if (CurNodeOpcode == Opc)
2935 // Otherwise, skip over this case.
2936 MatcherIndex += CaseSize;
2939 // If no cases matched, bail out.
2940 if (CaseSize == 0) break;
2942 // Otherwise, execute the case we found.
2943 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart
2944 << " to " << MatcherIndex << "\n");
2948 case OPC_SwitchType: {
2949 MVT CurNodeVT = N.getSimpleValueType();
2950 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2953 // Get the size of this case.
2954 CaseSize = MatcherTable[MatcherIndex++];
2956 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2957 if (CaseSize == 0) break;
2959 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2960 if (CaseVT == MVT::iPTR)
2961 CaseVT = TLI->getPointerTy(CurDAG->getDataLayout());
2963 // If the VT matches, then we will execute this case.
2964 if (CurNodeVT == CaseVT)
2967 // Otherwise, skip over this case.
2968 MatcherIndex += CaseSize;
2971 // If no cases matched, bail out.
2972 if (CaseSize == 0) break;
2974 // Otherwise, execute the case we found.
2975 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2976 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2979 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2980 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2981 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2982 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2983 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2984 CurDAG->getDataLayout(),
2985 Opcode - OPC_CheckChild0Type))
2988 case OPC_CheckCondCode:
2989 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2991 case OPC_CheckValueType:
2992 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI,
2993 CurDAG->getDataLayout()))
2996 case OPC_CheckInteger:
2997 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2999 case OPC_CheckChild0Integer: case OPC_CheckChild1Integer:
3000 case OPC_CheckChild2Integer: case OPC_CheckChild3Integer:
3001 case OPC_CheckChild4Integer:
3002 if (!::CheckChildInteger(MatcherTable, MatcherIndex, N,
3003 Opcode-OPC_CheckChild0Integer)) break;
3005 case OPC_CheckAndImm:
3006 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
3008 case OPC_CheckOrImm:
3009 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
3012 case OPC_CheckFoldableChainNode: {
3013 assert(NodeStack.size() != 1 && "No parent node");
3014 // Verify that all intermediate nodes between the root and this one have
3016 bool HasMultipleUses = false;
3017 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
3018 if (!NodeStack[i].hasOneUse()) {
3019 HasMultipleUses = true;
3022 if (HasMultipleUses) break;
3024 // Check to see that the target thinks this is profitable to fold and that
3025 // we can fold it without inducing cycles in the graph.
3026 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
3028 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
3029 NodeToMatch, OptLevel,
3030 true/*We validate our own chains*/))
3035 case OPC_EmitInteger: {
3036 MVT::SimpleValueType VT =
3037 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3038 int64_t Val = MatcherTable[MatcherIndex++];
3040 Val = GetVBR(Val, MatcherTable, MatcherIndex);
3041 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
3042 CurDAG->getTargetConstant(Val, SDLoc(NodeToMatch),
3046 case OPC_EmitRegister: {
3047 MVT::SimpleValueType VT =
3048 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3049 unsigned RegNo = MatcherTable[MatcherIndex++];
3050 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
3051 CurDAG->getRegister(RegNo, VT), nullptr));
3054 case OPC_EmitRegister2: {
3055 // For targets w/ more than 256 register names, the register enum
3056 // values are stored in two bytes in the matcher table (just like
3058 MVT::SimpleValueType VT =
3059 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3060 unsigned RegNo = MatcherTable[MatcherIndex++];
3061 RegNo |= MatcherTable[MatcherIndex++] << 8;
3062 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
3063 CurDAG->getRegister(RegNo, VT), nullptr));
3067 case OPC_EmitConvertToTarget: {
3068 // Convert from IMM/FPIMM to target version.
3069 unsigned RecNo = MatcherTable[MatcherIndex++];
3070 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget");
3071 SDValue Imm = RecordedNodes[RecNo].first;
3073 if (Imm->getOpcode() == ISD::Constant) {
3074 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
3075 Imm = CurDAG->getConstant(*Val, SDLoc(NodeToMatch), Imm.getValueType(),
3077 } else if (Imm->getOpcode() == ISD::ConstantFP) {
3078 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
3079 Imm = CurDAG->getConstantFP(*Val, SDLoc(NodeToMatch),
3080 Imm.getValueType(), true);
3083 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
3087 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
3088 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
3089 // These are space-optimized forms of OPC_EmitMergeInputChains.
3090 assert(!InputChain.getNode() &&
3091 "EmitMergeInputChains should be the first chain producing node");
3092 assert(ChainNodesMatched.empty() &&
3093 "Should only have one EmitMergeInputChains per match");
3095 // Read all of the chained nodes.
3096 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
3097 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3098 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3100 // FIXME: What if other value results of the node have uses not matched
3102 if (ChainNodesMatched.back() != NodeToMatch &&
3103 !RecordedNodes[RecNo].first.hasOneUse()) {
3104 ChainNodesMatched.clear();
3108 // Merge the input chains if they are not intra-pattern references.
3109 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3111 if (!InputChain.getNode())
3112 break; // Failed to merge.
3116 case OPC_EmitMergeInputChains: {
3117 assert(!InputChain.getNode() &&
3118 "EmitMergeInputChains should be the first chain producing node");
3119 // This node gets a list of nodes we matched in the input that have
3120 // chains. We want to token factor all of the input chains to these nodes
3121 // together. However, if any of the input chains is actually one of the
3122 // nodes matched in this pattern, then we have an intra-match reference.
3123 // Ignore these because the newly token factored chain should not refer to
3125 unsigned NumChains = MatcherTable[MatcherIndex++];
3126 assert(NumChains != 0 && "Can't TF zero chains");
3128 assert(ChainNodesMatched.empty() &&
3129 "Should only have one EmitMergeInputChains per match");
3131 // Read all of the chained nodes.
3132 for (unsigned i = 0; i != NumChains; ++i) {
3133 unsigned RecNo = MatcherTable[MatcherIndex++];
3134 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3135 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3137 // FIXME: What if other value results of the node have uses not matched
3139 if (ChainNodesMatched.back() != NodeToMatch &&
3140 !RecordedNodes[RecNo].first.hasOneUse()) {
3141 ChainNodesMatched.clear();
3146 // If the inner loop broke out, the match fails.
3147 if (ChainNodesMatched.empty())
3150 // Merge the input chains if they are not intra-pattern references.
3151 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3153 if (!InputChain.getNode())
3154 break; // Failed to merge.
3159 case OPC_EmitCopyToReg: {
3160 unsigned RecNo = MatcherTable[MatcherIndex++];
3161 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg");
3162 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
3164 if (!InputChain.getNode())
3165 InputChain = CurDAG->getEntryNode();
3167 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
3168 DestPhysReg, RecordedNodes[RecNo].first,
3171 InputGlue = InputChain.getValue(1);
3175 case OPC_EmitNodeXForm: {
3176 unsigned XFormNo = MatcherTable[MatcherIndex++];
3177 unsigned RecNo = MatcherTable[MatcherIndex++];
3178 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm");
3179 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
3180 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, nullptr));
3185 case OPC_MorphNodeTo: {
3186 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
3187 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
3188 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
3189 // Get the result VT list.
3190 unsigned NumVTs = MatcherTable[MatcherIndex++];
3191 SmallVector<EVT, 4> VTs;
3192 for (unsigned i = 0; i != NumVTs; ++i) {
3193 MVT::SimpleValueType VT =
3194 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3195 if (VT == MVT::iPTR)
3196 VT = TLI->getPointerTy(CurDAG->getDataLayout()).SimpleTy;
3200 if (EmitNodeInfo & OPFL_Chain)
3201 VTs.push_back(MVT::Other);
3202 if (EmitNodeInfo & OPFL_GlueOutput)
3203 VTs.push_back(MVT::Glue);
3205 // This is hot code, so optimize the two most common cases of 1 and 2
3208 if (VTs.size() == 1)
3209 VTList = CurDAG->getVTList(VTs[0]);
3210 else if (VTs.size() == 2)
3211 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
3213 VTList = CurDAG->getVTList(VTs);
3215 // Get the operand list.
3216 unsigned NumOps = MatcherTable[MatcherIndex++];
3217 SmallVector<SDValue, 8> Ops;
3218 for (unsigned i = 0; i != NumOps; ++i) {
3219 unsigned RecNo = MatcherTable[MatcherIndex++];
3221 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3223 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
3224 Ops.push_back(RecordedNodes[RecNo].first);
3227 // If there are variadic operands to add, handle them now.
3228 if (EmitNodeInfo & OPFL_VariadicInfo) {
3229 // Determine the start index to copy from.
3230 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
3231 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
3232 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
3233 "Invalid variadic node");
3234 // Copy all of the variadic operands, not including a potential glue
3236 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
3238 SDValue V = NodeToMatch->getOperand(i);
3239 if (V.getValueType() == MVT::Glue) break;
3244 // If this has chain/glue inputs, add them.
3245 if (EmitNodeInfo & OPFL_Chain)
3246 Ops.push_back(InputChain);
3247 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != nullptr)
3248 Ops.push_back(InputGlue);
3251 SDNode *Res = nullptr;
3252 if (Opcode != OPC_MorphNodeTo) {
3253 // If this is a normal EmitNode command, just create the new node and
3254 // add the results to the RecordedNodes list.
3255 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
3258 // Add all the non-glue/non-chain results to the RecordedNodes list.
3259 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
3260 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
3261 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
3265 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
3266 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops, EmitNodeInfo);
3268 // NodeToMatch was eliminated by CSE when the target changed the DAG.
3269 // We will visit the equivalent node later.
3270 DEBUG(dbgs() << "Node was eliminated by CSE\n");
3274 // If the node had chain/glue results, update our notion of the current
3276 if (EmitNodeInfo & OPFL_GlueOutput) {
3277 InputGlue = SDValue(Res, VTs.size()-1);
3278 if (EmitNodeInfo & OPFL_Chain)
3279 InputChain = SDValue(Res, VTs.size()-2);
3280 } else if (EmitNodeInfo & OPFL_Chain)
3281 InputChain = SDValue(Res, VTs.size()-1);
3283 // If the OPFL_MemRefs glue is set on this node, slap all of the
3284 // accumulated memrefs onto it.
3286 // FIXME: This is vastly incorrect for patterns with multiple outputs
3287 // instructions that access memory and for ComplexPatterns that match
3289 if (EmitNodeInfo & OPFL_MemRefs) {
3290 // Only attach load or store memory operands if the generated
3291 // instruction may load or store.
3292 const MCInstrDesc &MCID = TII->get(TargetOpc);
3293 bool mayLoad = MCID.mayLoad();
3294 bool mayStore = MCID.mayStore();
3296 unsigned NumMemRefs = 0;
3297 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3298 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3299 if ((*I)->isLoad()) {
3302 } else if ((*I)->isStore()) {
3310 MachineSDNode::mmo_iterator MemRefs =
3311 MF->allocateMemRefsArray(NumMemRefs);
3313 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
3314 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3315 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3316 if ((*I)->isLoad()) {
3319 } else if ((*I)->isStore()) {
3327 cast<MachineSDNode>(Res)
3328 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
3332 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
3333 << " node: "; Res->dump(CurDAG); dbgs() << "\n");
3335 // If this was a MorphNodeTo then we're completely done!
3336 if (Opcode == OPC_MorphNodeTo) {
3337 // Update chain and glue uses.
3338 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3339 InputGlue, GlueResultNodesMatched, true);
3346 case OPC_MarkGlueResults: {
3347 unsigned NumNodes = MatcherTable[MatcherIndex++];
3349 // Read and remember all the glue-result nodes.
3350 for (unsigned i = 0; i != NumNodes; ++i) {
3351 unsigned RecNo = MatcherTable[MatcherIndex++];
3353 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3355 assert(RecNo < RecordedNodes.size() && "Invalid MarkGlueResults");
3356 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3361 case OPC_CompleteMatch: {
3362 // The match has been completed, and any new nodes (if any) have been
3363 // created. Patch up references to the matched dag to use the newly
3365 unsigned NumResults = MatcherTable[MatcherIndex++];
3367 for (unsigned i = 0; i != NumResults; ++i) {
3368 unsigned ResSlot = MatcherTable[MatcherIndex++];
3370 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
3372 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch");
3373 SDValue Res = RecordedNodes[ResSlot].first;
3375 assert(i < NodeToMatch->getNumValues() &&
3376 NodeToMatch->getValueType(i) != MVT::Other &&
3377 NodeToMatch->getValueType(i) != MVT::Glue &&
3378 "Invalid number of results to complete!");
3379 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
3380 NodeToMatch->getValueType(i) == MVT::iPTR ||
3381 Res.getValueType() == MVT::iPTR ||
3382 NodeToMatch->getValueType(i).getSizeInBits() ==
3383 Res.getValueType().getSizeInBits()) &&
3384 "invalid replacement");
3385 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
3388 // If the root node defines glue, add it to the glue nodes to update list.
3389 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
3390 GlueResultNodesMatched.push_back(NodeToMatch);
3392 // Update chain and glue uses.
3393 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3394 InputGlue, GlueResultNodesMatched, false);
3396 assert(NodeToMatch->use_empty() &&
3397 "Didn't replace all uses of the node?");
3399 // FIXME: We just return here, which interacts correctly with SelectRoot
3400 // above. We should fix this to not return an SDNode* anymore.
3405 // If the code reached this point, then the match failed. See if there is
3406 // another child to try in the current 'Scope', otherwise pop it until we
3407 // find a case to check.
3408 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
3409 ++NumDAGIselRetries;
3411 if (MatchScopes.empty()) {
3412 CannotYetSelect(NodeToMatch);
3416 // Restore the interpreter state back to the point where the scope was
3418 MatchScope &LastScope = MatchScopes.back();
3419 RecordedNodes.resize(LastScope.NumRecordedNodes);
3421 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
3422 N = NodeStack.back();
3424 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
3425 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
3426 MatcherIndex = LastScope.FailIndex;
3428 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n");
3430 InputChain = LastScope.InputChain;
3431 InputGlue = LastScope.InputGlue;
3432 if (!LastScope.HasChainNodesMatched)
3433 ChainNodesMatched.clear();
3434 if (!LastScope.HasGlueResultNodesMatched)
3435 GlueResultNodesMatched.clear();
3437 // Check to see what the offset is at the new MatcherIndex. If it is zero
3438 // we have reached the end of this scope, otherwise we have another child
3439 // in the current scope to try.
3440 unsigned NumToSkip = MatcherTable[MatcherIndex++];
3441 if (NumToSkip & 128)
3442 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
3444 // If we have another child in this scope to match, update FailIndex and
3446 if (NumToSkip != 0) {
3447 LastScope.FailIndex = MatcherIndex+NumToSkip;
3451 // End of this scope, pop it and try the next child in the containing
3453 MatchScopes.pop_back();
3460 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
3462 raw_string_ostream Msg(msg);
3463 Msg << "Cannot select: ";
3465 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
3466 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
3467 N->getOpcode() != ISD::INTRINSIC_VOID) {
3468 N->printrFull(Msg, CurDAG);
3469 Msg << "\nIn function: " << MF->getName();
3471 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3473 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3474 if (iid < Intrinsic::num_intrinsics)
3475 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3476 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3477 Msg << "target intrinsic %" << TII->getName(iid);
3479 Msg << "unknown intrinsic #" << iid;
3481 report_fatal_error(Msg.str());
3484 char SelectionDAGISel::ID = 0;