1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "ScheduleDAGSDNodes.h"
17 #include "SelectionDAGBuilder.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/TargetTransformInfo.h"
23 #include "llvm/CodeGen/FastISel.h"
24 #include "llvm/CodeGen/FunctionLoweringInfo.h"
25 #include "llvm/CodeGen/GCMetadata.h"
26 #include "llvm/CodeGen/GCStrategy.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
33 #include "llvm/CodeGen/SchedulerRegistry.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/DebugInfo.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/InlineAsm.h"
39 #include "llvm/IR/Instructions.h"
40 #include "llvm/IR/IntrinsicInst.h"
41 #include "llvm/IR/Intrinsics.h"
42 #include "llvm/IR/LLVMContext.h"
43 #include "llvm/IR/Module.h"
44 #include "llvm/Support/Compiler.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/Timer.h"
48 #include "llvm/Support/raw_ostream.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetIntrinsicInfo.h"
51 #include "llvm/Target/TargetLibraryInfo.h"
52 #include "llvm/Target/TargetLowering.h"
53 #include "llvm/Target/TargetMachine.h"
54 #include "llvm/Target/TargetOptions.h"
55 #include "llvm/Target/TargetRegisterInfo.h"
56 #include "llvm/Target/TargetSubtargetInfo.h"
57 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
61 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
62 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
63 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
64 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
65 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
69 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
70 cl::desc("Enable extra verbose messages in the \"fast\" "
71 "instruction selector"));
73 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
74 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
75 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
76 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
77 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
78 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
79 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
81 // Standard binary operators...
82 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
83 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
84 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
85 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
86 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
87 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
88 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
89 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
90 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
91 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
92 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
93 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
95 // Logical operators...
96 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
97 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
98 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
100 // Memory instructions...
101 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
102 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
103 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
104 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
105 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
106 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
107 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
109 // Convert instructions...
110 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
111 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
112 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
113 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
114 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
115 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
116 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
117 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
118 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
119 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
120 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
121 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
123 // Other instructions...
124 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
125 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
126 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
127 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
128 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
129 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
130 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
131 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
132 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
133 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
134 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
135 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
136 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
137 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
138 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
142 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
143 cl::desc("Enable verbose messages in the \"fast\" "
144 "instruction selector"));
146 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
147 cl::desc("Enable abort calls when \"fast\" instruction selection "
148 "fails to lower an instruction"));
150 EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden,
151 cl::desc("Enable abort calls when \"fast\" instruction selection "
152 "fails to lower a formal argument"));
156 cl::desc("use Machine Branch Probability Info"),
157 cl::init(true), cl::Hidden);
161 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
162 cl::desc("Pop up a window to show dags before the first "
163 "dag combine pass"));
165 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
166 cl::desc("Pop up a window to show dags before legalize types"));
168 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
169 cl::desc("Pop up a window to show dags before legalize"));
171 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
172 cl::desc("Pop up a window to show dags before the second "
173 "dag combine pass"));
175 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
176 cl::desc("Pop up a window to show dags before the post legalize types"
177 " dag combine pass"));
179 ViewISelDAGs("view-isel-dags", cl::Hidden,
180 cl::desc("Pop up a window to show isel dags as they are selected"));
182 ViewSchedDAGs("view-sched-dags", cl::Hidden,
183 cl::desc("Pop up a window to show sched dags as they are processed"));
185 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
186 cl::desc("Pop up a window to show SUnit dags after they are processed"));
188 static const bool ViewDAGCombine1 = false,
189 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
190 ViewDAGCombine2 = false,
191 ViewDAGCombineLT = false,
192 ViewISelDAGs = false, ViewSchedDAGs = false,
193 ViewSUnitDAGs = false;
196 //===---------------------------------------------------------------------===//
198 /// RegisterScheduler class - Track the registration of instruction schedulers.
200 //===---------------------------------------------------------------------===//
201 MachinePassRegistry RegisterScheduler::Registry;
203 //===---------------------------------------------------------------------===//
205 /// ISHeuristic command line option for instruction schedulers.
207 //===---------------------------------------------------------------------===//
208 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
209 RegisterPassParser<RegisterScheduler> >
210 ISHeuristic("pre-RA-sched",
211 cl::init(&createDefaultScheduler),
212 cl::desc("Instruction schedulers available (before register"
215 static RegisterScheduler
216 defaultListDAGScheduler("default", "Best scheduler for the target",
217 createDefaultScheduler);
220 //===--------------------------------------------------------------------===//
221 /// createDefaultScheduler - This creates an instruction scheduler appropriate
223 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
224 CodeGenOpt::Level OptLevel) {
225 const TargetLowering &TLI = IS->getTargetLowering();
226 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>();
228 if (OptLevel == CodeGenOpt::None || ST.enableMachineScheduler() ||
229 TLI.getSchedulingPreference() == Sched::Source)
230 return createSourceListDAGScheduler(IS, OptLevel);
231 if (TLI.getSchedulingPreference() == Sched::RegPressure)
232 return createBURRListDAGScheduler(IS, OptLevel);
233 if (TLI.getSchedulingPreference() == Sched::Hybrid)
234 return createHybridListDAGScheduler(IS, OptLevel);
235 if (TLI.getSchedulingPreference() == Sched::VLIW)
236 return createVLIWDAGScheduler(IS, OptLevel);
237 assert(TLI.getSchedulingPreference() == Sched::ILP &&
238 "Unknown sched type!");
239 return createILPListDAGScheduler(IS, OptLevel);
243 // EmitInstrWithCustomInserter - This method should be implemented by targets
244 // that mark instructions with the 'usesCustomInserter' flag. These
245 // instructions are special in various ways, which require special support to
246 // insert. The specified MachineInstr is created but not inserted into any
247 // basic blocks, and this method is called to expand it into a sequence of
248 // instructions, potentially also creating new basic blocks and control flow.
249 // When new basic blocks are inserted and the edges from MBB to its successors
250 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
253 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
254 MachineBasicBlock *MBB) const {
256 dbgs() << "If a target marks an instruction with "
257 "'usesCustomInserter', it must implement "
258 "TargetLowering::EmitInstrWithCustomInserter!";
263 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
264 SDNode *Node) const {
265 assert(!MI->hasPostISelHook() &&
266 "If a target marks an instruction with 'hasPostISelHook', "
267 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
270 //===----------------------------------------------------------------------===//
271 // SelectionDAGISel code
272 //===----------------------------------------------------------------------===//
274 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm,
275 CodeGenOpt::Level OL) :
276 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
277 FuncInfo(new FunctionLoweringInfo(TLI)),
278 CurDAG(new SelectionDAG(tm, OL)),
279 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
283 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
284 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
285 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
286 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry());
289 SelectionDAGISel::~SelectionDAGISel() {
295 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
296 AU.addRequired<AliasAnalysis>();
297 AU.addPreserved<AliasAnalysis>();
298 AU.addRequired<GCModuleInfo>();
299 AU.addPreserved<GCModuleInfo>();
300 AU.addRequired<TargetLibraryInfo>();
301 if (UseMBPI && OptLevel != CodeGenOpt::None)
302 AU.addRequired<BranchProbabilityInfo>();
303 MachineFunctionPass::getAnalysisUsage(AU);
306 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
307 /// may trap on it. In this case we have to split the edge so that the path
308 /// through the predecessor block that doesn't go to the phi block doesn't
309 /// execute the possibly trapping instruction.
311 /// This is required for correctness, so it must be done at -O0.
313 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
314 // Loop for blocks with phi nodes.
315 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
316 PHINode *PN = dyn_cast<PHINode>(BB->begin());
317 if (PN == 0) continue;
320 // For each block with a PHI node, check to see if any of the input values
321 // are potentially trapping constant expressions. Constant expressions are
322 // the only potentially trapping value that can occur as the argument to a
324 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
325 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
326 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
327 if (CE == 0 || !CE->canTrap()) continue;
329 // The only case we have to worry about is when the edge is critical.
330 // Since this block has a PHI Node, we assume it has multiple input
331 // edges: check to see if the pred has multiple successors.
332 BasicBlock *Pred = PN->getIncomingBlock(i);
333 if (Pred->getTerminator()->getNumSuccessors() == 1)
336 // Okay, we have to split this edge.
337 SplitCriticalEdge(Pred->getTerminator(),
338 GetSuccessorNumber(Pred, BB), SDISel, true);
344 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
345 // Do some sanity-checking on the command-line options.
346 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
347 "-fast-isel-verbose requires -fast-isel");
348 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
349 "-fast-isel-abort requires -fast-isel");
351 const Function &Fn = *mf.getFunction();
352 const TargetInstrInfo &TII = *TM.getInstrInfo();
353 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
356 RegInfo = &MF->getRegInfo();
357 AA = &getAnalysis<AliasAnalysis>();
358 LibInfo = &getAnalysis<TargetLibraryInfo>();
359 TTI = getAnalysisIfAvailable<TargetTransformInfo>();
360 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
362 TargetSubtargetInfo &ST =
363 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>());
364 ST.resetSubtargetFeatures(MF);
366 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
368 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
370 CurDAG->init(*MF, TTI);
371 FuncInfo->set(Fn, *MF);
373 if (UseMBPI && OptLevel != CodeGenOpt::None)
374 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
378 SDB->init(GFI, *AA, LibInfo);
380 MF->setHasMSInlineAsm(false);
381 SelectAllBasicBlocks(Fn);
383 // If the first basic block in the function has live ins that need to be
384 // copied into vregs, emit the copies into the top of the block before
385 // emitting the code for the block.
386 MachineBasicBlock *EntryMBB = MF->begin();
387 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
389 DenseMap<unsigned, unsigned> LiveInMap;
390 if (!FuncInfo->ArgDbgValues.empty())
391 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
392 E = RegInfo->livein_end(); LI != E; ++LI)
394 LiveInMap.insert(std::make_pair(LI->first, LI->second));
396 // Insert DBG_VALUE instructions for function arguments to the entry block.
397 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
398 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
399 unsigned Reg = MI->getOperand(0).getReg();
400 if (TargetRegisterInfo::isPhysicalRegister(Reg))
401 EntryMBB->insert(EntryMBB->begin(), MI);
403 MachineInstr *Def = RegInfo->getVRegDef(Reg);
404 MachineBasicBlock::iterator InsertPos = Def;
405 // FIXME: VR def may not be in entry block.
406 Def->getParent()->insert(llvm::next(InsertPos), MI);
409 // If Reg is live-in then update debug info to track its copy in a vreg.
410 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
411 if (LDI != LiveInMap.end()) {
412 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
413 MachineBasicBlock::iterator InsertPos = Def;
414 const MDNode *Variable =
415 MI->getOperand(MI->getNumOperands()-1).getMetadata();
416 unsigned Offset = MI->getOperand(1).getImm();
417 // Def is never a terminator here, so it is ok to increment InsertPos.
418 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
419 TII.get(TargetOpcode::DBG_VALUE))
420 .addReg(LDI->second, RegState::Debug)
421 .addImm(Offset).addMetadata(Variable);
423 // If this vreg is directly copied into an exported register then
424 // that COPY instructions also need DBG_VALUE, if it is the only
425 // user of LDI->second.
426 MachineInstr *CopyUseMI = NULL;
427 for (MachineRegisterInfo::use_iterator
428 UI = RegInfo->use_begin(LDI->second);
429 MachineInstr *UseMI = UI.skipInstruction();) {
430 if (UseMI->isDebugValue()) continue;
431 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
432 CopyUseMI = UseMI; continue;
434 // Otherwise this is another use or second copy use.
435 CopyUseMI = NULL; break;
438 MachineInstr *NewMI =
439 BuildMI(*MF, CopyUseMI->getDebugLoc(),
440 TII.get(TargetOpcode::DBG_VALUE))
441 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
442 .addImm(Offset).addMetadata(Variable);
443 MachineBasicBlock::iterator Pos = CopyUseMI;
444 EntryMBB->insertAfter(Pos, NewMI);
449 // Determine if there are any calls in this machine function.
450 MachineFrameInfo *MFI = MF->getFrameInfo();
451 for (MachineFunction::const_iterator I = MF->begin(), E = MF->end(); I != E;
454 if (MFI->hasCalls() && MF->hasMSInlineAsm())
457 const MachineBasicBlock *MBB = I;
458 for (MachineBasicBlock::const_iterator II = MBB->begin(), IE = MBB->end();
460 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
461 if ((MCID.isCall() && !MCID.isReturn()) ||
462 II->isStackAligningInlineAsm()) {
463 MFI->setHasCalls(true);
465 if (II->isMSInlineAsm()) {
466 MF->setHasMSInlineAsm(true);
471 // Determine if there is a call to setjmp in the machine function.
472 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
474 // Replace forward-declared registers with the registers containing
475 // the desired value.
476 MachineRegisterInfo &MRI = MF->getRegInfo();
477 for (DenseMap<unsigned, unsigned>::iterator
478 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
480 unsigned From = I->first;
481 unsigned To = I->second;
482 // If To is also scheduled to be replaced, find what its ultimate
485 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
490 MRI.replaceRegWith(From, To);
493 // Freeze the set of reserved registers now that MachineFrameInfo has been
494 // set up. All the information required by getReservedRegs() should be
496 MRI.freezeReservedRegs(*MF);
498 // Release function-specific state. SDB and CurDAG are already cleared
505 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
506 BasicBlock::const_iterator End,
508 // Lower all of the non-terminator instructions. If a call is emitted
509 // as a tail call, cease emitting nodes for this block. Terminators
510 // are handled below.
511 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
514 // Make sure the root of the DAG is up-to-date.
515 CurDAG->setRoot(SDB->getControlRoot());
516 HadTailCall = SDB->HasTailCall;
519 // Final step, emit the lowered DAG as machine code.
523 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
524 SmallPtrSet<SDNode*, 128> VisitedNodes;
525 SmallVector<SDNode*, 128> Worklist;
527 Worklist.push_back(CurDAG->getRoot().getNode());
533 SDNode *N = Worklist.pop_back_val();
535 // If we've already seen this node, ignore it.
536 if (!VisitedNodes.insert(N))
539 // Otherwise, add all chain operands to the worklist.
540 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
541 if (N->getOperand(i).getValueType() == MVT::Other)
542 Worklist.push_back(N->getOperand(i).getNode());
544 // If this is a CopyToReg with a vreg dest, process it.
545 if (N->getOpcode() != ISD::CopyToReg)
548 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
549 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
552 // Ignore non-scalar or non-integer values.
553 SDValue Src = N->getOperand(2);
554 EVT SrcVT = Src.getValueType();
555 if (!SrcVT.isInteger() || SrcVT.isVector())
558 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
559 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne);
560 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
561 } while (!Worklist.empty());
564 void SelectionDAGISel::CodeGenAndEmitDAG() {
565 std::string GroupName;
566 if (TimePassesIsEnabled)
567 GroupName = "Instruction Selection and Scheduling";
568 std::string BlockName;
569 int BlockNumber = -1;
572 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
573 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
577 BlockNumber = FuncInfo->MBB->getNumber();
578 BlockName = MF->getName().str() + ":" +
579 FuncInfo->MBB->getBasicBlock()->getName().str();
581 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
582 << " '" << BlockName << "'\n"; CurDAG->dump());
584 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
586 // Run the DAG combiner in pre-legalize mode.
588 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
589 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
592 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
593 << " '" << BlockName << "'\n"; CurDAG->dump());
595 // Second step, hack on the DAG until it only uses operations and types that
596 // the target supports.
597 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
602 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
603 Changed = CurDAG->LegalizeTypes();
606 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
607 << " '" << BlockName << "'\n"; CurDAG->dump());
610 if (ViewDAGCombineLT)
611 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
613 // Run the DAG combiner in post-type-legalize mode.
615 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
616 TimePassesIsEnabled);
617 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
620 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
621 << " '" << BlockName << "'\n"; CurDAG->dump());
625 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
626 Changed = CurDAG->LegalizeVectors();
631 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
632 CurDAG->LegalizeTypes();
635 if (ViewDAGCombineLT)
636 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
638 // Run the DAG combiner in post-type-legalize mode.
640 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
641 TimePassesIsEnabled);
642 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
645 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
646 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
649 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
652 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
656 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
657 << " '" << BlockName << "'\n"; CurDAG->dump());
659 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
661 // Run the DAG combiner in post-legalize mode.
663 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
664 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
667 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
668 << " '" << BlockName << "'\n"; CurDAG->dump());
670 if (OptLevel != CodeGenOpt::None)
671 ComputeLiveOutVRegInfo();
673 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
675 // Third, instruction select all of the operations to machine code, adding the
676 // code to the MachineBasicBlock.
678 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
679 DoInstructionSelection();
682 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
683 << " '" << BlockName << "'\n"; CurDAG->dump());
685 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
687 // Schedule machine code.
688 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
690 NamedRegionTimer T("Instruction Scheduling", GroupName,
691 TimePassesIsEnabled);
692 Scheduler->Run(CurDAG, FuncInfo->MBB);
695 if (ViewSUnitDAGs) Scheduler->viewGraph();
697 // Emit machine code to BB. This can change 'BB' to the last block being
699 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
701 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
703 // FuncInfo->InsertPt is passed by reference and set to the end of the
704 // scheduled instructions.
705 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
708 // If the block was split, make sure we update any references that are used to
709 // update PHI nodes later on.
710 if (FirstMBB != LastMBB)
711 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
713 // Free the scheduler state.
715 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
716 TimePassesIsEnabled);
720 // Free the SelectionDAG state, now that we're finished with it.
725 /// ISelUpdater - helper class to handle updates of the instruction selection
727 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
728 SelectionDAG::allnodes_iterator &ISelPosition;
730 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
731 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
733 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
734 /// deleted is the current ISelPosition node, update ISelPosition.
736 virtual void NodeDeleted(SDNode *N, SDNode *E) {
737 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
741 } // end anonymous namespace
743 void SelectionDAGISel::DoInstructionSelection() {
744 DEBUG(errs() << "===== Instruction selection begins: BB#"
745 << FuncInfo->MBB->getNumber()
746 << " '" << FuncInfo->MBB->getName() << "'\n");
750 // Select target instructions for the DAG.
752 // Number all nodes with a topological order and set DAGSize.
753 DAGSize = CurDAG->AssignTopologicalOrder();
755 // Create a dummy node (which is not added to allnodes), that adds
756 // a reference to the root node, preventing it from being deleted,
757 // and tracking any changes of the root.
758 HandleSDNode Dummy(CurDAG->getRoot());
759 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
762 // Make sure that ISelPosition gets properly updated when nodes are deleted
763 // in calls made from this function.
764 ISelUpdater ISU(*CurDAG, ISelPosition);
766 // The AllNodes list is now topological-sorted. Visit the
767 // nodes by starting at the end of the list (the root of the
768 // graph) and preceding back toward the beginning (the entry
770 while (ISelPosition != CurDAG->allnodes_begin()) {
771 SDNode *Node = --ISelPosition;
772 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
773 // but there are currently some corner cases that it misses. Also, this
774 // makes it theoretically possible to disable the DAGCombiner.
775 if (Node->use_empty())
778 SDNode *ResNode = Select(Node);
780 // FIXME: This is pretty gross. 'Select' should be changed to not return
781 // anything at all and this code should be nuked with a tactical strike.
783 // If node should not be replaced, continue with the next one.
784 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
788 ReplaceUses(Node, ResNode);
790 // If after the replacement this node is not used any more,
791 // remove this dead node.
792 if (Node->use_empty()) // Don't delete EntryToken, etc.
793 CurDAG->RemoveDeadNode(Node);
796 CurDAG->setRoot(Dummy.getValue());
799 DEBUG(errs() << "===== Instruction selection ends:\n");
801 PostprocessISelDAG();
804 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
805 /// do other setup for EH landing-pad blocks.
806 void SelectionDAGISel::PrepareEHLandingPad() {
807 MachineBasicBlock *MBB = FuncInfo->MBB;
809 // Add a label to mark the beginning of the landing pad. Deletion of the
810 // landing pad can thus be detected via the MachineModuleInfo.
811 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
813 // Assign the call site to the landing pad's begin label.
814 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
816 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
817 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
820 // Mark exception register as live in.
821 unsigned Reg = TLI.getExceptionPointerRegister();
822 if (Reg) MBB->addLiveIn(Reg);
824 // Mark exception selector register as live in.
825 Reg = TLI.getExceptionSelectorRegister();
826 if (Reg) MBB->addLiveIn(Reg);
829 /// TryToFoldFastISelLoad - We're checking to see if we can fold the specified
830 /// load into the specified FoldInst. Note that we could have a sequence where
831 /// multiple LLVM IR instructions are folded into the same machineinstr. For
832 /// example we could have:
833 /// A: x = load i32 *P
834 /// B: y = icmp A, 42
837 /// In this scenario, LI is "A", and FoldInst is "C". We know about "B" (and
838 /// any other folded instructions) because it is between A and C.
840 /// If we succeed in folding the load into the operation, return true.
842 bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI,
843 const Instruction *FoldInst,
845 // We know that the load has a single use, but don't know what it is. If it
846 // isn't one of the folded instructions, then we can't succeed here. Handle
847 // this by scanning the single-use users of the load until we get to FoldInst.
848 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
850 const Instruction *TheUser = LI->use_back();
851 while (TheUser != FoldInst && // Scan up until we find FoldInst.
852 // Stay in the right block.
853 TheUser->getParent() == FoldInst->getParent() &&
854 --MaxUsers) { // Don't scan too far.
855 // If there are multiple or no uses of this instruction, then bail out.
856 if (!TheUser->hasOneUse())
859 TheUser = TheUser->use_back();
862 // If we didn't find the fold instruction, then we failed to collapse the
864 if (TheUser != FoldInst)
867 // Don't try to fold volatile loads. Target has to deal with alignment
869 if (LI->isVolatile()) return false;
871 // Figure out which vreg this is going into. If there is no assigned vreg yet
872 // then there actually was no reference to it. Perhaps the load is referenced
873 // by a dead instruction.
874 unsigned LoadReg = FastIS->getRegForValue(LI);
878 // Check to see what the uses of this vreg are. If it has no uses, or more
879 // than one use (at the machine instr level) then we can't fold it.
880 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg);
881 if (RI == RegInfo->reg_end())
884 // See if there is exactly one use of the vreg. If there are multiple uses,
885 // then the instruction got lowered to multiple machine instructions or the
886 // use of the loaded value ended up being multiple operands of the result, in
887 // either case, we can't fold this.
888 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI;
889 if (PostRI != RegInfo->reg_end())
892 assert(RI.getOperand().isUse() &&
893 "The only use of the vreg must be a use, we haven't emitted the def!");
895 MachineInstr *User = &*RI;
897 // Set the insertion point properly. Folding the load can cause generation of
898 // other random instructions (like sign extends) for addressing modes, make
899 // sure they get inserted in a logical place before the new instruction.
900 FuncInfo->InsertPt = User;
901 FuncInfo->MBB = User->getParent();
903 // Ask the target to try folding the load.
904 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI);
907 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
908 /// side-effect free and is either dead or folded into a generated instruction.
909 /// Return false if it needs to be emitted.
910 static bool isFoldedOrDeadInstruction(const Instruction *I,
911 FunctionLoweringInfo *FuncInfo) {
912 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
913 !isa<TerminatorInst>(I) && // Terminators aren't folded.
914 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
915 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
916 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
920 // Collect per Instruction statistics for fast-isel misses. Only those
921 // instructions that cause the bail are accounted for. It does not account for
922 // instructions higher in the block. Thus, summing the per instructions stats
923 // will not add up to what is reported by NumFastIselFailures.
924 static void collectFailStats(const Instruction *I) {
925 switch (I->getOpcode()) {
926 default: assert (0 && "<Invalid operator> ");
929 case Instruction::Ret: NumFastIselFailRet++; return;
930 case Instruction::Br: NumFastIselFailBr++; return;
931 case Instruction::Switch: NumFastIselFailSwitch++; return;
932 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
933 case Instruction::Invoke: NumFastIselFailInvoke++; return;
934 case Instruction::Resume: NumFastIselFailResume++; return;
935 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
937 // Standard binary operators...
938 case Instruction::Add: NumFastIselFailAdd++; return;
939 case Instruction::FAdd: NumFastIselFailFAdd++; return;
940 case Instruction::Sub: NumFastIselFailSub++; return;
941 case Instruction::FSub: NumFastIselFailFSub++; return;
942 case Instruction::Mul: NumFastIselFailMul++; return;
943 case Instruction::FMul: NumFastIselFailFMul++; return;
944 case Instruction::UDiv: NumFastIselFailUDiv++; return;
945 case Instruction::SDiv: NumFastIselFailSDiv++; return;
946 case Instruction::FDiv: NumFastIselFailFDiv++; return;
947 case Instruction::URem: NumFastIselFailURem++; return;
948 case Instruction::SRem: NumFastIselFailSRem++; return;
949 case Instruction::FRem: NumFastIselFailFRem++; return;
951 // Logical operators...
952 case Instruction::And: NumFastIselFailAnd++; return;
953 case Instruction::Or: NumFastIselFailOr++; return;
954 case Instruction::Xor: NumFastIselFailXor++; return;
956 // Memory instructions...
957 case Instruction::Alloca: NumFastIselFailAlloca++; return;
958 case Instruction::Load: NumFastIselFailLoad++; return;
959 case Instruction::Store: NumFastIselFailStore++; return;
960 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
961 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
962 case Instruction::Fence: NumFastIselFailFence++; return;
963 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
965 // Convert instructions...
966 case Instruction::Trunc: NumFastIselFailTrunc++; return;
967 case Instruction::ZExt: NumFastIselFailZExt++; return;
968 case Instruction::SExt: NumFastIselFailSExt++; return;
969 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
970 case Instruction::FPExt: NumFastIselFailFPExt++; return;
971 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
972 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
973 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
974 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
975 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
976 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
977 case Instruction::BitCast: NumFastIselFailBitCast++; return;
979 // Other instructions...
980 case Instruction::ICmp: NumFastIselFailICmp++; return;
981 case Instruction::FCmp: NumFastIselFailFCmp++; return;
982 case Instruction::PHI: NumFastIselFailPHI++; return;
983 case Instruction::Select: NumFastIselFailSelect++; return;
984 case Instruction::Call: NumFastIselFailCall++; return;
985 case Instruction::Shl: NumFastIselFailShl++; return;
986 case Instruction::LShr: NumFastIselFailLShr++; return;
987 case Instruction::AShr: NumFastIselFailAShr++; return;
988 case Instruction::VAArg: NumFastIselFailVAArg++; return;
989 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
990 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
991 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
992 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
993 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
994 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
999 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
1000 // Initialize the Fast-ISel state, if needed.
1001 FastISel *FastIS = 0;
1002 if (TM.Options.EnableFastISel)
1003 FastIS = TLI.createFastISel(*FuncInfo, LibInfo);
1005 // Iterate over all basic blocks in the function.
1006 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
1007 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
1008 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
1009 const BasicBlock *LLVMBB = *I;
1011 if (OptLevel != CodeGenOpt::None) {
1012 bool AllPredsVisited = true;
1013 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1015 if (!FuncInfo->VisitedBBs.count(*PI)) {
1016 AllPredsVisited = false;
1021 if (AllPredsVisited) {
1022 for (BasicBlock::const_iterator I = LLVMBB->begin();
1023 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1024 FuncInfo->ComputePHILiveOutRegInfo(PN);
1026 for (BasicBlock::const_iterator I = LLVMBB->begin();
1027 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1028 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1031 FuncInfo->VisitedBBs.insert(LLVMBB);
1034 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1035 BasicBlock::const_iterator const End = LLVMBB->end();
1036 BasicBlock::const_iterator BI = End;
1038 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1039 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1041 // Setup an EH landing-pad block.
1042 if (FuncInfo->MBB->isLandingPad())
1043 PrepareEHLandingPad();
1045 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1047 FastIS->startNewBlock();
1049 // Emit code for any incoming arguments. This must happen before
1050 // beginning FastISel on the entry block.
1051 if (LLVMBB == &Fn.getEntryBlock()) {
1052 // Lower any arguments needed in this block if this is the entry block.
1053 if (!FastIS->LowerArguments()) {
1054 // Fast isel failed to lower these arguments
1055 if (EnableFastISelAbortArgs)
1056 llvm_unreachable("FastISel didn't lower all arguments");
1058 // Use SelectionDAG argument lowering
1060 CurDAG->setRoot(SDB->getControlRoot());
1062 CodeGenAndEmitDAG();
1065 // If we inserted any instructions at the beginning, make a note of
1066 // where they are, so we can be sure to emit subsequent instructions
1068 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1069 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
1071 FastIS->setLastLocalValue(0);
1074 unsigned NumFastIselRemaining = std::distance(Begin, End);
1075 // Do FastISel on as many instructions as possible.
1076 for (; BI != Begin; --BI) {
1077 const Instruction *Inst = llvm::prior(BI);
1079 // If we no longer require this instruction, skip it.
1080 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1081 --NumFastIselRemaining;
1085 // Bottom-up: reset the insert pos at the top, after any local-value
1087 FastIS->recomputeInsertPt();
1089 // Try to select the instruction with FastISel.
1090 if (FastIS->SelectInstruction(Inst)) {
1091 --NumFastIselRemaining;
1092 ++NumFastIselSuccess;
1093 // If fast isel succeeded, skip over all the folded instructions, and
1094 // then see if there is a load right before the selected instructions.
1095 // Try to fold the load if so.
1096 const Instruction *BeforeInst = Inst;
1097 while (BeforeInst != Begin) {
1098 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst));
1099 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1102 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1103 BeforeInst->hasOneUse() &&
1104 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS)) {
1105 // If we succeeded, don't re-select the load.
1106 BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
1107 --NumFastIselRemaining;
1108 ++NumFastIselSuccess;
1114 if (EnableFastISelVerbose2)
1115 collectFailStats(Inst);
1118 // Then handle certain instructions as single-LLVM-Instruction blocks.
1119 if (isa<CallInst>(Inst)) {
1121 if (EnableFastISelVerbose || EnableFastISelAbort) {
1122 dbgs() << "FastISel missed call: ";
1126 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1127 unsigned &R = FuncInfo->ValueMap[Inst];
1129 R = FuncInfo->CreateRegs(Inst->getType());
1132 bool HadTailCall = false;
1133 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1134 SelectBasicBlock(Inst, BI, HadTailCall);
1136 // If the call was emitted as a tail call, we're done with the block.
1137 // We also need to delete any previously emitted instructions.
1139 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1144 // Recompute NumFastIselRemaining as Selection DAG instruction
1145 // selection may have handled the call, input args, etc.
1146 unsigned RemainingNow = std::distance(Begin, BI);
1147 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1148 NumFastIselRemaining = RemainingNow;
1152 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
1153 // Don't abort, and use a different message for terminator misses.
1154 NumFastIselFailures += NumFastIselRemaining;
1155 if (EnableFastISelVerbose || EnableFastISelAbort) {
1156 dbgs() << "FastISel missed terminator: ";
1160 NumFastIselFailures += NumFastIselRemaining;
1161 if (EnableFastISelVerbose || EnableFastISelAbort) {
1162 dbgs() << "FastISel miss: ";
1165 if (EnableFastISelAbort)
1166 // The "fast" selector couldn't handle something and bailed.
1167 // For the purpose of debugging, just abort.
1168 llvm_unreachable("FastISel didn't select the entire block");
1173 FastIS->recomputeInsertPt();
1175 // Lower any arguments needed in this block if this is the entry block.
1176 if (LLVMBB == &Fn.getEntryBlock())
1183 ++NumFastIselBlocks;
1186 // Run SelectionDAG instruction selection on the remainder of the block
1187 // not handled by FastISel. If FastISel is not run, this is the entire
1190 SelectBasicBlock(Begin, BI, HadTailCall);
1194 FuncInfo->PHINodesToUpdate.clear();
1198 SDB->clearDanglingDebugInfo();
1202 SelectionDAGISel::FinishBasicBlock() {
1204 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1205 << FuncInfo->PHINodesToUpdate.size() << "\n";
1206 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1207 dbgs() << "Node " << i << " : ("
1208 << FuncInfo->PHINodesToUpdate[i].first
1209 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1211 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1212 // PHI nodes in successors.
1213 if (SDB->SwitchCases.empty() &&
1214 SDB->JTCases.empty() &&
1215 SDB->BitTestCases.empty()) {
1216 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1217 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1218 assert(PHI->isPHI() &&
1219 "This is not a machine PHI node that we are updating!");
1220 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1222 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1227 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1228 // Lower header first, if it wasn't already lowered
1229 if (!SDB->BitTestCases[i].Emitted) {
1230 // Set the current basic block to the mbb we wish to insert the code into
1231 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1232 FuncInfo->InsertPt = FuncInfo->MBB->end();
1234 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1235 CurDAG->setRoot(SDB->getRoot());
1237 CodeGenAndEmitDAG();
1240 uint32_t UnhandledWeight = 0;
1241 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1242 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1244 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1245 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1246 // Set the current basic block to the mbb we wish to insert the code into
1247 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1248 FuncInfo->InsertPt = FuncInfo->MBB->end();
1251 SDB->visitBitTestCase(SDB->BitTestCases[i],
1252 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1254 SDB->BitTestCases[i].Reg,
1255 SDB->BitTestCases[i].Cases[j],
1258 SDB->visitBitTestCase(SDB->BitTestCases[i],
1259 SDB->BitTestCases[i].Default,
1261 SDB->BitTestCases[i].Reg,
1262 SDB->BitTestCases[i].Cases[j],
1266 CurDAG->setRoot(SDB->getRoot());
1268 CodeGenAndEmitDAG();
1272 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1274 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1275 MachineBasicBlock *PHIBB = PHI->getParent();
1276 assert(PHI->isPHI() &&
1277 "This is not a machine PHI node that we are updating!");
1278 // This is "default" BB. We have two jumps to it. From "header" BB and
1279 // from last "case" BB.
1280 if (PHIBB == SDB->BitTestCases[i].Default)
1281 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1282 .addMBB(SDB->BitTestCases[i].Parent)
1283 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1284 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1285 // One of "cases" BB.
1286 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1288 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1289 if (cBB->isSuccessor(PHIBB))
1290 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1294 SDB->BitTestCases.clear();
1296 // If the JumpTable record is filled in, then we need to emit a jump table.
1297 // Updating the PHI nodes is tricky in this case, since we need to determine
1298 // whether the PHI is a successor of the range check MBB or the jump table MBB
1299 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1300 // Lower header first, if it wasn't already lowered
1301 if (!SDB->JTCases[i].first.Emitted) {
1302 // Set the current basic block to the mbb we wish to insert the code into
1303 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1304 FuncInfo->InsertPt = FuncInfo->MBB->end();
1306 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1308 CurDAG->setRoot(SDB->getRoot());
1310 CodeGenAndEmitDAG();
1313 // Set the current basic block to the mbb we wish to insert the code into
1314 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1315 FuncInfo->InsertPt = FuncInfo->MBB->end();
1317 SDB->visitJumpTable(SDB->JTCases[i].second);
1318 CurDAG->setRoot(SDB->getRoot());
1320 CodeGenAndEmitDAG();
1323 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1325 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1326 MachineBasicBlock *PHIBB = PHI->getParent();
1327 assert(PHI->isPHI() &&
1328 "This is not a machine PHI node that we are updating!");
1329 // "default" BB. We can go there only from header BB.
1330 if (PHIBB == SDB->JTCases[i].second.Default)
1331 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1332 .addMBB(SDB->JTCases[i].first.HeaderBB);
1333 // JT BB. Just iterate over successors here
1334 if (FuncInfo->MBB->isSuccessor(PHIBB))
1335 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1338 SDB->JTCases.clear();
1340 // If the switch block involved a branch to one of the actual successors, we
1341 // need to update PHI nodes in that block.
1342 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1343 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1344 assert(PHI->isPHI() &&
1345 "This is not a machine PHI node that we are updating!");
1346 if (FuncInfo->MBB->isSuccessor(PHI->getParent()))
1347 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1350 // If we generated any switch lowering information, build and codegen any
1351 // additional DAGs necessary.
1352 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1353 // Set the current basic block to the mbb we wish to insert the code into
1354 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1355 FuncInfo->InsertPt = FuncInfo->MBB->end();
1357 // Determine the unique successors.
1358 SmallVector<MachineBasicBlock *, 2> Succs;
1359 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1360 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1361 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1363 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1364 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1365 CurDAG->setRoot(SDB->getRoot());
1367 CodeGenAndEmitDAG();
1369 // Remember the last block, now that any splitting is done, for use in
1370 // populating PHI nodes in successors.
1371 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1373 // Handle any PHI nodes in successors of this chunk, as if we were coming
1374 // from the original BB before switch expansion. Note that PHI nodes can
1375 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1376 // handle them the right number of times.
1377 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1378 FuncInfo->MBB = Succs[i];
1379 FuncInfo->InsertPt = FuncInfo->MBB->end();
1380 // FuncInfo->MBB may have been removed from the CFG if a branch was
1382 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1383 for (MachineBasicBlock::iterator
1384 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1385 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1386 MachineInstrBuilder PHI(*MF, MBBI);
1387 // This value for this PHI node is recorded in PHINodesToUpdate.
1388 for (unsigned pn = 0; ; ++pn) {
1389 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1390 "Didn't find PHI entry!");
1391 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1392 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1400 SDB->SwitchCases.clear();
1404 /// Create the scheduler. If a specific scheduler was specified
1405 /// via the SchedulerRegistry, use it, otherwise select the
1406 /// one preferred by the target.
1408 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1409 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1413 RegisterScheduler::setDefault(Ctor);
1416 return Ctor(this, OptLevel);
1419 //===----------------------------------------------------------------------===//
1420 // Helper functions used by the generated instruction selector.
1421 //===----------------------------------------------------------------------===//
1422 // Calls to these methods are generated by tblgen.
1424 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1425 /// the dag combiner simplified the 255, we still want to match. RHS is the
1426 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1427 /// specified in the .td file (e.g. 255).
1428 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1429 int64_t DesiredMaskS) const {
1430 const APInt &ActualMask = RHS->getAPIntValue();
1431 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1433 // If the actual mask exactly matches, success!
1434 if (ActualMask == DesiredMask)
1437 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1438 if (ActualMask.intersects(~DesiredMask))
1441 // Otherwise, the DAG Combiner may have proven that the value coming in is
1442 // either already zero or is not demanded. Check for known zero input bits.
1443 APInt NeededMask = DesiredMask & ~ActualMask;
1444 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1447 // TODO: check to see if missing bits are just not demanded.
1449 // Otherwise, this pattern doesn't match.
1453 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1454 /// the dag combiner simplified the 255, we still want to match. RHS is the
1455 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1456 /// specified in the .td file (e.g. 255).
1457 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1458 int64_t DesiredMaskS) const {
1459 const APInt &ActualMask = RHS->getAPIntValue();
1460 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1462 // If the actual mask exactly matches, success!
1463 if (ActualMask == DesiredMask)
1466 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1467 if (ActualMask.intersects(~DesiredMask))
1470 // Otherwise, the DAG Combiner may have proven that the value coming in is
1471 // either already zero or is not demanded. Check for known zero input bits.
1472 APInt NeededMask = DesiredMask & ~ActualMask;
1474 APInt KnownZero, KnownOne;
1475 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne);
1477 // If all the missing bits in the or are already known to be set, match!
1478 if ((NeededMask & KnownOne) == NeededMask)
1481 // TODO: check to see if missing bits are just not demanded.
1483 // Otherwise, this pattern doesn't match.
1488 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1489 /// by tblgen. Others should not call it.
1490 void SelectionDAGISel::
1491 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1492 std::vector<SDValue> InOps;
1493 std::swap(InOps, Ops);
1495 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1496 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1497 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1498 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1500 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1501 if (InOps[e-1].getValueType() == MVT::Glue)
1502 --e; // Don't process a glue operand if it is here.
1505 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1506 if (!InlineAsm::isMemKind(Flags)) {
1507 // Just skip over this operand, copying the operands verbatim.
1508 Ops.insert(Ops.end(), InOps.begin()+i,
1509 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1510 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1512 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1513 "Memory operand with multiple values?");
1514 // Otherwise, this is a memory operand. Ask the target to select it.
1515 std::vector<SDValue> SelOps;
1516 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1517 report_fatal_error("Could not match memory address. Inline asm"
1520 // Add this to the output node.
1522 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1523 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1524 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1529 // Add the glue input back if present.
1530 if (e != InOps.size())
1531 Ops.push_back(InOps.back());
1534 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1537 static SDNode *findGlueUse(SDNode *N) {
1538 unsigned FlagResNo = N->getNumValues()-1;
1539 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1540 SDUse &Use = I.getUse();
1541 if (Use.getResNo() == FlagResNo)
1542 return Use.getUser();
1547 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1548 /// This function recursively traverses up the operand chain, ignoring
1550 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1551 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1552 bool IgnoreChains) {
1553 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1554 // greater than all of its (recursive) operands. If we scan to a point where
1555 // 'use' is smaller than the node we're scanning for, then we know we will
1558 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1559 // happen because we scan down to newly selected nodes in the case of glue
1561 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1564 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1565 // won't fail if we scan it again.
1566 if (!Visited.insert(Use))
1569 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1570 // Ignore chain uses, they are validated by HandleMergeInputChains.
1571 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1574 SDNode *N = Use->getOperand(i).getNode();
1576 if (Use == ImmedUse || Use == Root)
1577 continue; // We are not looking for immediate use.
1582 // Traverse up the operand chain.
1583 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1589 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1590 /// operand node N of U during instruction selection that starts at Root.
1591 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1592 SDNode *Root) const {
1593 if (OptLevel == CodeGenOpt::None) return false;
1594 return N.hasOneUse();
1597 /// IsLegalToFold - Returns true if the specific operand node N of
1598 /// U can be folded during instruction selection that starts at Root.
1599 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1600 CodeGenOpt::Level OptLevel,
1601 bool IgnoreChains) {
1602 if (OptLevel == CodeGenOpt::None) return false;
1604 // If Root use can somehow reach N through a path that that doesn't contain
1605 // U then folding N would create a cycle. e.g. In the following
1606 // diagram, Root can reach N through X. If N is folded into into Root, then
1607 // X is both a predecessor and a successor of U.
1618 // * indicates nodes to be folded together.
1620 // If Root produces glue, then it gets (even more) interesting. Since it
1621 // will be "glued" together with its glue use in the scheduler, we need to
1622 // check if it might reach N.
1641 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1642 // (call it Fold), then X is a predecessor of GU and a successor of
1643 // Fold. But since Fold and GU are glued together, this will create
1644 // a cycle in the scheduling graph.
1646 // If the node has glue, walk down the graph to the "lowest" node in the
1648 EVT VT = Root->getValueType(Root->getNumValues()-1);
1649 while (VT == MVT::Glue) {
1650 SDNode *GU = findGlueUse(Root);
1654 VT = Root->getValueType(Root->getNumValues()-1);
1656 // If our query node has a glue result with a use, we've walked up it. If
1657 // the user (which has already been selected) has a chain or indirectly uses
1658 // the chain, our WalkChainUsers predicate will not consider it. Because of
1659 // this, we cannot ignore chains in this predicate.
1660 IgnoreChains = false;
1664 SmallPtrSet<SDNode*, 16> Visited;
1665 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1668 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1669 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1670 SelectInlineAsmMemoryOperands(Ops);
1672 EVT VTs[] = { MVT::Other, MVT::Glue };
1673 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1674 VTs, &Ops[0], Ops.size());
1676 return New.getNode();
1679 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1680 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1683 /// GetVBR - decode a vbr encoding whose top bit is set.
1684 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1685 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1686 assert(Val >= 128 && "Not a VBR");
1687 Val &= 127; // Remove first vbr bit.
1692 NextBits = MatcherTable[Idx++];
1693 Val |= (NextBits&127) << Shift;
1695 } while (NextBits & 128);
1701 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1702 /// interior glue and chain results to use the new glue and chain results.
1703 void SelectionDAGISel::
1704 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1705 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1707 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1708 bool isMorphNodeTo) {
1709 SmallVector<SDNode*, 4> NowDeadNodes;
1711 // Now that all the normal results are replaced, we replace the chain and
1712 // glue results if present.
1713 if (!ChainNodesMatched.empty()) {
1714 assert(InputChain.getNode() != 0 &&
1715 "Matched input chains but didn't produce a chain");
1716 // Loop over all of the nodes we matched that produced a chain result.
1717 // Replace all the chain results with the final chain we ended up with.
1718 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1719 SDNode *ChainNode = ChainNodesMatched[i];
1721 // If this node was already deleted, don't look at it.
1722 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1725 // Don't replace the results of the root node if we're doing a
1727 if (ChainNode == NodeToMatch && isMorphNodeTo)
1730 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1731 if (ChainVal.getValueType() == MVT::Glue)
1732 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1733 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1734 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
1736 // If the node became dead and we haven't already seen it, delete it.
1737 if (ChainNode->use_empty() &&
1738 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1739 NowDeadNodes.push_back(ChainNode);
1743 // If the result produces glue, update any glue results in the matched
1744 // pattern with the glue result.
1745 if (InputGlue.getNode() != 0) {
1746 // Handle any interior nodes explicitly marked.
1747 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1748 SDNode *FRN = GlueResultNodesMatched[i];
1750 // If this node was already deleted, don't look at it.
1751 if (FRN->getOpcode() == ISD::DELETED_NODE)
1754 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1755 "Doesn't have a glue result");
1756 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1759 // If the node became dead and we haven't already seen it, delete it.
1760 if (FRN->use_empty() &&
1761 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1762 NowDeadNodes.push_back(FRN);
1766 if (!NowDeadNodes.empty())
1767 CurDAG->RemoveDeadNodes(NowDeadNodes);
1769 DEBUG(errs() << "ISEL: Match complete!\n");
1775 CR_LeadsToInteriorNode
1778 /// WalkChainUsers - Walk down the users of the specified chained node that is
1779 /// part of the pattern we're matching, looking at all of the users we find.
1780 /// This determines whether something is an interior node, whether we have a
1781 /// non-pattern node in between two pattern nodes (which prevent folding because
1782 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1783 /// between pattern nodes (in which case the TF becomes part of the pattern).
1785 /// The walk we do here is guaranteed to be small because we quickly get down to
1786 /// already selected nodes "below" us.
1788 WalkChainUsers(const SDNode *ChainedNode,
1789 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1790 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1791 ChainResult Result = CR_Simple;
1793 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1794 E = ChainedNode->use_end(); UI != E; ++UI) {
1795 // Make sure the use is of the chain, not some other value we produce.
1796 if (UI.getUse().getValueType() != MVT::Other) continue;
1800 // If we see an already-selected machine node, then we've gone beyond the
1801 // pattern that we're selecting down into the already selected chunk of the
1803 if (User->isMachineOpcode() ||
1804 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1807 unsigned UserOpcode = User->getOpcode();
1808 if (UserOpcode == ISD::CopyToReg ||
1809 UserOpcode == ISD::CopyFromReg ||
1810 UserOpcode == ISD::INLINEASM ||
1811 UserOpcode == ISD::EH_LABEL ||
1812 UserOpcode == ISD::LIFETIME_START ||
1813 UserOpcode == ISD::LIFETIME_END) {
1814 // If their node ID got reset to -1 then they've already been selected.
1815 // Treat them like a MachineOpcode.
1816 if (User->getNodeId() == -1)
1820 // If we have a TokenFactor, we handle it specially.
1821 if (User->getOpcode() != ISD::TokenFactor) {
1822 // If the node isn't a token factor and isn't part of our pattern, then it
1823 // must be a random chained node in between two nodes we're selecting.
1824 // This happens when we have something like:
1829 // Because we structurally match the load/store as a read/modify/write,
1830 // but the call is chained between them. We cannot fold in this case
1831 // because it would induce a cycle in the graph.
1832 if (!std::count(ChainedNodesInPattern.begin(),
1833 ChainedNodesInPattern.end(), User))
1834 return CR_InducesCycle;
1836 // Otherwise we found a node that is part of our pattern. For example in:
1840 // This would happen when we're scanning down from the load and see the
1841 // store as a user. Record that there is a use of ChainedNode that is
1842 // part of the pattern and keep scanning uses.
1843 Result = CR_LeadsToInteriorNode;
1844 InteriorChainedNodes.push_back(User);
1848 // If we found a TokenFactor, there are two cases to consider: first if the
1849 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1850 // uses of the TF are in our pattern) we just want to ignore it. Second,
1851 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1857 // | \ DAG's like cheese
1860 // [TokenFactor] [Op]
1867 // In this case, the TokenFactor becomes part of our match and we rewrite it
1868 // as a new TokenFactor.
1870 // To distinguish these two cases, do a recursive walk down the uses.
1871 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1873 // If the uses of the TokenFactor are just already-selected nodes, ignore
1874 // it, it is "below" our pattern.
1876 case CR_InducesCycle:
1877 // If the uses of the TokenFactor lead to nodes that are not part of our
1878 // pattern that are not selected, folding would turn this into a cycle,
1880 return CR_InducesCycle;
1881 case CR_LeadsToInteriorNode:
1882 break; // Otherwise, keep processing.
1885 // Okay, we know we're in the interesting interior case. The TokenFactor
1886 // is now going to be considered part of the pattern so that we rewrite its
1887 // uses (it may have uses that are not part of the pattern) with the
1888 // ultimate chain result of the generated code. We will also add its chain
1889 // inputs as inputs to the ultimate TokenFactor we create.
1890 Result = CR_LeadsToInteriorNode;
1891 ChainedNodesInPattern.push_back(User);
1892 InteriorChainedNodes.push_back(User);
1899 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1900 /// operation for when the pattern matched at least one node with a chains. The
1901 /// input vector contains a list of all of the chained nodes that we match. We
1902 /// must determine if this is a valid thing to cover (i.e. matching it won't
1903 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1904 /// be used as the input node chain for the generated nodes.
1906 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1907 SelectionDAG *CurDAG) {
1908 // Walk all of the chained nodes we've matched, recursively scanning down the
1909 // users of the chain result. This adds any TokenFactor nodes that are caught
1910 // in between chained nodes to the chained and interior nodes list.
1911 SmallVector<SDNode*, 3> InteriorChainedNodes;
1912 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1913 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1914 InteriorChainedNodes) == CR_InducesCycle)
1915 return SDValue(); // Would induce a cycle.
1918 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1919 // that we are interested in. Form our input TokenFactor node.
1920 SmallVector<SDValue, 3> InputChains;
1921 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1922 // Add the input chain of this node to the InputChains list (which will be
1923 // the operands of the generated TokenFactor) if it's not an interior node.
1924 SDNode *N = ChainNodesMatched[i];
1925 if (N->getOpcode() != ISD::TokenFactor) {
1926 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1929 // Otherwise, add the input chain.
1930 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1931 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1932 InputChains.push_back(InChain);
1936 // If we have a token factor, we want to add all inputs of the token factor
1937 // that are not part of the pattern we're matching.
1938 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1939 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1940 N->getOperand(op).getNode()))
1941 InputChains.push_back(N->getOperand(op));
1946 if (InputChains.size() == 1)
1947 return InputChains[0];
1948 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1949 MVT::Other, &InputChains[0], InputChains.size());
1952 /// MorphNode - Handle morphing a node in place for the selector.
1953 SDNode *SelectionDAGISel::
1954 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1955 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1956 // It is possible we're using MorphNodeTo to replace a node with no
1957 // normal results with one that has a normal result (or we could be
1958 // adding a chain) and the input could have glue and chains as well.
1959 // In this case we need to shift the operands down.
1960 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1961 // than the old isel though.
1962 int OldGlueResultNo = -1, OldChainResultNo = -1;
1964 unsigned NTMNumResults = Node->getNumValues();
1965 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
1966 OldGlueResultNo = NTMNumResults-1;
1967 if (NTMNumResults != 1 &&
1968 Node->getValueType(NTMNumResults-2) == MVT::Other)
1969 OldChainResultNo = NTMNumResults-2;
1970 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1971 OldChainResultNo = NTMNumResults-1;
1973 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1974 // that this deletes operands of the old node that become dead.
1975 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1977 // MorphNodeTo can operate in two ways: if an existing node with the
1978 // specified operands exists, it can just return it. Otherwise, it
1979 // updates the node in place to have the requested operands.
1981 // If we updated the node in place, reset the node ID. To the isel,
1982 // this should be just like a newly allocated machine node.
1986 unsigned ResNumResults = Res->getNumValues();
1987 // Move the glue if needed.
1988 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
1989 (unsigned)OldGlueResultNo != ResNumResults-1)
1990 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
1991 SDValue(Res, ResNumResults-1));
1993 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
1996 // Move the chain reference if needed.
1997 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1998 (unsigned)OldChainResultNo != ResNumResults-1)
1999 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2000 SDValue(Res, ResNumResults-1));
2002 // Otherwise, no replacement happened because the node already exists. Replace
2003 // Uses of the old node with the new one.
2005 CurDAG->ReplaceAllUsesWith(Node, Res);
2010 /// CheckSame - Implements OP_CheckSame.
2011 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2012 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2014 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2015 // Accept if it is exactly the same as a previously recorded node.
2016 unsigned RecNo = MatcherTable[MatcherIndex++];
2017 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2018 return N == RecordedNodes[RecNo].first;
2021 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2022 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2023 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2024 const SelectionDAGISel &SDISel) {
2025 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2028 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2029 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2030 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2031 const SelectionDAGISel &SDISel, SDNode *N) {
2032 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2035 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2036 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2038 uint16_t Opc = MatcherTable[MatcherIndex++];
2039 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2040 return N->getOpcode() == Opc;
2043 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2044 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2045 SDValue N, const TargetLowering &TLI) {
2046 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2047 if (N.getValueType() == VT) return true;
2049 // Handle the case when VT is iPTR.
2050 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
2053 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2054 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2055 SDValue N, const TargetLowering &TLI,
2057 if (ChildNo >= N.getNumOperands())
2058 return false; // Match fails if out of range child #.
2059 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2063 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2064 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2066 return cast<CondCodeSDNode>(N)->get() ==
2067 (ISD::CondCode)MatcherTable[MatcherIndex++];
2070 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2071 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2072 SDValue N, const TargetLowering &TLI) {
2073 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2074 if (cast<VTSDNode>(N)->getVT() == VT)
2077 // Handle the case when VT is iPTR.
2078 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
2081 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2082 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2084 int64_t Val = MatcherTable[MatcherIndex++];
2086 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2088 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2089 return C != 0 && C->getSExtValue() == Val;
2092 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2093 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2094 SDValue N, const SelectionDAGISel &SDISel) {
2095 int64_t Val = MatcherTable[MatcherIndex++];
2097 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2099 if (N->getOpcode() != ISD::AND) return false;
2101 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2102 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2105 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2106 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2107 SDValue N, const SelectionDAGISel &SDISel) {
2108 int64_t Val = MatcherTable[MatcherIndex++];
2110 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2112 if (N->getOpcode() != ISD::OR) return false;
2114 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2115 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2118 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2119 /// scope, evaluate the current node. If the current predicate is known to
2120 /// fail, set Result=true and return anything. If the current predicate is
2121 /// known to pass, set Result=false and return the MatcherIndex to continue
2122 /// with. If the current predicate is unknown, set Result=false and return the
2123 /// MatcherIndex to continue with.
2124 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2125 unsigned Index, SDValue N,
2127 const SelectionDAGISel &SDISel,
2128 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2129 switch (Table[Index++]) {
2132 return Index-1; // Could not evaluate this predicate.
2133 case SelectionDAGISel::OPC_CheckSame:
2134 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2136 case SelectionDAGISel::OPC_CheckPatternPredicate:
2137 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2139 case SelectionDAGISel::OPC_CheckPredicate:
2140 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2142 case SelectionDAGISel::OPC_CheckOpcode:
2143 Result = !::CheckOpcode(Table, Index, N.getNode());
2145 case SelectionDAGISel::OPC_CheckType:
2146 Result = !::CheckType(Table, Index, N, SDISel.TLI);
2148 case SelectionDAGISel::OPC_CheckChild0Type:
2149 case SelectionDAGISel::OPC_CheckChild1Type:
2150 case SelectionDAGISel::OPC_CheckChild2Type:
2151 case SelectionDAGISel::OPC_CheckChild3Type:
2152 case SelectionDAGISel::OPC_CheckChild4Type:
2153 case SelectionDAGISel::OPC_CheckChild5Type:
2154 case SelectionDAGISel::OPC_CheckChild6Type:
2155 case SelectionDAGISel::OPC_CheckChild7Type:
2156 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
2157 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
2159 case SelectionDAGISel::OPC_CheckCondCode:
2160 Result = !::CheckCondCode(Table, Index, N);
2162 case SelectionDAGISel::OPC_CheckValueType:
2163 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2165 case SelectionDAGISel::OPC_CheckInteger:
2166 Result = !::CheckInteger(Table, Index, N);
2168 case SelectionDAGISel::OPC_CheckAndImm:
2169 Result = !::CheckAndImm(Table, Index, N, SDISel);
2171 case SelectionDAGISel::OPC_CheckOrImm:
2172 Result = !::CheckOrImm(Table, Index, N, SDISel);
2180 /// FailIndex - If this match fails, this is the index to continue with.
2183 /// NodeStack - The node stack when the scope was formed.
2184 SmallVector<SDValue, 4> NodeStack;
2186 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2187 unsigned NumRecordedNodes;
2189 /// NumMatchedMemRefs - The number of matched memref entries.
2190 unsigned NumMatchedMemRefs;
2192 /// InputChain/InputGlue - The current chain/glue
2193 SDValue InputChain, InputGlue;
2195 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2196 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2201 SDNode *SelectionDAGISel::
2202 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2203 unsigned TableSize) {
2204 // FIXME: Should these even be selected? Handle these cases in the caller?
2205 switch (NodeToMatch->getOpcode()) {
2208 case ISD::EntryToken: // These nodes remain the same.
2209 case ISD::BasicBlock:
2211 case ISD::RegisterMask:
2212 //case ISD::VALUETYPE:
2213 //case ISD::CONDCODE:
2214 case ISD::HANDLENODE:
2215 case ISD::MDNODE_SDNODE:
2216 case ISD::TargetConstant:
2217 case ISD::TargetConstantFP:
2218 case ISD::TargetConstantPool:
2219 case ISD::TargetFrameIndex:
2220 case ISD::TargetExternalSymbol:
2221 case ISD::TargetBlockAddress:
2222 case ISD::TargetJumpTable:
2223 case ISD::TargetGlobalTLSAddress:
2224 case ISD::TargetGlobalAddress:
2225 case ISD::TokenFactor:
2226 case ISD::CopyFromReg:
2227 case ISD::CopyToReg:
2229 case ISD::LIFETIME_START:
2230 case ISD::LIFETIME_END:
2231 NodeToMatch->setNodeId(-1); // Mark selected.
2233 case ISD::AssertSext:
2234 case ISD::AssertZext:
2235 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2236 NodeToMatch->getOperand(0));
2238 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2239 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2242 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2244 // Set up the node stack with NodeToMatch as the only node on the stack.
2245 SmallVector<SDValue, 8> NodeStack;
2246 SDValue N = SDValue(NodeToMatch, 0);
2247 NodeStack.push_back(N);
2249 // MatchScopes - Scopes used when matching, if a match failure happens, this
2250 // indicates where to continue checking.
2251 SmallVector<MatchScope, 8> MatchScopes;
2253 // RecordedNodes - This is the set of nodes that have been recorded by the
2254 // state machine. The second value is the parent of the node, or null if the
2255 // root is recorded.
2256 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2258 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2260 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2262 // These are the current input chain and glue for use when generating nodes.
2263 // Various Emit operations change these. For example, emitting a copytoreg
2264 // uses and updates these.
2265 SDValue InputChain, InputGlue;
2267 // ChainNodesMatched - If a pattern matches nodes that have input/output
2268 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2269 // which ones they are. The result is captured into this list so that we can
2270 // update the chain results when the pattern is complete.
2271 SmallVector<SDNode*, 3> ChainNodesMatched;
2272 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2274 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2275 NodeToMatch->dump(CurDAG);
2278 // Determine where to start the interpreter. Normally we start at opcode #0,
2279 // but if the state machine starts with an OPC_SwitchOpcode, then we
2280 // accelerate the first lookup (which is guaranteed to be hot) with the
2281 // OpcodeOffset table.
2282 unsigned MatcherIndex = 0;
2284 if (!OpcodeOffset.empty()) {
2285 // Already computed the OpcodeOffset table, just index into it.
2286 if (N.getOpcode() < OpcodeOffset.size())
2287 MatcherIndex = OpcodeOffset[N.getOpcode()];
2288 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2290 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2291 // Otherwise, the table isn't computed, but the state machine does start
2292 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2293 // is the first time we're selecting an instruction.
2296 // Get the size of this case.
2297 unsigned CaseSize = MatcherTable[Idx++];
2299 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2300 if (CaseSize == 0) break;
2302 // Get the opcode, add the index to the table.
2303 uint16_t Opc = MatcherTable[Idx++];
2304 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2305 if (Opc >= OpcodeOffset.size())
2306 OpcodeOffset.resize((Opc+1)*2);
2307 OpcodeOffset[Opc] = Idx;
2311 // Okay, do the lookup for the first opcode.
2312 if (N.getOpcode() < OpcodeOffset.size())
2313 MatcherIndex = OpcodeOffset[N.getOpcode()];
2317 assert(MatcherIndex < TableSize && "Invalid index");
2319 unsigned CurrentOpcodeIndex = MatcherIndex;
2321 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2324 // Okay, the semantics of this operation are that we should push a scope
2325 // then evaluate the first child. However, pushing a scope only to have
2326 // the first check fail (which then pops it) is inefficient. If we can
2327 // determine immediately that the first check (or first several) will
2328 // immediately fail, don't even bother pushing a scope for them.
2332 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2333 if (NumToSkip & 128)
2334 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2335 // Found the end of the scope with no match.
2336 if (NumToSkip == 0) {
2341 FailIndex = MatcherIndex+NumToSkip;
2343 unsigned MatcherIndexOfPredicate = MatcherIndex;
2344 (void)MatcherIndexOfPredicate; // silence warning.
2346 // If we can't evaluate this predicate without pushing a scope (e.g. if
2347 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2348 // push the scope and evaluate the full predicate chain.
2350 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2351 Result, *this, RecordedNodes);
2355 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2356 << "index " << MatcherIndexOfPredicate
2357 << ", continuing at " << FailIndex << "\n");
2358 ++NumDAGIselRetries;
2360 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2361 // move to the next case.
2362 MatcherIndex = FailIndex;
2365 // If the whole scope failed to match, bail.
2366 if (FailIndex == 0) break;
2368 // Push a MatchScope which indicates where to go if the first child fails
2370 MatchScope NewEntry;
2371 NewEntry.FailIndex = FailIndex;
2372 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2373 NewEntry.NumRecordedNodes = RecordedNodes.size();
2374 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2375 NewEntry.InputChain = InputChain;
2376 NewEntry.InputGlue = InputGlue;
2377 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2378 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2379 MatchScopes.push_back(NewEntry);
2382 case OPC_RecordNode: {
2383 // Remember this node, it may end up being an operand in the pattern.
2385 if (NodeStack.size() > 1)
2386 Parent = NodeStack[NodeStack.size()-2].getNode();
2387 RecordedNodes.push_back(std::make_pair(N, Parent));
2391 case OPC_RecordChild0: case OPC_RecordChild1:
2392 case OPC_RecordChild2: case OPC_RecordChild3:
2393 case OPC_RecordChild4: case OPC_RecordChild5:
2394 case OPC_RecordChild6: case OPC_RecordChild7: {
2395 unsigned ChildNo = Opcode-OPC_RecordChild0;
2396 if (ChildNo >= N.getNumOperands())
2397 break; // Match fails if out of range child #.
2399 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2403 case OPC_RecordMemRef:
2404 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2407 case OPC_CaptureGlueInput:
2408 // If the current node has an input glue, capture it in InputGlue.
2409 if (N->getNumOperands() != 0 &&
2410 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2411 InputGlue = N->getOperand(N->getNumOperands()-1);
2414 case OPC_MoveChild: {
2415 unsigned ChildNo = MatcherTable[MatcherIndex++];
2416 if (ChildNo >= N.getNumOperands())
2417 break; // Match fails if out of range child #.
2418 N = N.getOperand(ChildNo);
2419 NodeStack.push_back(N);
2423 case OPC_MoveParent:
2424 // Pop the current node off the NodeStack.
2425 NodeStack.pop_back();
2426 assert(!NodeStack.empty() && "Node stack imbalance!");
2427 N = NodeStack.back();
2431 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2433 case OPC_CheckPatternPredicate:
2434 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2436 case OPC_CheckPredicate:
2437 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2441 case OPC_CheckComplexPat: {
2442 unsigned CPNum = MatcherTable[MatcherIndex++];
2443 unsigned RecNo = MatcherTable[MatcherIndex++];
2444 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2445 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2446 RecordedNodes[RecNo].first, CPNum,
2451 case OPC_CheckOpcode:
2452 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2456 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2459 case OPC_SwitchOpcode: {
2460 unsigned CurNodeOpcode = N.getOpcode();
2461 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2464 // Get the size of this case.
2465 CaseSize = MatcherTable[MatcherIndex++];
2467 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2468 if (CaseSize == 0) break;
2470 uint16_t Opc = MatcherTable[MatcherIndex++];
2471 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2473 // If the opcode matches, then we will execute this case.
2474 if (CurNodeOpcode == Opc)
2477 // Otherwise, skip over this case.
2478 MatcherIndex += CaseSize;
2481 // If no cases matched, bail out.
2482 if (CaseSize == 0) break;
2484 // Otherwise, execute the case we found.
2485 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2486 << " to " << MatcherIndex << "\n");
2490 case OPC_SwitchType: {
2491 MVT CurNodeVT = N.getValueType().getSimpleVT();
2492 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2495 // Get the size of this case.
2496 CaseSize = MatcherTable[MatcherIndex++];
2498 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2499 if (CaseSize == 0) break;
2501 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2502 if (CaseVT == MVT::iPTR)
2503 CaseVT = TLI.getPointerTy();
2505 // If the VT matches, then we will execute this case.
2506 if (CurNodeVT == CaseVT)
2509 // Otherwise, skip over this case.
2510 MatcherIndex += CaseSize;
2513 // If no cases matched, bail out.
2514 if (CaseSize == 0) break;
2516 // Otherwise, execute the case we found.
2517 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2518 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2521 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2522 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2523 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2524 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2525 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2526 Opcode-OPC_CheckChild0Type))
2529 case OPC_CheckCondCode:
2530 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2532 case OPC_CheckValueType:
2533 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2535 case OPC_CheckInteger:
2536 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2538 case OPC_CheckAndImm:
2539 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2541 case OPC_CheckOrImm:
2542 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2545 case OPC_CheckFoldableChainNode: {
2546 assert(NodeStack.size() != 1 && "No parent node");
2547 // Verify that all intermediate nodes between the root and this one have
2549 bool HasMultipleUses = false;
2550 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2551 if (!NodeStack[i].hasOneUse()) {
2552 HasMultipleUses = true;
2555 if (HasMultipleUses) break;
2557 // Check to see that the target thinks this is profitable to fold and that
2558 // we can fold it without inducing cycles in the graph.
2559 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2561 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2562 NodeToMatch, OptLevel,
2563 true/*We validate our own chains*/))
2568 case OPC_EmitInteger: {
2569 MVT::SimpleValueType VT =
2570 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2571 int64_t Val = MatcherTable[MatcherIndex++];
2573 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2574 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2575 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2578 case OPC_EmitRegister: {
2579 MVT::SimpleValueType VT =
2580 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2581 unsigned RegNo = MatcherTable[MatcherIndex++];
2582 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2583 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2586 case OPC_EmitRegister2: {
2587 // For targets w/ more than 256 register names, the register enum
2588 // values are stored in two bytes in the matcher table (just like
2590 MVT::SimpleValueType VT =
2591 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2592 unsigned RegNo = MatcherTable[MatcherIndex++];
2593 RegNo |= MatcherTable[MatcherIndex++] << 8;
2594 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2595 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2599 case OPC_EmitConvertToTarget: {
2600 // Convert from IMM/FPIMM to target version.
2601 unsigned RecNo = MatcherTable[MatcherIndex++];
2602 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2603 SDValue Imm = RecordedNodes[RecNo].first;
2605 if (Imm->getOpcode() == ISD::Constant) {
2606 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
2607 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true);
2608 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2609 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2610 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true);
2613 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2617 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2618 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2619 // These are space-optimized forms of OPC_EmitMergeInputChains.
2620 assert(InputChain.getNode() == 0 &&
2621 "EmitMergeInputChains should be the first chain producing node");
2622 assert(ChainNodesMatched.empty() &&
2623 "Should only have one EmitMergeInputChains per match");
2625 // Read all of the chained nodes.
2626 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2627 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2628 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2630 // FIXME: What if other value results of the node have uses not matched
2632 if (ChainNodesMatched.back() != NodeToMatch &&
2633 !RecordedNodes[RecNo].first.hasOneUse()) {
2634 ChainNodesMatched.clear();
2638 // Merge the input chains if they are not intra-pattern references.
2639 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2641 if (InputChain.getNode() == 0)
2642 break; // Failed to merge.
2646 case OPC_EmitMergeInputChains: {
2647 assert(InputChain.getNode() == 0 &&
2648 "EmitMergeInputChains should be the first chain producing node");
2649 // This node gets a list of nodes we matched in the input that have
2650 // chains. We want to token factor all of the input chains to these nodes
2651 // together. However, if any of the input chains is actually one of the
2652 // nodes matched in this pattern, then we have an intra-match reference.
2653 // Ignore these because the newly token factored chain should not refer to
2655 unsigned NumChains = MatcherTable[MatcherIndex++];
2656 assert(NumChains != 0 && "Can't TF zero chains");
2658 assert(ChainNodesMatched.empty() &&
2659 "Should only have one EmitMergeInputChains per match");
2661 // Read all of the chained nodes.
2662 for (unsigned i = 0; i != NumChains; ++i) {
2663 unsigned RecNo = MatcherTable[MatcherIndex++];
2664 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2665 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2667 // FIXME: What if other value results of the node have uses not matched
2669 if (ChainNodesMatched.back() != NodeToMatch &&
2670 !RecordedNodes[RecNo].first.hasOneUse()) {
2671 ChainNodesMatched.clear();
2676 // If the inner loop broke out, the match fails.
2677 if (ChainNodesMatched.empty())
2680 // Merge the input chains if they are not intra-pattern references.
2681 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2683 if (InputChain.getNode() == 0)
2684 break; // Failed to merge.
2689 case OPC_EmitCopyToReg: {
2690 unsigned RecNo = MatcherTable[MatcherIndex++];
2691 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2692 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2694 if (InputChain.getNode() == 0)
2695 InputChain = CurDAG->getEntryNode();
2697 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2698 DestPhysReg, RecordedNodes[RecNo].first,
2701 InputGlue = InputChain.getValue(1);
2705 case OPC_EmitNodeXForm: {
2706 unsigned XFormNo = MatcherTable[MatcherIndex++];
2707 unsigned RecNo = MatcherTable[MatcherIndex++];
2708 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2709 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2710 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2715 case OPC_MorphNodeTo: {
2716 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2717 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2718 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2719 // Get the result VT list.
2720 unsigned NumVTs = MatcherTable[MatcherIndex++];
2721 SmallVector<EVT, 4> VTs;
2722 for (unsigned i = 0; i != NumVTs; ++i) {
2723 MVT::SimpleValueType VT =
2724 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2725 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2729 if (EmitNodeInfo & OPFL_Chain)
2730 VTs.push_back(MVT::Other);
2731 if (EmitNodeInfo & OPFL_GlueOutput)
2732 VTs.push_back(MVT::Glue);
2734 // This is hot code, so optimize the two most common cases of 1 and 2
2737 if (VTs.size() == 1)
2738 VTList = CurDAG->getVTList(VTs[0]);
2739 else if (VTs.size() == 2)
2740 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2742 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2744 // Get the operand list.
2745 unsigned NumOps = MatcherTable[MatcherIndex++];
2746 SmallVector<SDValue, 8> Ops;
2747 for (unsigned i = 0; i != NumOps; ++i) {
2748 unsigned RecNo = MatcherTable[MatcherIndex++];
2750 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2752 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2753 Ops.push_back(RecordedNodes[RecNo].first);
2756 // If there are variadic operands to add, handle them now.
2757 if (EmitNodeInfo & OPFL_VariadicInfo) {
2758 // Determine the start index to copy from.
2759 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2760 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2761 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2762 "Invalid variadic node");
2763 // Copy all of the variadic operands, not including a potential glue
2765 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2767 SDValue V = NodeToMatch->getOperand(i);
2768 if (V.getValueType() == MVT::Glue) break;
2773 // If this has chain/glue inputs, add them.
2774 if (EmitNodeInfo & OPFL_Chain)
2775 Ops.push_back(InputChain);
2776 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2777 Ops.push_back(InputGlue);
2781 if (Opcode != OPC_MorphNodeTo) {
2782 // If this is a normal EmitNode command, just create the new node and
2783 // add the results to the RecordedNodes list.
2784 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2785 VTList, Ops.data(), Ops.size());
2787 // Add all the non-glue/non-chain results to the RecordedNodes list.
2788 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2789 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2790 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2794 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
2795 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2798 // NodeToMatch was eliminated by CSE when the target changed the DAG.
2799 // We will visit the equivalent node later.
2800 DEBUG(dbgs() << "Node was eliminated by CSE\n");
2804 // If the node had chain/glue results, update our notion of the current
2806 if (EmitNodeInfo & OPFL_GlueOutput) {
2807 InputGlue = SDValue(Res, VTs.size()-1);
2808 if (EmitNodeInfo & OPFL_Chain)
2809 InputChain = SDValue(Res, VTs.size()-2);
2810 } else if (EmitNodeInfo & OPFL_Chain)
2811 InputChain = SDValue(Res, VTs.size()-1);
2813 // If the OPFL_MemRefs glue is set on this node, slap all of the
2814 // accumulated memrefs onto it.
2816 // FIXME: This is vastly incorrect for patterns with multiple outputs
2817 // instructions that access memory and for ComplexPatterns that match
2819 if (EmitNodeInfo & OPFL_MemRefs) {
2820 // Only attach load or store memory operands if the generated
2821 // instruction may load or store.
2822 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc);
2823 bool mayLoad = MCID.mayLoad();
2824 bool mayStore = MCID.mayStore();
2826 unsigned NumMemRefs = 0;
2827 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2828 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2829 if ((*I)->isLoad()) {
2832 } else if ((*I)->isStore()) {
2840 MachineSDNode::mmo_iterator MemRefs =
2841 MF->allocateMemRefsArray(NumMemRefs);
2843 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
2844 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2845 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2846 if ((*I)->isLoad()) {
2849 } else if ((*I)->isStore()) {
2857 cast<MachineSDNode>(Res)
2858 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
2862 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2863 << " node: "; Res->dump(CurDAG); errs() << "\n");
2865 // If this was a MorphNodeTo then we're completely done!
2866 if (Opcode == OPC_MorphNodeTo) {
2867 // Update chain and glue uses.
2868 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2869 InputGlue, GlueResultNodesMatched, true);
2876 case OPC_MarkGlueResults: {
2877 unsigned NumNodes = MatcherTable[MatcherIndex++];
2879 // Read and remember all the glue-result nodes.
2880 for (unsigned i = 0; i != NumNodes; ++i) {
2881 unsigned RecNo = MatcherTable[MatcherIndex++];
2883 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2885 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2886 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2891 case OPC_CompleteMatch: {
2892 // The match has been completed, and any new nodes (if any) have been
2893 // created. Patch up references to the matched dag to use the newly
2895 unsigned NumResults = MatcherTable[MatcherIndex++];
2897 for (unsigned i = 0; i != NumResults; ++i) {
2898 unsigned ResSlot = MatcherTable[MatcherIndex++];
2900 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2902 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2903 SDValue Res = RecordedNodes[ResSlot].first;
2905 assert(i < NodeToMatch->getNumValues() &&
2906 NodeToMatch->getValueType(i) != MVT::Other &&
2907 NodeToMatch->getValueType(i) != MVT::Glue &&
2908 "Invalid number of results to complete!");
2909 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2910 NodeToMatch->getValueType(i) == MVT::iPTR ||
2911 Res.getValueType() == MVT::iPTR ||
2912 NodeToMatch->getValueType(i).getSizeInBits() ==
2913 Res.getValueType().getSizeInBits()) &&
2914 "invalid replacement");
2915 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2918 // If the root node defines glue, add it to the glue nodes to update list.
2919 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
2920 GlueResultNodesMatched.push_back(NodeToMatch);
2922 // Update chain and glue uses.
2923 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2924 InputGlue, GlueResultNodesMatched, false);
2926 assert(NodeToMatch->use_empty() &&
2927 "Didn't replace all uses of the node?");
2929 // FIXME: We just return here, which interacts correctly with SelectRoot
2930 // above. We should fix this to not return an SDNode* anymore.
2935 // If the code reached this point, then the match failed. See if there is
2936 // another child to try in the current 'Scope', otherwise pop it until we
2937 // find a case to check.
2938 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2939 ++NumDAGIselRetries;
2941 if (MatchScopes.empty()) {
2942 CannotYetSelect(NodeToMatch);
2946 // Restore the interpreter state back to the point where the scope was
2948 MatchScope &LastScope = MatchScopes.back();
2949 RecordedNodes.resize(LastScope.NumRecordedNodes);
2951 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2952 N = NodeStack.back();
2954 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2955 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2956 MatcherIndex = LastScope.FailIndex;
2958 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2960 InputChain = LastScope.InputChain;
2961 InputGlue = LastScope.InputGlue;
2962 if (!LastScope.HasChainNodesMatched)
2963 ChainNodesMatched.clear();
2964 if (!LastScope.HasGlueResultNodesMatched)
2965 GlueResultNodesMatched.clear();
2967 // Check to see what the offset is at the new MatcherIndex. If it is zero
2968 // we have reached the end of this scope, otherwise we have another child
2969 // in the current scope to try.
2970 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2971 if (NumToSkip & 128)
2972 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2974 // If we have another child in this scope to match, update FailIndex and
2976 if (NumToSkip != 0) {
2977 LastScope.FailIndex = MatcherIndex+NumToSkip;
2981 // End of this scope, pop it and try the next child in the containing
2983 MatchScopes.pop_back();
2990 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2992 raw_string_ostream Msg(msg);
2993 Msg << "Cannot select: ";
2995 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2996 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2997 N->getOpcode() != ISD::INTRINSIC_VOID) {
2998 N->printrFull(Msg, CurDAG);
2999 Msg << "\nIn function: " << MF->getName();
3001 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3003 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3004 if (iid < Intrinsic::num_intrinsics)
3005 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3006 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3007 Msg << "target intrinsic %" << TII->getName(iid);
3009 Msg << "unknown intrinsic #" << iid;
3011 report_fatal_error(Msg.str());
3014 char SelectionDAGISel::ID = 0;