1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/CodeGen/FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/LLVMContext.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/GCStrategy.h"
31 #include "llvm/CodeGen/GCMetadata.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
38 #include "llvm/CodeGen/SchedulerRegistry.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetIntrinsicInfo.h"
42 #include "llvm/Target/TargetInstrInfo.h"
43 #include "llvm/Target/TargetLowering.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/Support/Compiler.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/Timer.h"
50 #include "llvm/Support/raw_ostream.h"
51 #include "llvm/ADT/Statistic.h"
55 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
56 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
59 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
60 cl::desc("Enable verbose messages in the \"fast\" "
61 "instruction selector"));
63 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
64 cl::desc("Enable abort calls when \"fast\" instruction fails"));
68 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
69 cl::desc("Pop up a window to show dags before the first "
72 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
73 cl::desc("Pop up a window to show dags before legalize types"));
75 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
76 cl::desc("Pop up a window to show dags before legalize"));
78 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
79 cl::desc("Pop up a window to show dags before the second "
82 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
83 cl::desc("Pop up a window to show dags before the post legalize types"
84 " dag combine pass"));
86 ViewISelDAGs("view-isel-dags", cl::Hidden,
87 cl::desc("Pop up a window to show isel dags as they are selected"));
89 ViewSchedDAGs("view-sched-dags", cl::Hidden,
90 cl::desc("Pop up a window to show sched dags as they are processed"));
92 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
93 cl::desc("Pop up a window to show SUnit dags after they are processed"));
95 static const bool ViewDAGCombine1 = false,
96 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
97 ViewDAGCombine2 = false,
98 ViewDAGCombineLT = false,
99 ViewISelDAGs = false, ViewSchedDAGs = false,
100 ViewSUnitDAGs = false;
103 //===---------------------------------------------------------------------===//
105 /// RegisterScheduler class - Track the registration of instruction schedulers.
107 //===---------------------------------------------------------------------===//
108 MachinePassRegistry RegisterScheduler::Registry;
110 //===---------------------------------------------------------------------===//
112 /// ISHeuristic command line option for instruction schedulers.
114 //===---------------------------------------------------------------------===//
115 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
116 RegisterPassParser<RegisterScheduler> >
117 ISHeuristic("pre-RA-sched",
118 cl::init(&createDefaultScheduler),
119 cl::desc("Instruction schedulers available (before register"
122 static RegisterScheduler
123 defaultListDAGScheduler("default", "Best scheduler for the target",
124 createDefaultScheduler);
127 //===--------------------------------------------------------------------===//
128 /// createDefaultScheduler - This creates an instruction scheduler appropriate
130 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
131 CodeGenOpt::Level OptLevel) {
132 const TargetLowering &TLI = IS->getTargetLowering();
134 if (OptLevel == CodeGenOpt::None)
135 return createFastDAGScheduler(IS, OptLevel);
136 if (TLI.getSchedulingPreference() == Sched::Latency)
137 return createTDListDAGScheduler(IS, OptLevel);
138 if (TLI.getSchedulingPreference() == Sched::RegPressure)
139 return createBURRListDAGScheduler(IS, OptLevel);
140 assert(TLI.getSchedulingPreference() == Sched::Hybrid &&
141 "Unknown sched type!");
142 return createHybridListDAGScheduler(IS, OptLevel);
146 // EmitInstrWithCustomInserter - This method should be implemented by targets
147 // that mark instructions with the 'usesCustomInserter' flag. These
148 // instructions are special in various ways, which require special support to
149 // insert. The specified MachineInstr is created but not inserted into any
150 // basic blocks, and this method is called to expand it into a sequence of
151 // instructions, potentially also creating new basic blocks and control flow.
152 // When new basic blocks are inserted and the edges from MBB to its successors
153 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
156 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
157 MachineBasicBlock *MBB) const {
159 dbgs() << "If a target marks an instruction with "
160 "'usesCustomInserter', it must implement "
161 "TargetLowering::EmitInstrWithCustomInserter!";
167 //===----------------------------------------------------------------------===//
168 // SelectionDAGISel code
169 //===----------------------------------------------------------------------===//
171 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, CodeGenOpt::Level OL) :
172 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
173 FuncInfo(new FunctionLoweringInfo(TLI)),
174 CurDAG(new SelectionDAG(tm)),
175 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
181 SelectionDAGISel::~SelectionDAGISel() {
187 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
188 AU.addRequired<AliasAnalysis>();
189 AU.addPreserved<AliasAnalysis>();
190 AU.addRequired<GCModuleInfo>();
191 AU.addPreserved<GCModuleInfo>();
192 MachineFunctionPass::getAnalysisUsage(AU);
195 /// FunctionCallsSetJmp - Return true if the function has a call to setjmp or
196 /// other function that gcc recognizes as "returning twice". This is used to
197 /// limit code-gen optimizations on the machine function.
199 /// FIXME: Remove after <rdar://problem/8031714> is fixed.
200 static bool FunctionCallsSetJmp(const Function *F) {
201 const Module *M = F->getParent();
202 static const char *ReturnsTwiceFns[] = {
211 #define NUM_RETURNS_TWICE_FNS sizeof(ReturnsTwiceFns) / sizeof(const char *)
213 for (unsigned I = 0; I < NUM_RETURNS_TWICE_FNS; ++I)
214 if (const Function *Callee = M->getFunction(ReturnsTwiceFns[I])) {
215 if (!Callee->use_empty())
216 for (Value::const_use_iterator
217 I = Callee->use_begin(), E = Callee->use_end();
219 if (const CallInst *CI = dyn_cast<CallInst>(I))
220 if (CI->getParent()->getParent() == F)
225 #undef NUM_RETURNS_TWICE_FNS
228 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
229 // Do some sanity-checking on the command-line options.
230 assert((!EnableFastISelVerbose || EnableFastISel) &&
231 "-fast-isel-verbose requires -fast-isel");
232 assert((!EnableFastISelAbort || EnableFastISel) &&
233 "-fast-isel-abort requires -fast-isel");
235 const Function &Fn = *mf.getFunction();
236 const TargetInstrInfo &TII = *TM.getInstrInfo();
237 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
240 RegInfo = &MF->getRegInfo();
241 AA = &getAnalysis<AliasAnalysis>();
242 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
244 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
247 FuncInfo->set(Fn, *MF);
250 SelectAllBasicBlocks(Fn);
252 // If the first basic block in the function has live ins that need to be
253 // copied into vregs, emit the copies into the top of the block before
254 // emitting the code for the block.
255 MachineBasicBlock *EntryMBB = MF->begin();
256 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
258 DenseMap<unsigned, unsigned> LiveInMap;
259 if (!FuncInfo->ArgDbgValues.empty())
260 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
261 E = RegInfo->livein_end(); LI != E; ++LI)
263 LiveInMap.insert(std::make_pair(LI->first, LI->second));
265 // Insert DBG_VALUE instructions for function arguments to the entry block.
266 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
267 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
268 unsigned Reg = MI->getOperand(0).getReg();
269 if (TargetRegisterInfo::isPhysicalRegister(Reg))
270 EntryMBB->insert(EntryMBB->begin(), MI);
272 MachineInstr *Def = RegInfo->getVRegDef(Reg);
273 MachineBasicBlock::iterator InsertPos = Def;
274 // FIXME: VR def may not be in entry block.
275 Def->getParent()->insert(llvm::next(InsertPos), MI);
278 // If Reg is live-in then update debug info to track its copy in a vreg.
279 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
280 if (LDI != LiveInMap.end()) {
281 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
282 MachineBasicBlock::iterator InsertPos = Def;
283 const MDNode *Variable =
284 MI->getOperand(MI->getNumOperands()-1).getMetadata();
285 unsigned Offset = MI->getOperand(1).getImm();
286 // Def is never a terminator here, so it is ok to increment InsertPos.
287 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
288 TII.get(TargetOpcode::DBG_VALUE))
289 .addReg(LDI->second, RegState::Debug)
290 .addImm(Offset).addMetadata(Variable);
294 // Determine if there are any calls in this machine function.
295 MachineFrameInfo *MFI = MF->getFrameInfo();
296 if (!MFI->hasCalls()) {
297 for (MachineFunction::const_iterator
298 I = MF->begin(), E = MF->end(); I != E; ++I) {
299 const MachineBasicBlock *MBB = I;
300 for (MachineBasicBlock::const_iterator
301 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
302 const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode());
303 if (II->isInlineAsm() || (TID.isCall() && !TID.isReturn())) {
304 MFI->setHasCalls(true);
312 // Determine if there is a call to setjmp in the machine function.
313 MF->setCallsSetJmp(FunctionCallsSetJmp(&Fn));
315 // Release function-specific state. SDB and CurDAG are already cleared
323 SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
324 BasicBlock::const_iterator End,
326 // Lower all of the non-terminator instructions. If a call is emitted
327 // as a tail call, cease emitting nodes for this block. Terminators
328 // are handled below.
329 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
332 // Make sure the root of the DAG is up-to-date.
333 CurDAG->setRoot(SDB->getControlRoot());
334 HadTailCall = SDB->HasTailCall;
337 // Final step, emit the lowered DAG as machine code.
342 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
343 /// nodes from the worklist.
344 class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener {
345 SmallVector<SDNode*, 128> &Worklist;
346 SmallPtrSet<SDNode*, 128> &InWorklist;
348 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl,
349 SmallPtrSet<SDNode*, 128> &inwl)
350 : Worklist(wl), InWorklist(inwl) {}
352 void RemoveFromWorklist(SDNode *N) {
353 if (!InWorklist.erase(N)) return;
355 SmallVector<SDNode*, 128>::iterator I =
356 std::find(Worklist.begin(), Worklist.end(), N);
357 assert(I != Worklist.end() && "Not in worklist");
359 *I = Worklist.back();
363 virtual void NodeDeleted(SDNode *N, SDNode *E) {
364 RemoveFromWorklist(N);
367 virtual void NodeUpdated(SDNode *N) {
373 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
374 SmallPtrSet<SDNode*, 128> VisitedNodes;
375 SmallVector<SDNode*, 128> Worklist;
377 Worklist.push_back(CurDAG->getRoot().getNode());
384 SDNode *N = Worklist.pop_back_val();
386 // If we've already seen this node, ignore it.
387 if (!VisitedNodes.insert(N))
390 // Otherwise, add all chain operands to the worklist.
391 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
392 if (N->getOperand(i).getValueType() == MVT::Other)
393 Worklist.push_back(N->getOperand(i).getNode());
395 // If this is a CopyToReg with a vreg dest, process it.
396 if (N->getOpcode() != ISD::CopyToReg)
399 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
400 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
403 // Ignore non-scalar or non-integer values.
404 SDValue Src = N->getOperand(2);
405 EVT SrcVT = Src.getValueType();
406 if (!SrcVT.isInteger() || SrcVT.isVector())
409 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
410 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
411 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
413 // Only install this information if it tells us something.
414 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
415 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
416 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
417 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
418 FunctionLoweringInfo::LiveOutInfo &LOI =
419 FuncInfo->LiveOutRegInfo[DestReg];
420 LOI.NumSignBits = NumSignBits;
421 LOI.KnownOne = KnownOne;
422 LOI.KnownZero = KnownZero;
424 } while (!Worklist.empty());
427 void SelectionDAGISel::CodeGenAndEmitDAG() {
428 std::string GroupName;
429 if (TimePassesIsEnabled)
430 GroupName = "Instruction Selection and Scheduling";
431 std::string BlockName;
432 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
433 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
435 BlockName = MF->getFunction()->getNameStr() + ":" +
436 FuncInfo->MBB->getBasicBlock()->getNameStr();
438 DEBUG(dbgs() << "Initial selection DAG:\n"; CurDAG->dump());
440 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
442 // Run the DAG combiner in pre-legalize mode.
444 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
445 CurDAG->Combine(Unrestricted, *AA, OptLevel);
448 DEBUG(dbgs() << "Optimized lowered selection DAG:\n"; CurDAG->dump());
450 // Second step, hack on the DAG until it only uses operations and types that
451 // the target supports.
452 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
457 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
458 Changed = CurDAG->LegalizeTypes();
461 DEBUG(dbgs() << "Type-legalized selection DAG:\n"; CurDAG->dump());
464 if (ViewDAGCombineLT)
465 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
467 // Run the DAG combiner in post-type-legalize mode.
469 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
470 TimePassesIsEnabled);
471 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
474 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n";
479 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
480 Changed = CurDAG->LegalizeVectors();
485 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
486 CurDAG->LegalizeTypes();
489 if (ViewDAGCombineLT)
490 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
492 // Run the DAG combiner in post-type-legalize mode.
494 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
495 TimePassesIsEnabled);
496 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
499 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n";
503 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
506 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
507 CurDAG->Legalize(OptLevel);
510 DEBUG(dbgs() << "Legalized selection DAG:\n"; CurDAG->dump());
512 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
514 // Run the DAG combiner in post-legalize mode.
516 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
517 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
520 DEBUG(dbgs() << "Optimized legalized selection DAG:\n"; CurDAG->dump());
522 if (OptLevel != CodeGenOpt::None)
523 ComputeLiveOutVRegInfo();
525 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
527 // Third, instruction select all of the operations to machine code, adding the
528 // code to the MachineBasicBlock.
530 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
531 DoInstructionSelection();
534 DEBUG(dbgs() << "Selected selection DAG:\n"; CurDAG->dump());
536 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
538 // Schedule machine code.
539 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
541 NamedRegionTimer T("Instruction Scheduling", GroupName,
542 TimePassesIsEnabled);
543 Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt);
546 if (ViewSUnitDAGs) Scheduler->viewGraph();
548 // Emit machine code to BB. This can change 'BB' to the last block being
551 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
552 FuncInfo->MBB = Scheduler->EmitSchedule();
555 // Free the scheduler state.
557 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
558 TimePassesIsEnabled);
562 // Free the SelectionDAG state, now that we're finished with it.
566 void SelectionDAGISel::DoInstructionSelection() {
567 DEBUG(errs() << "===== Instruction selection begins:\n");
571 // Select target instructions for the DAG.
573 // Number all nodes with a topological order and set DAGSize.
574 DAGSize = CurDAG->AssignTopologicalOrder();
576 // Create a dummy node (which is not added to allnodes), that adds
577 // a reference to the root node, preventing it from being deleted,
578 // and tracking any changes of the root.
579 HandleSDNode Dummy(CurDAG->getRoot());
580 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
583 // The AllNodes list is now topological-sorted. Visit the
584 // nodes by starting at the end of the list (the root of the
585 // graph) and preceding back toward the beginning (the entry
587 while (ISelPosition != CurDAG->allnodes_begin()) {
588 SDNode *Node = --ISelPosition;
589 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
590 // but there are currently some corner cases that it misses. Also, this
591 // makes it theoretically possible to disable the DAGCombiner.
592 if (Node->use_empty())
595 SDNode *ResNode = Select(Node);
597 // FIXME: This is pretty gross. 'Select' should be changed to not return
598 // anything at all and this code should be nuked with a tactical strike.
600 // If node should not be replaced, continue with the next one.
601 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
605 ReplaceUses(Node, ResNode);
607 // If after the replacement this node is not used any more,
608 // remove this dead node.
609 if (Node->use_empty()) { // Don't delete EntryToken, etc.
610 ISelUpdater ISU(ISelPosition);
611 CurDAG->RemoveDeadNode(Node, &ISU);
615 CurDAG->setRoot(Dummy.getValue());
618 DEBUG(errs() << "===== Instruction selection ends:\n");
620 PostprocessISelDAG();
623 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
624 /// do other setup for EH landing-pad blocks.
625 void SelectionDAGISel::PrepareEHLandingPad() {
626 // Add a label to mark the beginning of the landing pad. Deletion of the
627 // landing pad can thus be detected via the MachineModuleInfo.
628 MCSymbol *Label = MF->getMMI().addLandingPad(FuncInfo->MBB);
630 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
631 BuildMI(*FuncInfo->MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
634 // Mark exception register as live in.
635 unsigned Reg = TLI.getExceptionAddressRegister();
636 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
638 // Mark exception selector register as live in.
639 Reg = TLI.getExceptionSelectorRegister();
640 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
642 // FIXME: Hack around an exception handling flaw (PR1508): the personality
643 // function and list of typeids logically belong to the invoke (or, if you
644 // like, the basic block containing the invoke), and need to be associated
645 // with it in the dwarf exception handling tables. Currently however the
646 // information is provided by an intrinsic (eh.selector) that can be moved
647 // to unexpected places by the optimizers: if the unwind edge is critical,
648 // then breaking it can result in the intrinsics being in the successor of
649 // the landing pad, not the landing pad itself. This results
650 // in exceptions not being caught because no typeids are associated with
651 // the invoke. This may not be the only way things can go wrong, but it
652 // is the only way we try to work around for the moment.
653 const BasicBlock *LLVMBB = FuncInfo->MBB->getBasicBlock();
654 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
656 if (Br && Br->isUnconditional()) { // Critical edge?
657 BasicBlock::const_iterator I, E;
658 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
659 if (isa<EHSelectorInst>(I))
663 // No catch info found - try to extract some from the successor.
664 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
668 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
669 // Initialize the Fast-ISel state, if needed.
670 FastISel *FastIS = 0;
672 FastIS = TLI.createFastISel(*FuncInfo);
674 // Iterate over all basic blocks in the function.
675 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
676 const BasicBlock *LLVMBB = &*I;
677 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
678 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
680 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
681 BasicBlock::const_iterator const End = LLVMBB->end();
682 BasicBlock::const_iterator BI = Begin;
684 // Lower any arguments needed in this block if this is the entry block.
685 if (LLVMBB == &Fn.getEntryBlock())
686 LowerArguments(LLVMBB);
688 // Setup an EH landing-pad block.
689 if (FuncInfo->MBB->isLandingPad())
690 PrepareEHLandingPad();
692 // Before doing SelectionDAG ISel, see if FastISel has been requested.
694 // Emit code for any incoming arguments. This must happen before
695 // beginning FastISel on the entry block.
696 if (LLVMBB == &Fn.getEntryBlock()) {
697 CurDAG->setRoot(SDB->getControlRoot());
701 FastIS->startNewBlock();
702 // Do FastISel on as many instructions as possible.
703 for (; BI != End; ++BI) {
705 // Defer instructions with no side effects; they'll be emitted
707 if (BI->isSafeToSpeculativelyExecute() &&
708 !FuncInfo->isExportedInst(BI))
712 // Try to select the instruction with FastISel.
713 if (FastIS->SelectInstruction(BI))
716 // Then handle certain instructions as single-LLVM-Instruction blocks.
717 if (isa<CallInst>(BI)) {
718 ++NumFastIselFailures;
719 if (EnableFastISelVerbose || EnableFastISelAbort) {
720 dbgs() << "FastISel missed call: ";
724 if (!BI->getType()->isVoidTy() && !BI->use_empty()) {
725 unsigned &R = FuncInfo->ValueMap[BI];
727 R = FuncInfo->CreateRegs(BI->getType());
730 bool HadTailCall = false;
731 SelectBasicBlock(BI, llvm::next(BI), HadTailCall);
733 // If the call was emitted as a tail call, we're done with the block.
742 // Otherwise, give up on FastISel for the rest of the block.
743 // For now, be a little lenient about non-branch terminators.
744 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
745 ++NumFastIselFailures;
746 if (EnableFastISelVerbose || EnableFastISelAbort) {
747 dbgs() << "FastISel miss: ";
750 if (EnableFastISelAbort)
751 // The "fast" selector couldn't handle something and bailed.
752 // For the purpose of debugging, just abort.
753 llvm_unreachable("FastISel didn't select the entire block");
759 // Run SelectionDAG instruction selection on the remainder of the block
760 // not handled by FastISel. If FastISel is not run, this is the entire
764 SelectBasicBlock(BI, End, HadTailCall);
768 FuncInfo->PHINodesToUpdate.clear();
775 SelectionDAGISel::FinishBasicBlock() {
777 DEBUG(dbgs() << "Total amount of phi nodes to update: "
778 << FuncInfo->PHINodesToUpdate.size() << "\n";
779 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
780 dbgs() << "Node " << i << " : ("
781 << FuncInfo->PHINodesToUpdate[i].first
782 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
784 // Next, now that we know what the last MBB the LLVM BB expanded is, update
785 // PHI nodes in successors.
786 if (SDB->SwitchCases.empty() &&
787 SDB->JTCases.empty() &&
788 SDB->BitTestCases.empty()) {
789 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
790 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
791 assert(PHI->isPHI() &&
792 "This is not a machine PHI node that we are updating!");
793 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
796 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
797 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
802 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
803 // Lower header first, if it wasn't already lowered
804 if (!SDB->BitTestCases[i].Emitted) {
805 // Set the current basic block to the mbb we wish to insert the code into
806 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
807 FuncInfo->InsertPt = FuncInfo->MBB->end();
809 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
810 CurDAG->setRoot(SDB->getRoot());
815 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
816 // Set the current basic block to the mbb we wish to insert the code into
817 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
818 FuncInfo->InsertPt = FuncInfo->MBB->end();
821 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
822 SDB->BitTestCases[i].Reg,
823 SDB->BitTestCases[i].Cases[j],
826 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
827 SDB->BitTestCases[i].Reg,
828 SDB->BitTestCases[i].Cases[j],
832 CurDAG->setRoot(SDB->getRoot());
838 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
840 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
841 MachineBasicBlock *PHIBB = PHI->getParent();
842 assert(PHI->isPHI() &&
843 "This is not a machine PHI node that we are updating!");
844 // This is "default" BB. We have two jumps to it. From "header" BB and
845 // from last "case" BB.
846 if (PHIBB == SDB->BitTestCases[i].Default) {
847 PHI->addOperand(MachineOperand::
848 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
850 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
851 PHI->addOperand(MachineOperand::
852 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
854 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
857 // One of "cases" BB.
858 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
860 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
861 if (cBB->isSuccessor(PHIBB)) {
862 PHI->addOperand(MachineOperand::
863 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
865 PHI->addOperand(MachineOperand::CreateMBB(cBB));
870 SDB->BitTestCases.clear();
872 // If the JumpTable record is filled in, then we need to emit a jump table.
873 // Updating the PHI nodes is tricky in this case, since we need to determine
874 // whether the PHI is a successor of the range check MBB or the jump table MBB
875 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
876 // Lower header first, if it wasn't already lowered
877 if (!SDB->JTCases[i].first.Emitted) {
878 // Set the current basic block to the mbb we wish to insert the code into
879 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
880 FuncInfo->InsertPt = FuncInfo->MBB->end();
882 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
884 CurDAG->setRoot(SDB->getRoot());
889 // Set the current basic block to the mbb we wish to insert the code into
890 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
891 FuncInfo->InsertPt = FuncInfo->MBB->end();
893 SDB->visitJumpTable(SDB->JTCases[i].second);
894 CurDAG->setRoot(SDB->getRoot());
899 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
901 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
902 MachineBasicBlock *PHIBB = PHI->getParent();
903 assert(PHI->isPHI() &&
904 "This is not a machine PHI node that we are updating!");
905 // "default" BB. We can go there only from header BB.
906 if (PHIBB == SDB->JTCases[i].second.Default) {
908 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
911 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
913 // JT BB. Just iterate over successors here
914 if (FuncInfo->MBB->isSuccessor(PHIBB)) {
916 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
918 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
922 SDB->JTCases.clear();
924 // If the switch block involved a branch to one of the actual successors, we
925 // need to update PHI nodes in that block.
926 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
927 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
928 assert(PHI->isPHI() &&
929 "This is not a machine PHI node that we are updating!");
930 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) {
932 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
933 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
937 // If we generated any switch lowering information, build and codegen any
938 // additional DAGs necessary.
939 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
940 // Set the current basic block to the mbb we wish to insert the code into
941 MachineBasicBlock *ThisBB = FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
942 FuncInfo->InsertPt = FuncInfo->MBB->end();
944 // Determine the unique successors.
945 SmallVector<MachineBasicBlock *, 2> Succs;
946 Succs.push_back(SDB->SwitchCases[i].TrueBB);
947 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
948 Succs.push_back(SDB->SwitchCases[i].FalseBB);
950 // Emit the code. Note that this could result in ThisBB being split, so
951 // we need to check for updates.
952 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
953 CurDAG->setRoot(SDB->getRoot());
956 ThisBB = FuncInfo->MBB;
958 // Handle any PHI nodes in successors of this chunk, as if we were coming
959 // from the original BB before switch expansion. Note that PHI nodes can
960 // occur multiple times in PHINodesToUpdate. We have to be very careful to
961 // handle them the right number of times.
962 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
963 FuncInfo->MBB = Succs[i];
964 FuncInfo->InsertPt = FuncInfo->MBB->end();
965 // BB may have been removed from the CFG if a branch was constant folded.
966 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
967 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin();
968 Phi != FuncInfo->MBB->end() && Phi->isPHI();
970 // This value for this PHI node is recorded in PHINodesToUpdate.
971 for (unsigned pn = 0; ; ++pn) {
972 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
973 "Didn't find PHI entry!");
974 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) {
975 Phi->addOperand(MachineOperand::
976 CreateReg(FuncInfo->PHINodesToUpdate[pn].second,
978 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
986 SDB->SwitchCases.clear();
990 /// Create the scheduler. If a specific scheduler was specified
991 /// via the SchedulerRegistry, use it, otherwise select the
992 /// one preferred by the target.
994 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
995 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
999 RegisterScheduler::setDefault(Ctor);
1002 return Ctor(this, OptLevel);
1005 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1006 return new ScheduleHazardRecognizer();
1009 //===----------------------------------------------------------------------===//
1010 // Helper functions used by the generated instruction selector.
1011 //===----------------------------------------------------------------------===//
1012 // Calls to these methods are generated by tblgen.
1014 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1015 /// the dag combiner simplified the 255, we still want to match. RHS is the
1016 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1017 /// specified in the .td file (e.g. 255).
1018 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1019 int64_t DesiredMaskS) const {
1020 const APInt &ActualMask = RHS->getAPIntValue();
1021 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1023 // If the actual mask exactly matches, success!
1024 if (ActualMask == DesiredMask)
1027 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1028 if (ActualMask.intersects(~DesiredMask))
1031 // Otherwise, the DAG Combiner may have proven that the value coming in is
1032 // either already zero or is not demanded. Check for known zero input bits.
1033 APInt NeededMask = DesiredMask & ~ActualMask;
1034 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1037 // TODO: check to see if missing bits are just not demanded.
1039 // Otherwise, this pattern doesn't match.
1043 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1044 /// the dag combiner simplified the 255, we still want to match. RHS is the
1045 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1046 /// specified in the .td file (e.g. 255).
1047 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1048 int64_t DesiredMaskS) const {
1049 const APInt &ActualMask = RHS->getAPIntValue();
1050 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1052 // If the actual mask exactly matches, success!
1053 if (ActualMask == DesiredMask)
1056 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1057 if (ActualMask.intersects(~DesiredMask))
1060 // Otherwise, the DAG Combiner may have proven that the value coming in is
1061 // either already zero or is not demanded. Check for known zero input bits.
1062 APInt NeededMask = DesiredMask & ~ActualMask;
1064 APInt KnownZero, KnownOne;
1065 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1067 // If all the missing bits in the or are already known to be set, match!
1068 if ((NeededMask & KnownOne) == NeededMask)
1071 // TODO: check to see if missing bits are just not demanded.
1073 // Otherwise, this pattern doesn't match.
1078 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1079 /// by tblgen. Others should not call it.
1080 void SelectionDAGISel::
1081 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1082 std::vector<SDValue> InOps;
1083 std::swap(InOps, Ops);
1085 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1086 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1087 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1088 Ops.push_back(InOps[InlineAsm::Op_IsAlignStack]); // 3
1090 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1091 if (InOps[e-1].getValueType() == MVT::Flag)
1092 --e; // Don't process a flag operand if it is here.
1095 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1096 if (!InlineAsm::isMemKind(Flags)) {
1097 // Just skip over this operand, copying the operands verbatim.
1098 Ops.insert(Ops.end(), InOps.begin()+i,
1099 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1100 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1102 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1103 "Memory operand with multiple values?");
1104 // Otherwise, this is a memory operand. Ask the target to select it.
1105 std::vector<SDValue> SelOps;
1106 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1107 report_fatal_error("Could not match memory address. Inline asm"
1110 // Add this to the output node.
1112 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1113 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1114 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1119 // Add the flag input back if present.
1120 if (e != InOps.size())
1121 Ops.push_back(InOps.back());
1124 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1127 static SDNode *findFlagUse(SDNode *N) {
1128 unsigned FlagResNo = N->getNumValues()-1;
1129 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1130 SDUse &Use = I.getUse();
1131 if (Use.getResNo() == FlagResNo)
1132 return Use.getUser();
1137 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1138 /// This function recursively traverses up the operand chain, ignoring
1140 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1141 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1142 bool IgnoreChains) {
1143 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1144 // greater than all of its (recursive) operands. If we scan to a point where
1145 // 'use' is smaller than the node we're scanning for, then we know we will
1148 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1149 // happen because we scan down to newly selected nodes in the case of flag
1151 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1154 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1155 // won't fail if we scan it again.
1156 if (!Visited.insert(Use))
1159 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1160 // Ignore chain uses, they are validated by HandleMergeInputChains.
1161 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1164 SDNode *N = Use->getOperand(i).getNode();
1166 if (Use == ImmedUse || Use == Root)
1167 continue; // We are not looking for immediate use.
1172 // Traverse up the operand chain.
1173 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1179 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1180 /// operand node N of U during instruction selection that starts at Root.
1181 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1182 SDNode *Root) const {
1183 if (OptLevel == CodeGenOpt::None) return false;
1184 return N.hasOneUse();
1187 /// IsLegalToFold - Returns true if the specific operand node N of
1188 /// U can be folded during instruction selection that starts at Root.
1189 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1190 CodeGenOpt::Level OptLevel,
1191 bool IgnoreChains) {
1192 if (OptLevel == CodeGenOpt::None) return false;
1194 // If Root use can somehow reach N through a path that that doesn't contain
1195 // U then folding N would create a cycle. e.g. In the following
1196 // diagram, Root can reach N through X. If N is folded into into Root, then
1197 // X is both a predecessor and a successor of U.
1208 // * indicates nodes to be folded together.
1210 // If Root produces a flag, then it gets (even more) interesting. Since it
1211 // will be "glued" together with its flag use in the scheduler, we need to
1212 // check if it might reach N.
1231 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1232 // (call it Fold), then X is a predecessor of FU and a successor of
1233 // Fold. But since Fold and FU are flagged together, this will create
1234 // a cycle in the scheduling graph.
1236 // If the node has flags, walk down the graph to the "lowest" node in the
1238 EVT VT = Root->getValueType(Root->getNumValues()-1);
1239 while (VT == MVT::Flag) {
1240 SDNode *FU = findFlagUse(Root);
1244 VT = Root->getValueType(Root->getNumValues()-1);
1246 // If our query node has a flag result with a use, we've walked up it. If
1247 // the user (which has already been selected) has a chain or indirectly uses
1248 // the chain, our WalkChainUsers predicate will not consider it. Because of
1249 // this, we cannot ignore chains in this predicate.
1250 IgnoreChains = false;
1254 SmallPtrSet<SDNode*, 16> Visited;
1255 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1258 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1259 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1260 SelectInlineAsmMemoryOperands(Ops);
1262 std::vector<EVT> VTs;
1263 VTs.push_back(MVT::Other);
1264 VTs.push_back(MVT::Flag);
1265 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1266 VTs, &Ops[0], Ops.size());
1268 return New.getNode();
1271 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1272 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1275 /// GetVBR - decode a vbr encoding whose top bit is set.
1276 ALWAYS_INLINE static uint64_t
1277 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1278 assert(Val >= 128 && "Not a VBR");
1279 Val &= 127; // Remove first vbr bit.
1284 NextBits = MatcherTable[Idx++];
1285 Val |= (NextBits&127) << Shift;
1287 } while (NextBits & 128);
1293 /// UpdateChainsAndFlags - When a match is complete, this method updates uses of
1294 /// interior flag and chain results to use the new flag and chain results.
1295 void SelectionDAGISel::
1296 UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
1297 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1299 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched,
1300 bool isMorphNodeTo) {
1301 SmallVector<SDNode*, 4> NowDeadNodes;
1303 ISelUpdater ISU(ISelPosition);
1305 // Now that all the normal results are replaced, we replace the chain and
1306 // flag results if present.
1307 if (!ChainNodesMatched.empty()) {
1308 assert(InputChain.getNode() != 0 &&
1309 "Matched input chains but didn't produce a chain");
1310 // Loop over all of the nodes we matched that produced a chain result.
1311 // Replace all the chain results with the final chain we ended up with.
1312 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1313 SDNode *ChainNode = ChainNodesMatched[i];
1315 // If this node was already deleted, don't look at it.
1316 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1319 // Don't replace the results of the root node if we're doing a
1321 if (ChainNode == NodeToMatch && isMorphNodeTo)
1324 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1325 if (ChainVal.getValueType() == MVT::Flag)
1326 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1327 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1328 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1330 // If the node became dead and we haven't already seen it, delete it.
1331 if (ChainNode->use_empty() &&
1332 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1333 NowDeadNodes.push_back(ChainNode);
1337 // If the result produces a flag, update any flag results in the matched
1338 // pattern with the flag result.
1339 if (InputFlag.getNode() != 0) {
1340 // Handle any interior nodes explicitly marked.
1341 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) {
1342 SDNode *FRN = FlagResultNodesMatched[i];
1344 // If this node was already deleted, don't look at it.
1345 if (FRN->getOpcode() == ISD::DELETED_NODE)
1348 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag &&
1349 "Doesn't have a flag result");
1350 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1353 // If the node became dead and we haven't already seen it, delete it.
1354 if (FRN->use_empty() &&
1355 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1356 NowDeadNodes.push_back(FRN);
1360 if (!NowDeadNodes.empty())
1361 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1363 DEBUG(errs() << "ISEL: Match complete!\n");
1369 CR_LeadsToInteriorNode
1372 /// WalkChainUsers - Walk down the users of the specified chained node that is
1373 /// part of the pattern we're matching, looking at all of the users we find.
1374 /// This determines whether something is an interior node, whether we have a
1375 /// non-pattern node in between two pattern nodes (which prevent folding because
1376 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1377 /// between pattern nodes (in which case the TF becomes part of the pattern).
1379 /// The walk we do here is guaranteed to be small because we quickly get down to
1380 /// already selected nodes "below" us.
1382 WalkChainUsers(SDNode *ChainedNode,
1383 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1384 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1385 ChainResult Result = CR_Simple;
1387 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1388 E = ChainedNode->use_end(); UI != E; ++UI) {
1389 // Make sure the use is of the chain, not some other value we produce.
1390 if (UI.getUse().getValueType() != MVT::Other) continue;
1394 // If we see an already-selected machine node, then we've gone beyond the
1395 // pattern that we're selecting down into the already selected chunk of the
1397 if (User->isMachineOpcode() ||
1398 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1401 if (User->getOpcode() == ISD::CopyToReg ||
1402 User->getOpcode() == ISD::CopyFromReg ||
1403 User->getOpcode() == ISD::INLINEASM ||
1404 User->getOpcode() == ISD::EH_LABEL) {
1405 // If their node ID got reset to -1 then they've already been selected.
1406 // Treat them like a MachineOpcode.
1407 if (User->getNodeId() == -1)
1411 // If we have a TokenFactor, we handle it specially.
1412 if (User->getOpcode() != ISD::TokenFactor) {
1413 // If the node isn't a token factor and isn't part of our pattern, then it
1414 // must be a random chained node in between two nodes we're selecting.
1415 // This happens when we have something like:
1420 // Because we structurally match the load/store as a read/modify/write,
1421 // but the call is chained between them. We cannot fold in this case
1422 // because it would induce a cycle in the graph.
1423 if (!std::count(ChainedNodesInPattern.begin(),
1424 ChainedNodesInPattern.end(), User))
1425 return CR_InducesCycle;
1427 // Otherwise we found a node that is part of our pattern. For example in:
1431 // This would happen when we're scanning down from the load and see the
1432 // store as a user. Record that there is a use of ChainedNode that is
1433 // part of the pattern and keep scanning uses.
1434 Result = CR_LeadsToInteriorNode;
1435 InteriorChainedNodes.push_back(User);
1439 // If we found a TokenFactor, there are two cases to consider: first if the
1440 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1441 // uses of the TF are in our pattern) we just want to ignore it. Second,
1442 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1448 // | \ DAG's like cheese
1451 // [TokenFactor] [Op]
1458 // In this case, the TokenFactor becomes part of our match and we rewrite it
1459 // as a new TokenFactor.
1461 // To distinguish these two cases, do a recursive walk down the uses.
1462 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1464 // If the uses of the TokenFactor are just already-selected nodes, ignore
1465 // it, it is "below" our pattern.
1467 case CR_InducesCycle:
1468 // If the uses of the TokenFactor lead to nodes that are not part of our
1469 // pattern that are not selected, folding would turn this into a cycle,
1471 return CR_InducesCycle;
1472 case CR_LeadsToInteriorNode:
1473 break; // Otherwise, keep processing.
1476 // Okay, we know we're in the interesting interior case. The TokenFactor
1477 // is now going to be considered part of the pattern so that we rewrite its
1478 // uses (it may have uses that are not part of the pattern) with the
1479 // ultimate chain result of the generated code. We will also add its chain
1480 // inputs as inputs to the ultimate TokenFactor we create.
1481 Result = CR_LeadsToInteriorNode;
1482 ChainedNodesInPattern.push_back(User);
1483 InteriorChainedNodes.push_back(User);
1490 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1491 /// operation for when the pattern matched at least one node with a chains. The
1492 /// input vector contains a list of all of the chained nodes that we match. We
1493 /// must determine if this is a valid thing to cover (i.e. matching it won't
1494 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1495 /// be used as the input node chain for the generated nodes.
1497 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1498 SelectionDAG *CurDAG) {
1499 // Walk all of the chained nodes we've matched, recursively scanning down the
1500 // users of the chain result. This adds any TokenFactor nodes that are caught
1501 // in between chained nodes to the chained and interior nodes list.
1502 SmallVector<SDNode*, 3> InteriorChainedNodes;
1503 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1504 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1505 InteriorChainedNodes) == CR_InducesCycle)
1506 return SDValue(); // Would induce a cycle.
1509 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1510 // that we are interested in. Form our input TokenFactor node.
1511 SmallVector<SDValue, 3> InputChains;
1512 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1513 // Add the input chain of this node to the InputChains list (which will be
1514 // the operands of the generated TokenFactor) if it's not an interior node.
1515 SDNode *N = ChainNodesMatched[i];
1516 if (N->getOpcode() != ISD::TokenFactor) {
1517 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1520 // Otherwise, add the input chain.
1521 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1522 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1523 InputChains.push_back(InChain);
1527 // If we have a token factor, we want to add all inputs of the token factor
1528 // that are not part of the pattern we're matching.
1529 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1530 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1531 N->getOperand(op).getNode()))
1532 InputChains.push_back(N->getOperand(op));
1537 if (InputChains.size() == 1)
1538 return InputChains[0];
1539 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1540 MVT::Other, &InputChains[0], InputChains.size());
1543 /// MorphNode - Handle morphing a node in place for the selector.
1544 SDNode *SelectionDAGISel::
1545 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1546 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1547 // It is possible we're using MorphNodeTo to replace a node with no
1548 // normal results with one that has a normal result (or we could be
1549 // adding a chain) and the input could have flags and chains as well.
1550 // In this case we need to shift the operands down.
1551 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1552 // than the old isel though.
1553 int OldFlagResultNo = -1, OldChainResultNo = -1;
1555 unsigned NTMNumResults = Node->getNumValues();
1556 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) {
1557 OldFlagResultNo = NTMNumResults-1;
1558 if (NTMNumResults != 1 &&
1559 Node->getValueType(NTMNumResults-2) == MVT::Other)
1560 OldChainResultNo = NTMNumResults-2;
1561 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1562 OldChainResultNo = NTMNumResults-1;
1564 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1565 // that this deletes operands of the old node that become dead.
1566 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1568 // MorphNodeTo can operate in two ways: if an existing node with the
1569 // specified operands exists, it can just return it. Otherwise, it
1570 // updates the node in place to have the requested operands.
1572 // If we updated the node in place, reset the node ID. To the isel,
1573 // this should be just like a newly allocated machine node.
1577 unsigned ResNumResults = Res->getNumValues();
1578 // Move the flag if needed.
1579 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 &&
1580 (unsigned)OldFlagResultNo != ResNumResults-1)
1581 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo),
1582 SDValue(Res, ResNumResults-1));
1584 if ((EmitNodeInfo & OPFL_FlagOutput) != 0)
1587 // Move the chain reference if needed.
1588 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1589 (unsigned)OldChainResultNo != ResNumResults-1)
1590 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1591 SDValue(Res, ResNumResults-1));
1593 // Otherwise, no replacement happened because the node already exists. Replace
1594 // Uses of the old node with the new one.
1596 CurDAG->ReplaceAllUsesWith(Node, Res);
1601 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1602 ALWAYS_INLINE static bool
1603 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1604 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) {
1605 // Accept if it is exactly the same as a previously recorded node.
1606 unsigned RecNo = MatcherTable[MatcherIndex++];
1607 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1608 return N == RecordedNodes[RecNo];
1611 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1612 ALWAYS_INLINE static bool
1613 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1614 SelectionDAGISel &SDISel) {
1615 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1618 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1619 ALWAYS_INLINE static bool
1620 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1621 SelectionDAGISel &SDISel, SDNode *N) {
1622 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1625 ALWAYS_INLINE static bool
1626 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1628 uint16_t Opc = MatcherTable[MatcherIndex++];
1629 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1630 return N->getOpcode() == Opc;
1633 ALWAYS_INLINE static bool
1634 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1635 SDValue N, const TargetLowering &TLI) {
1636 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1637 if (N.getValueType() == VT) return true;
1639 // Handle the case when VT is iPTR.
1640 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1643 ALWAYS_INLINE static bool
1644 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1645 SDValue N, const TargetLowering &TLI,
1647 if (ChildNo >= N.getNumOperands())
1648 return false; // Match fails if out of range child #.
1649 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1653 ALWAYS_INLINE static bool
1654 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1656 return cast<CondCodeSDNode>(N)->get() ==
1657 (ISD::CondCode)MatcherTable[MatcherIndex++];
1660 ALWAYS_INLINE static bool
1661 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1662 SDValue N, const TargetLowering &TLI) {
1663 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1664 if (cast<VTSDNode>(N)->getVT() == VT)
1667 // Handle the case when VT is iPTR.
1668 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1671 ALWAYS_INLINE static bool
1672 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1674 int64_t Val = MatcherTable[MatcherIndex++];
1676 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1678 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1679 return C != 0 && C->getSExtValue() == Val;
1682 ALWAYS_INLINE static bool
1683 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1684 SDValue N, SelectionDAGISel &SDISel) {
1685 int64_t Val = MatcherTable[MatcherIndex++];
1687 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1689 if (N->getOpcode() != ISD::AND) return false;
1691 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1692 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1695 ALWAYS_INLINE static bool
1696 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1697 SDValue N, SelectionDAGISel &SDISel) {
1698 int64_t Val = MatcherTable[MatcherIndex++];
1700 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1702 if (N->getOpcode() != ISD::OR) return false;
1704 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1705 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1708 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1709 /// scope, evaluate the current node. If the current predicate is known to
1710 /// fail, set Result=true and return anything. If the current predicate is
1711 /// known to pass, set Result=false and return the MatcherIndex to continue
1712 /// with. If the current predicate is unknown, set Result=false and return the
1713 /// MatcherIndex to continue with.
1714 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1715 unsigned Index, SDValue N,
1716 bool &Result, SelectionDAGISel &SDISel,
1717 SmallVectorImpl<SDValue> &RecordedNodes){
1718 switch (Table[Index++]) {
1721 return Index-1; // Could not evaluate this predicate.
1722 case SelectionDAGISel::OPC_CheckSame:
1723 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1725 case SelectionDAGISel::OPC_CheckPatternPredicate:
1726 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1728 case SelectionDAGISel::OPC_CheckPredicate:
1729 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1731 case SelectionDAGISel::OPC_CheckOpcode:
1732 Result = !::CheckOpcode(Table, Index, N.getNode());
1734 case SelectionDAGISel::OPC_CheckType:
1735 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1737 case SelectionDAGISel::OPC_CheckChild0Type:
1738 case SelectionDAGISel::OPC_CheckChild1Type:
1739 case SelectionDAGISel::OPC_CheckChild2Type:
1740 case SelectionDAGISel::OPC_CheckChild3Type:
1741 case SelectionDAGISel::OPC_CheckChild4Type:
1742 case SelectionDAGISel::OPC_CheckChild5Type:
1743 case SelectionDAGISel::OPC_CheckChild6Type:
1744 case SelectionDAGISel::OPC_CheckChild7Type:
1745 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1746 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1748 case SelectionDAGISel::OPC_CheckCondCode:
1749 Result = !::CheckCondCode(Table, Index, N);
1751 case SelectionDAGISel::OPC_CheckValueType:
1752 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
1754 case SelectionDAGISel::OPC_CheckInteger:
1755 Result = !::CheckInteger(Table, Index, N);
1757 case SelectionDAGISel::OPC_CheckAndImm:
1758 Result = !::CheckAndImm(Table, Index, N, SDISel);
1760 case SelectionDAGISel::OPC_CheckOrImm:
1761 Result = !::CheckOrImm(Table, Index, N, SDISel);
1769 /// FailIndex - If this match fails, this is the index to continue with.
1772 /// NodeStack - The node stack when the scope was formed.
1773 SmallVector<SDValue, 4> NodeStack;
1775 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
1776 unsigned NumRecordedNodes;
1778 /// NumMatchedMemRefs - The number of matched memref entries.
1779 unsigned NumMatchedMemRefs;
1781 /// InputChain/InputFlag - The current chain/flag
1782 SDValue InputChain, InputFlag;
1784 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
1785 bool HasChainNodesMatched, HasFlagResultNodesMatched;
1790 SDNode *SelectionDAGISel::
1791 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
1792 unsigned TableSize) {
1793 // FIXME: Should these even be selected? Handle these cases in the caller?
1794 switch (NodeToMatch->getOpcode()) {
1797 case ISD::EntryToken: // These nodes remain the same.
1798 case ISD::BasicBlock:
1800 //case ISD::VALUETYPE:
1801 //case ISD::CONDCODE:
1802 case ISD::HANDLENODE:
1803 case ISD::MDNODE_SDNODE:
1804 case ISD::TargetConstant:
1805 case ISD::TargetConstantFP:
1806 case ISD::TargetConstantPool:
1807 case ISD::TargetFrameIndex:
1808 case ISD::TargetExternalSymbol:
1809 case ISD::TargetBlockAddress:
1810 case ISD::TargetJumpTable:
1811 case ISD::TargetGlobalTLSAddress:
1812 case ISD::TargetGlobalAddress:
1813 case ISD::TokenFactor:
1814 case ISD::CopyFromReg:
1815 case ISD::CopyToReg:
1817 NodeToMatch->setNodeId(-1); // Mark selected.
1819 case ISD::AssertSext:
1820 case ISD::AssertZext:
1821 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
1822 NodeToMatch->getOperand(0));
1824 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
1825 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
1828 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
1830 // Set up the node stack with NodeToMatch as the only node on the stack.
1831 SmallVector<SDValue, 8> NodeStack;
1832 SDValue N = SDValue(NodeToMatch, 0);
1833 NodeStack.push_back(N);
1835 // MatchScopes - Scopes used when matching, if a match failure happens, this
1836 // indicates where to continue checking.
1837 SmallVector<MatchScope, 8> MatchScopes;
1839 // RecordedNodes - This is the set of nodes that have been recorded by the
1841 SmallVector<SDValue, 8> RecordedNodes;
1843 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
1845 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
1847 // These are the current input chain and flag for use when generating nodes.
1848 // Various Emit operations change these. For example, emitting a copytoreg
1849 // uses and updates these.
1850 SDValue InputChain, InputFlag;
1852 // ChainNodesMatched - If a pattern matches nodes that have input/output
1853 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
1854 // which ones they are. The result is captured into this list so that we can
1855 // update the chain results when the pattern is complete.
1856 SmallVector<SDNode*, 3> ChainNodesMatched;
1857 SmallVector<SDNode*, 3> FlagResultNodesMatched;
1859 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
1860 NodeToMatch->dump(CurDAG);
1863 // Determine where to start the interpreter. Normally we start at opcode #0,
1864 // but if the state machine starts with an OPC_SwitchOpcode, then we
1865 // accelerate the first lookup (which is guaranteed to be hot) with the
1866 // OpcodeOffset table.
1867 unsigned MatcherIndex = 0;
1869 if (!OpcodeOffset.empty()) {
1870 // Already computed the OpcodeOffset table, just index into it.
1871 if (N.getOpcode() < OpcodeOffset.size())
1872 MatcherIndex = OpcodeOffset[N.getOpcode()];
1873 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
1875 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
1876 // Otherwise, the table isn't computed, but the state machine does start
1877 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
1878 // is the first time we're selecting an instruction.
1881 // Get the size of this case.
1882 unsigned CaseSize = MatcherTable[Idx++];
1884 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
1885 if (CaseSize == 0) break;
1887 // Get the opcode, add the index to the table.
1888 uint16_t Opc = MatcherTable[Idx++];
1889 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
1890 if (Opc >= OpcodeOffset.size())
1891 OpcodeOffset.resize((Opc+1)*2);
1892 OpcodeOffset[Opc] = Idx;
1896 // Okay, do the lookup for the first opcode.
1897 if (N.getOpcode() < OpcodeOffset.size())
1898 MatcherIndex = OpcodeOffset[N.getOpcode()];
1902 assert(MatcherIndex < TableSize && "Invalid index");
1904 unsigned CurrentOpcodeIndex = MatcherIndex;
1906 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
1909 // Okay, the semantics of this operation are that we should push a scope
1910 // then evaluate the first child. However, pushing a scope only to have
1911 // the first check fail (which then pops it) is inefficient. If we can
1912 // determine immediately that the first check (or first several) will
1913 // immediately fail, don't even bother pushing a scope for them.
1917 unsigned NumToSkip = MatcherTable[MatcherIndex++];
1918 if (NumToSkip & 128)
1919 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
1920 // Found the end of the scope with no match.
1921 if (NumToSkip == 0) {
1926 FailIndex = MatcherIndex+NumToSkip;
1928 unsigned MatcherIndexOfPredicate = MatcherIndex;
1929 (void)MatcherIndexOfPredicate; // silence warning.
1931 // If we can't evaluate this predicate without pushing a scope (e.g. if
1932 // it is a 'MoveParent') or if the predicate succeeds on this node, we
1933 // push the scope and evaluate the full predicate chain.
1935 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
1936 Result, *this, RecordedNodes);
1940 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
1941 << "index " << MatcherIndexOfPredicate
1942 << ", continuing at " << FailIndex << "\n");
1943 ++NumDAGIselRetries;
1945 // Otherwise, we know that this case of the Scope is guaranteed to fail,
1946 // move to the next case.
1947 MatcherIndex = FailIndex;
1950 // If the whole scope failed to match, bail.
1951 if (FailIndex == 0) break;
1953 // Push a MatchScope which indicates where to go if the first child fails
1955 MatchScope NewEntry;
1956 NewEntry.FailIndex = FailIndex;
1957 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
1958 NewEntry.NumRecordedNodes = RecordedNodes.size();
1959 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
1960 NewEntry.InputChain = InputChain;
1961 NewEntry.InputFlag = InputFlag;
1962 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
1963 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty();
1964 MatchScopes.push_back(NewEntry);
1967 case OPC_RecordNode:
1968 // Remember this node, it may end up being an operand in the pattern.
1969 RecordedNodes.push_back(N);
1972 case OPC_RecordChild0: case OPC_RecordChild1:
1973 case OPC_RecordChild2: case OPC_RecordChild3:
1974 case OPC_RecordChild4: case OPC_RecordChild5:
1975 case OPC_RecordChild6: case OPC_RecordChild7: {
1976 unsigned ChildNo = Opcode-OPC_RecordChild0;
1977 if (ChildNo >= N.getNumOperands())
1978 break; // Match fails if out of range child #.
1980 RecordedNodes.push_back(N->getOperand(ChildNo));
1983 case OPC_RecordMemRef:
1984 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
1987 case OPC_CaptureFlagInput:
1988 // If the current node has an input flag, capture it in InputFlag.
1989 if (N->getNumOperands() != 0 &&
1990 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag)
1991 InputFlag = N->getOperand(N->getNumOperands()-1);
1994 case OPC_MoveChild: {
1995 unsigned ChildNo = MatcherTable[MatcherIndex++];
1996 if (ChildNo >= N.getNumOperands())
1997 break; // Match fails if out of range child #.
1998 N = N.getOperand(ChildNo);
1999 NodeStack.push_back(N);
2003 case OPC_MoveParent:
2004 // Pop the current node off the NodeStack.
2005 NodeStack.pop_back();
2006 assert(!NodeStack.empty() && "Node stack imbalance!");
2007 N = NodeStack.back();
2011 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2013 case OPC_CheckPatternPredicate:
2014 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2016 case OPC_CheckPredicate:
2017 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2021 case OPC_CheckComplexPat: {
2022 unsigned CPNum = MatcherTable[MatcherIndex++];
2023 unsigned RecNo = MatcherTable[MatcherIndex++];
2024 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2025 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum,
2030 case OPC_CheckOpcode:
2031 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2035 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2038 case OPC_SwitchOpcode: {
2039 unsigned CurNodeOpcode = N.getOpcode();
2040 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2043 // Get the size of this case.
2044 CaseSize = MatcherTable[MatcherIndex++];
2046 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2047 if (CaseSize == 0) break;
2049 uint16_t Opc = MatcherTable[MatcherIndex++];
2050 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2052 // If the opcode matches, then we will execute this case.
2053 if (CurNodeOpcode == Opc)
2056 // Otherwise, skip over this case.
2057 MatcherIndex += CaseSize;
2060 // If no cases matched, bail out.
2061 if (CaseSize == 0) break;
2063 // Otherwise, execute the case we found.
2064 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2065 << " to " << MatcherIndex << "\n");
2069 case OPC_SwitchType: {
2070 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy;
2071 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2074 // Get the size of this case.
2075 CaseSize = MatcherTable[MatcherIndex++];
2077 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2078 if (CaseSize == 0) break;
2080 MVT::SimpleValueType CaseVT =
2081 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2082 if (CaseVT == MVT::iPTR)
2083 CaseVT = TLI.getPointerTy().SimpleTy;
2085 // If the VT matches, then we will execute this case.
2086 if (CurNodeVT == CaseVT)
2089 // Otherwise, skip over this case.
2090 MatcherIndex += CaseSize;
2093 // If no cases matched, bail out.
2094 if (CaseSize == 0) break;
2096 // Otherwise, execute the case we found.
2097 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2098 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2101 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2102 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2103 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2104 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2105 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2106 Opcode-OPC_CheckChild0Type))
2109 case OPC_CheckCondCode:
2110 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2112 case OPC_CheckValueType:
2113 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2115 case OPC_CheckInteger:
2116 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2118 case OPC_CheckAndImm:
2119 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2121 case OPC_CheckOrImm:
2122 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2125 case OPC_CheckFoldableChainNode: {
2126 assert(NodeStack.size() != 1 && "No parent node");
2127 // Verify that all intermediate nodes between the root and this one have
2129 bool HasMultipleUses = false;
2130 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2131 if (!NodeStack[i].hasOneUse()) {
2132 HasMultipleUses = true;
2135 if (HasMultipleUses) break;
2137 // Check to see that the target thinks this is profitable to fold and that
2138 // we can fold it without inducing cycles in the graph.
2139 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2141 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2142 NodeToMatch, OptLevel,
2143 true/*We validate our own chains*/))
2148 case OPC_EmitInteger: {
2149 MVT::SimpleValueType VT =
2150 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2151 int64_t Val = MatcherTable[MatcherIndex++];
2153 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2154 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT));
2157 case OPC_EmitRegister: {
2158 MVT::SimpleValueType VT =
2159 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2160 unsigned RegNo = MatcherTable[MatcherIndex++];
2161 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT));
2165 case OPC_EmitConvertToTarget: {
2166 // Convert from IMM/FPIMM to target version.
2167 unsigned RecNo = MatcherTable[MatcherIndex++];
2168 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2169 SDValue Imm = RecordedNodes[RecNo];
2171 if (Imm->getOpcode() == ISD::Constant) {
2172 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2173 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2174 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2175 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2176 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2179 RecordedNodes.push_back(Imm);
2183 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2184 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2185 // These are space-optimized forms of OPC_EmitMergeInputChains.
2186 assert(InputChain.getNode() == 0 &&
2187 "EmitMergeInputChains should be the first chain producing node");
2188 assert(ChainNodesMatched.empty() &&
2189 "Should only have one EmitMergeInputChains per match");
2191 // Read all of the chained nodes.
2192 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2193 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2194 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2196 // FIXME: What if other value results of the node have uses not matched
2198 if (ChainNodesMatched.back() != NodeToMatch &&
2199 !RecordedNodes[RecNo].hasOneUse()) {
2200 ChainNodesMatched.clear();
2204 // Merge the input chains if they are not intra-pattern references.
2205 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2207 if (InputChain.getNode() == 0)
2208 break; // Failed to merge.
2212 case OPC_EmitMergeInputChains: {
2213 assert(InputChain.getNode() == 0 &&
2214 "EmitMergeInputChains should be the first chain producing node");
2215 // This node gets a list of nodes we matched in the input that have
2216 // chains. We want to token factor all of the input chains to these nodes
2217 // together. However, if any of the input chains is actually one of the
2218 // nodes matched in this pattern, then we have an intra-match reference.
2219 // Ignore these because the newly token factored chain should not refer to
2221 unsigned NumChains = MatcherTable[MatcherIndex++];
2222 assert(NumChains != 0 && "Can't TF zero chains");
2224 assert(ChainNodesMatched.empty() &&
2225 "Should only have one EmitMergeInputChains per match");
2227 // Read all of the chained nodes.
2228 for (unsigned i = 0; i != NumChains; ++i) {
2229 unsigned RecNo = MatcherTable[MatcherIndex++];
2230 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2231 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2233 // FIXME: What if other value results of the node have uses not matched
2235 if (ChainNodesMatched.back() != NodeToMatch &&
2236 !RecordedNodes[RecNo].hasOneUse()) {
2237 ChainNodesMatched.clear();
2242 // If the inner loop broke out, the match fails.
2243 if (ChainNodesMatched.empty())
2246 // Merge the input chains if they are not intra-pattern references.
2247 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2249 if (InputChain.getNode() == 0)
2250 break; // Failed to merge.
2255 case OPC_EmitCopyToReg: {
2256 unsigned RecNo = MatcherTable[MatcherIndex++];
2257 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2258 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2260 if (InputChain.getNode() == 0)
2261 InputChain = CurDAG->getEntryNode();
2263 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2264 DestPhysReg, RecordedNodes[RecNo],
2267 InputFlag = InputChain.getValue(1);
2271 case OPC_EmitNodeXForm: {
2272 unsigned XFormNo = MatcherTable[MatcherIndex++];
2273 unsigned RecNo = MatcherTable[MatcherIndex++];
2274 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2275 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo));
2280 case OPC_MorphNodeTo: {
2281 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2282 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2283 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2284 // Get the result VT list.
2285 unsigned NumVTs = MatcherTable[MatcherIndex++];
2286 SmallVector<EVT, 4> VTs;
2287 for (unsigned i = 0; i != NumVTs; ++i) {
2288 MVT::SimpleValueType VT =
2289 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2290 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2294 if (EmitNodeInfo & OPFL_Chain)
2295 VTs.push_back(MVT::Other);
2296 if (EmitNodeInfo & OPFL_FlagOutput)
2297 VTs.push_back(MVT::Flag);
2299 // This is hot code, so optimize the two most common cases of 1 and 2
2302 if (VTs.size() == 1)
2303 VTList = CurDAG->getVTList(VTs[0]);
2304 else if (VTs.size() == 2)
2305 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2307 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2309 // Get the operand list.
2310 unsigned NumOps = MatcherTable[MatcherIndex++];
2311 SmallVector<SDValue, 8> Ops;
2312 for (unsigned i = 0; i != NumOps; ++i) {
2313 unsigned RecNo = MatcherTable[MatcherIndex++];
2315 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2317 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2318 Ops.push_back(RecordedNodes[RecNo]);
2321 // If there are variadic operands to add, handle them now.
2322 if (EmitNodeInfo & OPFL_VariadicInfo) {
2323 // Determine the start index to copy from.
2324 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2325 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2326 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2327 "Invalid variadic node");
2328 // Copy all of the variadic operands, not including a potential flag
2330 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2332 SDValue V = NodeToMatch->getOperand(i);
2333 if (V.getValueType() == MVT::Flag) break;
2338 // If this has chain/flag inputs, add them.
2339 if (EmitNodeInfo & OPFL_Chain)
2340 Ops.push_back(InputChain);
2341 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0)
2342 Ops.push_back(InputFlag);
2346 if (Opcode != OPC_MorphNodeTo) {
2347 // If this is a normal EmitNode command, just create the new node and
2348 // add the results to the RecordedNodes list.
2349 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2350 VTList, Ops.data(), Ops.size());
2352 // Add all the non-flag/non-chain results to the RecordedNodes list.
2353 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2354 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
2355 RecordedNodes.push_back(SDValue(Res, i));
2359 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2363 // If the node had chain/flag results, update our notion of the current
2365 if (EmitNodeInfo & OPFL_FlagOutput) {
2366 InputFlag = SDValue(Res, VTs.size()-1);
2367 if (EmitNodeInfo & OPFL_Chain)
2368 InputChain = SDValue(Res, VTs.size()-2);
2369 } else if (EmitNodeInfo & OPFL_Chain)
2370 InputChain = SDValue(Res, VTs.size()-1);
2372 // If the OPFL_MemRefs flag is set on this node, slap all of the
2373 // accumulated memrefs onto it.
2375 // FIXME: This is vastly incorrect for patterns with multiple outputs
2376 // instructions that access memory and for ComplexPatterns that match
2378 if (EmitNodeInfo & OPFL_MemRefs) {
2379 MachineSDNode::mmo_iterator MemRefs =
2380 MF->allocateMemRefsArray(MatchedMemRefs.size());
2381 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2382 cast<MachineSDNode>(Res)
2383 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2387 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2388 << " node: "; Res->dump(CurDAG); errs() << "\n");
2390 // If this was a MorphNodeTo then we're completely done!
2391 if (Opcode == OPC_MorphNodeTo) {
2392 // Update chain and flag uses.
2393 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2394 InputFlag, FlagResultNodesMatched, true);
2401 case OPC_MarkFlagResults: {
2402 unsigned NumNodes = MatcherTable[MatcherIndex++];
2404 // Read and remember all the flag-result nodes.
2405 for (unsigned i = 0; i != NumNodes; ++i) {
2406 unsigned RecNo = MatcherTable[MatcherIndex++];
2408 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2410 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2411 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2416 case OPC_CompleteMatch: {
2417 // The match has been completed, and any new nodes (if any) have been
2418 // created. Patch up references to the matched dag to use the newly
2420 unsigned NumResults = MatcherTable[MatcherIndex++];
2422 for (unsigned i = 0; i != NumResults; ++i) {
2423 unsigned ResSlot = MatcherTable[MatcherIndex++];
2425 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2427 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2428 SDValue Res = RecordedNodes[ResSlot];
2430 assert(i < NodeToMatch->getNumValues() &&
2431 NodeToMatch->getValueType(i) != MVT::Other &&
2432 NodeToMatch->getValueType(i) != MVT::Flag &&
2433 "Invalid number of results to complete!");
2434 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2435 NodeToMatch->getValueType(i) == MVT::iPTR ||
2436 Res.getValueType() == MVT::iPTR ||
2437 NodeToMatch->getValueType(i).getSizeInBits() ==
2438 Res.getValueType().getSizeInBits()) &&
2439 "invalid replacement");
2440 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2443 // If the root node defines a flag, add it to the flag nodes to update
2445 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag)
2446 FlagResultNodesMatched.push_back(NodeToMatch);
2448 // Update chain and flag uses.
2449 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2450 InputFlag, FlagResultNodesMatched, false);
2452 assert(NodeToMatch->use_empty() &&
2453 "Didn't replace all uses of the node?");
2455 // FIXME: We just return here, which interacts correctly with SelectRoot
2456 // above. We should fix this to not return an SDNode* anymore.
2461 // If the code reached this point, then the match failed. See if there is
2462 // another child to try in the current 'Scope', otherwise pop it until we
2463 // find a case to check.
2464 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2465 ++NumDAGIselRetries;
2467 if (MatchScopes.empty()) {
2468 CannotYetSelect(NodeToMatch);
2472 // Restore the interpreter state back to the point where the scope was
2474 MatchScope &LastScope = MatchScopes.back();
2475 RecordedNodes.resize(LastScope.NumRecordedNodes);
2477 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2478 N = NodeStack.back();
2480 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2481 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2482 MatcherIndex = LastScope.FailIndex;
2484 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2486 InputChain = LastScope.InputChain;
2487 InputFlag = LastScope.InputFlag;
2488 if (!LastScope.HasChainNodesMatched)
2489 ChainNodesMatched.clear();
2490 if (!LastScope.HasFlagResultNodesMatched)
2491 FlagResultNodesMatched.clear();
2493 // Check to see what the offset is at the new MatcherIndex. If it is zero
2494 // we have reached the end of this scope, otherwise we have another child
2495 // in the current scope to try.
2496 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2497 if (NumToSkip & 128)
2498 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2500 // If we have another child in this scope to match, update FailIndex and
2502 if (NumToSkip != 0) {
2503 LastScope.FailIndex = MatcherIndex+NumToSkip;
2507 // End of this scope, pop it and try the next child in the containing
2509 MatchScopes.pop_back();
2516 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2518 raw_string_ostream Msg(msg);
2519 Msg << "Cannot yet select: ";
2521 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2522 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2523 N->getOpcode() != ISD::INTRINSIC_VOID) {
2524 N->printrFull(Msg, CurDAG);
2526 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2528 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2529 if (iid < Intrinsic::num_intrinsics)
2530 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2531 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2532 Msg << "target intrinsic %" << TII->getName(iid);
2534 Msg << "unknown intrinsic #" << iid;
2536 report_fatal_error(Msg.str());
2539 char SelectionDAGISel::ID = 0;