1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Function.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/Instructions.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/IntrinsicInst.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/FastISel.h"
32 #include "llvm/CodeGen/GCStrategy.h"
33 #include "llvm/CodeGen/GCMetadata.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
36 #include "llvm/CodeGen/MachineFrameInfo.h"
37 #include "llvm/CodeGen/MachineInstrBuilder.h"
38 #include "llvm/CodeGen/MachineJumpTableInfo.h"
39 #include "llvm/CodeGen/MachineModuleInfo.h"
40 #include "llvm/CodeGen/MachineRegisterInfo.h"
41 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
42 #include "llvm/CodeGen/SchedulerRegistry.h"
43 #include "llvm/CodeGen/SelectionDAG.h"
44 #include "llvm/Target/TargetRegisterInfo.h"
45 #include "llvm/Target/TargetData.h"
46 #include "llvm/Target/TargetFrameInfo.h"
47 #include "llvm/Target/TargetIntrinsicInfo.h"
48 #include "llvm/Target/TargetInstrInfo.h"
49 #include "llvm/Target/TargetLowering.h"
50 #include "llvm/Target/TargetMachine.h"
51 #include "llvm/Target/TargetOptions.h"
52 #include "llvm/Support/Compiler.h"
53 #include "llvm/Support/Debug.h"
54 #include "llvm/Support/ErrorHandling.h"
55 #include "llvm/Support/MathExtras.h"
56 #include "llvm/Support/Timer.h"
57 #include "llvm/Support/raw_ostream.h"
58 #include "llvm/ADT/Statistic.h"
62 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
63 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
66 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
67 cl::desc("Enable verbose messages in the \"fast\" "
68 "instruction selector"));
70 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
71 cl::desc("Enable abort calls when \"fast\" instruction fails"));
73 SchedLiveInCopies("schedule-livein-copies", cl::Hidden,
74 cl::desc("Schedule copies of livein registers"),
79 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
80 cl::desc("Pop up a window to show dags before the first "
83 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
84 cl::desc("Pop up a window to show dags before legalize types"));
86 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
87 cl::desc("Pop up a window to show dags before legalize"));
89 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
90 cl::desc("Pop up a window to show dags before the second "
93 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
94 cl::desc("Pop up a window to show dags before the post legalize types"
95 " dag combine pass"));
97 ViewISelDAGs("view-isel-dags", cl::Hidden,
98 cl::desc("Pop up a window to show isel dags as they are selected"));
100 ViewSchedDAGs("view-sched-dags", cl::Hidden,
101 cl::desc("Pop up a window to show sched dags as they are processed"));
103 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
104 cl::desc("Pop up a window to show SUnit dags after they are processed"));
106 static const bool ViewDAGCombine1 = false,
107 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
108 ViewDAGCombine2 = false,
109 ViewDAGCombineLT = false,
110 ViewISelDAGs = false, ViewSchedDAGs = false,
111 ViewSUnitDAGs = false;
114 //===---------------------------------------------------------------------===//
116 /// RegisterScheduler class - Track the registration of instruction schedulers.
118 //===---------------------------------------------------------------------===//
119 MachinePassRegistry RegisterScheduler::Registry;
121 //===---------------------------------------------------------------------===//
123 /// ISHeuristic command line option for instruction schedulers.
125 //===---------------------------------------------------------------------===//
126 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
127 RegisterPassParser<RegisterScheduler> >
128 ISHeuristic("pre-RA-sched",
129 cl::init(&createDefaultScheduler),
130 cl::desc("Instruction schedulers available (before register"
133 static RegisterScheduler
134 defaultListDAGScheduler("default", "Best scheduler for the target",
135 createDefaultScheduler);
138 //===--------------------------------------------------------------------===//
139 /// createDefaultScheduler - This creates an instruction scheduler appropriate
141 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
142 CodeGenOpt::Level OptLevel) {
143 const TargetLowering &TLI = IS->getTargetLowering();
145 if (OptLevel == CodeGenOpt::None)
146 return createFastDAGScheduler(IS, OptLevel);
147 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
148 return createTDListDAGScheduler(IS, OptLevel);
149 assert(TLI.getSchedulingPreference() ==
150 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
151 return createBURRListDAGScheduler(IS, OptLevel);
155 // EmitInstrWithCustomInserter - This method should be implemented by targets
156 // that mark instructions with the 'usesCustomInserter' flag. These
157 // instructions are special in various ways, which require special support to
158 // insert. The specified MachineInstr is created but not inserted into any
159 // basic blocks, and this method is called to expand it into a sequence of
160 // instructions, potentially also creating new basic blocks and control flow.
161 // When new basic blocks are inserted and the edges from MBB to its successors
162 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
164 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
165 MachineBasicBlock *MBB,
166 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
168 dbgs() << "If a target marks an instruction with "
169 "'usesCustomInserter', it must implement "
170 "TargetLowering::EmitInstrWithCustomInserter!";
176 /// EmitLiveInCopy - Emit a copy for a live in physical register. If the
177 /// physical register has only a single copy use, then coalesced the copy
179 static void EmitLiveInCopy(MachineBasicBlock *MBB,
180 MachineBasicBlock::iterator &InsertPos,
181 unsigned VirtReg, unsigned PhysReg,
182 const TargetRegisterClass *RC,
183 DenseMap<MachineInstr*, unsigned> &CopyRegMap,
184 const MachineRegisterInfo &MRI,
185 const TargetRegisterInfo &TRI,
186 const TargetInstrInfo &TII) {
187 unsigned NumUses = 0;
188 MachineInstr *UseMI = NULL;
189 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg),
190 UE = MRI.use_end(); UI != UE; ++UI) {
196 // If the number of uses is not one, or the use is not a move instruction,
197 // don't coalesce. Also, only coalesce away a virtual register to virtual
199 bool Coalesced = false;
200 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
202 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
203 TargetRegisterInfo::isVirtualRegister(DstReg)) {
208 // Now find an ideal location to insert the copy.
209 MachineBasicBlock::iterator Pos = InsertPos;
210 while (Pos != MBB->begin()) {
211 MachineInstr *PrevMI = prior(Pos);
212 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI);
213 // copyRegToReg might emit multiple instructions to do a copy.
214 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second;
215 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg))
216 // This is what the BB looks like right now:
221 // We want to insert "r1025 = mov r1". Inserting this copy below the
222 // move to r1024 makes it impossible for that move to be coalesced.
229 break; // Woot! Found a good location.
233 bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC);
234 assert(Emitted && "Unable to issue a live-in copy instruction!\n");
237 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg));
239 if (&*InsertPos == UseMI) ++InsertPos;
244 /// EmitLiveInCopies - If this is the first basic block in the function,
245 /// and if it has live ins that need to be copied into vregs, emit the
246 /// copies into the block.
247 static void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
248 const MachineRegisterInfo &MRI,
249 const TargetRegisterInfo &TRI,
250 const TargetInstrInfo &TII) {
251 if (SchedLiveInCopies) {
252 // Emit the copies at a heuristically-determined location in the block.
253 DenseMap<MachineInstr*, unsigned> CopyRegMap;
254 MachineBasicBlock::iterator InsertPos = EntryMBB->begin();
255 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
256 E = MRI.livein_end(); LI != E; ++LI)
258 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
259 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first,
260 RC, CopyRegMap, MRI, TRI, TII);
263 // Emit the copies into the top of the block.
264 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
265 E = MRI.livein_end(); LI != E; ++LI)
267 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
268 bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(),
269 LI->second, LI->first, RC, RC);
270 assert(Emitted && "Unable to issue a live-in copy instruction!\n");
276 //===----------------------------------------------------------------------===//
277 // SelectionDAGISel code
278 //===----------------------------------------------------------------------===//
280 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) :
281 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
282 FuncInfo(new FunctionLoweringInfo(TLI)),
283 CurDAG(new SelectionDAG(TLI, *FuncInfo)),
284 SDB(new SelectionDAGBuilder(*CurDAG, TLI, *FuncInfo, OL)),
290 SelectionDAGISel::~SelectionDAGISel() {
296 unsigned SelectionDAGISel::MakeReg(EVT VT) {
297 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
300 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
301 AU.addRequired<AliasAnalysis>();
302 AU.addPreserved<AliasAnalysis>();
303 AU.addRequired<GCModuleInfo>();
304 AU.addPreserved<GCModuleInfo>();
305 MachineFunctionPass::getAnalysisUsage(AU);
308 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
309 Function &Fn = *mf.getFunction();
311 // Do some sanity-checking on the command-line options.
312 assert((!EnableFastISelVerbose || EnableFastISel) &&
313 "-fast-isel-verbose requires -fast-isel");
314 assert((!EnableFastISelAbort || EnableFastISel) &&
315 "-fast-isel-abort requires -fast-isel");
317 // Get alias analysis for load/store combining.
318 AA = &getAnalysis<AliasAnalysis>();
321 const TargetInstrInfo &TII = *TM.getInstrInfo();
322 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
325 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn);
328 RegInfo = &MF->getRegInfo();
329 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
331 MachineModuleInfo *MMI = getAnalysisIfAvailable<MachineModuleInfo>();
332 CurDAG->init(*MF, MMI);
333 FuncInfo->set(Fn, *MF, EnableFastISel);
336 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
337 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
339 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
341 SelectAllBasicBlocks(Fn, *MF, MMI, TII);
343 // If the first basic block in the function has live ins that need to be
344 // copied into vregs, emit the copies into the top of the block before
345 // emitting the code for the block.
346 EmitLiveInCopies(MF->begin(), *RegInfo, TRI, TII);
348 // Add function live-ins to entry block live-in set.
349 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
350 E = RegInfo->livein_end(); I != E; ++I)
351 MF->begin()->addLiveIn(I->first);
354 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() &&
355 "Not all catch info was assigned to a landing pad!");
363 /// SetDebugLoc - Update MF's and SDB's DebugLocs if debug information is
364 /// attached with this instruction.
365 static void SetDebugLoc(Instruction *I, SelectionDAGBuilder *SDB,
366 FastISel *FastIS, MachineFunction *MF) {
367 DebugLoc DL = I->getDebugLoc();
368 if (DL.isUnknown()) return;
370 SDB->setCurDebugLoc(DL);
373 FastIS->setCurDebugLoc(DL);
375 // If the function doesn't have a default debug location yet, set
376 // it. This is kind of a hack.
377 if (MF->getDefaultDebugLoc().isUnknown())
378 MF->setDefaultDebugLoc(DL);
381 /// ResetDebugLoc - Set MF's and SDB's DebugLocs to Unknown.
382 static void ResetDebugLoc(SelectionDAGBuilder *SDB, FastISel *FastIS) {
383 SDB->setCurDebugLoc(DebugLoc());
385 FastIS->setCurDebugLoc(DebugLoc());
388 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
389 BasicBlock::iterator Begin,
390 BasicBlock::iterator End,
392 SDB->setCurrentBasicBlock(BB);
394 // Lower all of the non-terminator instructions. If a call is emitted
395 // as a tail call, cease emitting nodes for this block.
396 for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) {
397 SetDebugLoc(I, SDB, 0, MF);
399 if (!isa<TerminatorInst>(I)) {
402 // Set the current debug location back to "unknown" so that it doesn't
403 // spuriously apply to subsequent instructions.
404 ResetDebugLoc(SDB, 0);
408 if (!SDB->HasTailCall) {
409 // Ensure that all instructions which are used outside of their defining
410 // blocks are available as virtual registers. Invoke is handled elsewhere.
411 for (BasicBlock::iterator I = Begin; I != End; ++I)
412 if (!isa<PHINode>(I) && !isa<InvokeInst>(I))
413 SDB->CopyToExportRegsIfNeeded(I);
415 // Handle PHI nodes in successor blocks.
416 if (End == LLVMBB->end()) {
417 HandlePHINodesInSuccessorBlocks(LLVMBB);
419 // Lower the terminator after the copies are emitted.
420 SetDebugLoc(LLVMBB->getTerminator(), SDB, 0, MF);
421 SDB->visit(*LLVMBB->getTerminator());
422 ResetDebugLoc(SDB, 0);
426 // Make sure the root of the DAG is up-to-date.
427 CurDAG->setRoot(SDB->getControlRoot());
429 // Final step, emit the lowered DAG as machine code.
431 HadTailCall = SDB->HasTailCall;
436 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
437 /// nodes from the worklist.
438 class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener {
439 SmallVector<SDNode*, 128> &Worklist;
440 SmallPtrSet<SDNode*, 128> &InWorklist;
442 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl,
443 SmallPtrSet<SDNode*, 128> &inwl)
444 : Worklist(wl), InWorklist(inwl) {}
446 void RemoveFromWorklist(SDNode *N) {
447 if (!InWorklist.erase(N)) return;
449 SmallVector<SDNode*, 128>::iterator I =
450 std::find(Worklist.begin(), Worklist.end(), N);
451 assert(I != Worklist.end() && "Not in worklist");
453 *I = Worklist.back();
457 virtual void NodeDeleted(SDNode *N, SDNode *E) {
458 RemoveFromWorklist(N);
461 virtual void NodeUpdated(SDNode *N) {
467 /// TrivialTruncElim - Eliminate some trivial nops that can result from
468 /// ShrinkDemandedOps: (trunc (ext n)) -> n.
469 static bool TrivialTruncElim(SDValue Op,
470 TargetLowering::TargetLoweringOpt &TLO) {
471 SDValue N0 = Op.getOperand(0);
472 EVT VT = Op.getValueType();
473 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
474 N0.getOpcode() == ISD::SIGN_EXTEND ||
475 N0.getOpcode() == ISD::ANY_EXTEND) &&
476 N0.getOperand(0).getValueType() == VT) {
477 return TLO.CombineTo(Op, N0.getOperand(0));
482 /// ShrinkDemandedOps - A late transformation pass that shrink expressions
483 /// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts
484 /// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
485 void SelectionDAGISel::ShrinkDemandedOps() {
486 SmallVector<SDNode*, 128> Worklist;
487 SmallPtrSet<SDNode*, 128> InWorklist;
489 // Add all the dag nodes to the worklist.
490 Worklist.reserve(CurDAG->allnodes_size());
491 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
492 E = CurDAG->allnodes_end(); I != E; ++I) {
493 Worklist.push_back(I);
494 InWorklist.insert(I);
497 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true);
498 while (!Worklist.empty()) {
499 SDNode *N = Worklist.pop_back_val();
502 if (N->use_empty() && N != CurDAG->getRoot().getNode()) {
503 // Deleting this node may make its operands dead, add them to the worklist
504 // if they aren't already there.
505 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
506 if (InWorklist.insert(N->getOperand(i).getNode()))
507 Worklist.push_back(N->getOperand(i).getNode());
509 CurDAG->DeleteNode(N);
513 // Run ShrinkDemandedOp on scalar binary operations.
514 if (N->getNumValues() != 1 ||
515 !N->getValueType(0).isSimple() || !N->getValueType(0).isInteger())
518 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
519 APInt Demanded = APInt::getAllOnesValue(BitWidth);
520 APInt KnownZero, KnownOne;
521 if (!TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded,
522 KnownZero, KnownOne, TLO) &&
523 (N->getOpcode() != ISD::TRUNCATE ||
524 !TrivialTruncElim(SDValue(N, 0), TLO)))
528 assert(!InWorklist.count(N) && "Already in worklist");
529 Worklist.push_back(N);
530 InWorklist.insert(N);
532 // Replace the old value with the new one.
533 DEBUG(errs() << "\nShrinkDemandedOps replacing ";
534 TLO.Old.getNode()->dump(CurDAG);
535 errs() << "\nWith: ";
536 TLO.New.getNode()->dump(CurDAG);
539 if (InWorklist.insert(TLO.New.getNode()))
540 Worklist.push_back(TLO.New.getNode());
542 SDOPsWorkListRemover DeadNodes(Worklist, InWorklist);
543 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
545 if (!TLO.Old.getNode()->use_empty()) continue;
547 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands();
549 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode();
550 if (OpNode->hasOneUse()) {
551 // Add OpNode to the end of the list to revisit.
552 DeadNodes.RemoveFromWorklist(OpNode);
553 Worklist.push_back(OpNode);
554 InWorklist.insert(OpNode);
558 DeadNodes.RemoveFromWorklist(TLO.Old.getNode());
559 CurDAG->DeleteNode(TLO.Old.getNode());
563 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
564 SmallPtrSet<SDNode*, 128> VisitedNodes;
565 SmallVector<SDNode*, 128> Worklist;
567 Worklist.push_back(CurDAG->getRoot().getNode());
574 SDNode *N = Worklist.pop_back_val();
576 // If we've already seen this node, ignore it.
577 if (!VisitedNodes.insert(N))
580 // Otherwise, add all chain operands to the worklist.
581 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
582 if (N->getOperand(i).getValueType() == MVT::Other)
583 Worklist.push_back(N->getOperand(i).getNode());
585 // If this is a CopyToReg with a vreg dest, process it.
586 if (N->getOpcode() != ISD::CopyToReg)
589 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
590 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
593 // Ignore non-scalar or non-integer values.
594 SDValue Src = N->getOperand(2);
595 EVT SrcVT = Src.getValueType();
596 if (!SrcVT.isInteger() || SrcVT.isVector())
599 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
600 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
601 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
603 // Only install this information if it tells us something.
604 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
605 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
606 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
607 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
608 FunctionLoweringInfo::LiveOutInfo &LOI =
609 FuncInfo->LiveOutRegInfo[DestReg];
610 LOI.NumSignBits = NumSignBits;
611 LOI.KnownOne = KnownOne;
612 LOI.KnownZero = KnownZero;
614 } while (!Worklist.empty());
617 void SelectionDAGISel::CodeGenAndEmitDAG() {
618 std::string GroupName;
619 if (TimePassesIsEnabled)
620 GroupName = "Instruction Selection and Scheduling";
621 std::string BlockName;
622 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
623 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
625 BlockName = MF->getFunction()->getNameStr() + ":" +
626 BB->getBasicBlock()->getNameStr();
628 DEBUG(dbgs() << "Initial selection DAG:\n");
629 DEBUG(CurDAG->dump());
631 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
633 // Run the DAG combiner in pre-legalize mode.
634 if (TimePassesIsEnabled) {
635 NamedRegionTimer T("DAG Combining 1", GroupName);
636 CurDAG->Combine(Unrestricted, *AA, OptLevel);
638 CurDAG->Combine(Unrestricted, *AA, OptLevel);
641 DEBUG(dbgs() << "Optimized lowered selection DAG:\n");
642 DEBUG(CurDAG->dump());
644 // Second step, hack on the DAG until it only uses operations and types that
645 // the target supports.
646 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
650 if (TimePassesIsEnabled) {
651 NamedRegionTimer T("Type Legalization", GroupName);
652 Changed = CurDAG->LegalizeTypes();
654 Changed = CurDAG->LegalizeTypes();
657 DEBUG(dbgs() << "Type-legalized selection DAG:\n");
658 DEBUG(CurDAG->dump());
661 if (ViewDAGCombineLT)
662 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
664 // Run the DAG combiner in post-type-legalize mode.
665 if (TimePassesIsEnabled) {
666 NamedRegionTimer T("DAG Combining after legalize types", GroupName);
667 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
669 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
672 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n");
673 DEBUG(CurDAG->dump());
676 if (TimePassesIsEnabled) {
677 NamedRegionTimer T("Vector Legalization", GroupName);
678 Changed = CurDAG->LegalizeVectors();
680 Changed = CurDAG->LegalizeVectors();
684 if (TimePassesIsEnabled) {
685 NamedRegionTimer T("Type Legalization 2", GroupName);
686 CurDAG->LegalizeTypes();
688 CurDAG->LegalizeTypes();
691 if (ViewDAGCombineLT)
692 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
694 // Run the DAG combiner in post-type-legalize mode.
695 if (TimePassesIsEnabled) {
696 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName);
697 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
699 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
702 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n");
703 DEBUG(CurDAG->dump());
706 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
708 if (TimePassesIsEnabled) {
709 NamedRegionTimer T("DAG Legalization", GroupName);
710 CurDAG->Legalize(OptLevel);
712 CurDAG->Legalize(OptLevel);
715 DEBUG(dbgs() << "Legalized selection DAG:\n");
716 DEBUG(CurDAG->dump());
718 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
720 // Run the DAG combiner in post-legalize mode.
721 if (TimePassesIsEnabled) {
722 NamedRegionTimer T("DAG Combining 2", GroupName);
723 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
725 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
728 DEBUG(dbgs() << "Optimized legalized selection DAG:\n");
729 DEBUG(CurDAG->dump());
731 if (OptLevel != CodeGenOpt::None) {
733 ComputeLiveOutVRegInfo();
736 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
738 // Third, instruction select all of the operations to machine code, adding the
739 // code to the MachineBasicBlock.
740 if (TimePassesIsEnabled) {
741 NamedRegionTimer T("Instruction Selection", GroupName);
742 DoInstructionSelection();
744 DoInstructionSelection();
747 DEBUG(dbgs() << "Selected selection DAG:\n");
748 DEBUG(CurDAG->dump());
750 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
752 // Schedule machine code.
753 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
754 if (TimePassesIsEnabled) {
755 NamedRegionTimer T("Instruction Scheduling", GroupName);
756 Scheduler->Run(CurDAG, BB, BB->end());
758 Scheduler->Run(CurDAG, BB, BB->end());
761 if (ViewSUnitDAGs) Scheduler->viewGraph();
763 // Emit machine code to BB. This can change 'BB' to the last block being
765 if (TimePassesIsEnabled) {
766 NamedRegionTimer T("Instruction Creation", GroupName);
767 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
769 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
772 // Free the scheduler state.
773 if (TimePassesIsEnabled) {
774 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
780 DEBUG(dbgs() << "Selected machine code:\n");
784 void SelectionDAGISel::DoInstructionSelection() {
785 DEBUG(errs() << "===== Instruction selection begins:\n");
789 // Select target instructions for the DAG.
791 // Number all nodes with a topological order and set DAGSize.
792 DAGSize = CurDAG->AssignTopologicalOrder();
794 // Create a dummy node (which is not added to allnodes), that adds
795 // a reference to the root node, preventing it from being deleted,
796 // and tracking any changes of the root.
797 HandleSDNode Dummy(CurDAG->getRoot());
798 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
801 // The AllNodes list is now topological-sorted. Visit the
802 // nodes by starting at the end of the list (the root of the
803 // graph) and preceding back toward the beginning (the entry
805 while (ISelPosition != CurDAG->allnodes_begin()) {
806 SDNode *Node = --ISelPosition;
807 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
808 // but there are currently some corner cases that it misses. Also, this
809 // makes it theoretically possible to disable the DAGCombiner.
810 if (Node->use_empty())
813 SDNode *ResNode = Select(Node);
815 // FIXME: This is pretty gross. 'Select' should be changed to not return
816 // anything at all and this code should be nuked with a tactical strike.
818 // If node should not be replaced, continue with the next one.
819 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
823 ReplaceUses(Node, ResNode);
825 // If after the replacement this node is not used any more,
826 // remove this dead node.
827 if (Node->use_empty()) { // Don't delete EntryToken, etc.
828 ISelUpdater ISU(ISelPosition);
829 CurDAG->RemoveDeadNode(Node, &ISU);
833 CurDAG->setRoot(Dummy.getValue());
835 DEBUG(errs() << "===== Instruction selection ends:\n");
837 PostprocessISelDAG();
841 void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
843 MachineModuleInfo *MMI,
844 const TargetInstrInfo &TII) {
845 // Initialize the Fast-ISel state, if needed.
846 FastISel *FastIS = 0;
848 FastIS = TLI.createFastISel(MF, MMI,
851 FuncInfo->StaticAllocaMap
853 , FuncInfo->CatchInfoLost
857 // Iterate over all basic blocks in the function.
858 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
859 BasicBlock *LLVMBB = &*I;
860 BB = FuncInfo->MBBMap[LLVMBB];
862 BasicBlock::iterator const Begin = LLVMBB->begin();
863 BasicBlock::iterator const End = LLVMBB->end();
864 BasicBlock::iterator BI = Begin;
866 // Lower any arguments needed in this block if this is the entry block.
867 bool SuppressFastISel = false;
868 if (LLVMBB == &Fn.getEntryBlock()) {
869 LowerArguments(LLVMBB);
871 // If any of the arguments has the byval attribute, forgo
872 // fast-isel in the entry block.
875 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end();
877 if (Fn.paramHasAttr(j, Attribute::ByVal)) {
878 if (EnableFastISelVerbose || EnableFastISelAbort)
879 dbgs() << "FastISel skips entry block due to byval argument\n";
880 SuppressFastISel = true;
886 if (MMI && BB->isLandingPad()) {
887 // Add a label to mark the beginning of the landing pad. Deletion of the
888 // landing pad can thus be detected via the MachineModuleInfo.
889 MCSymbol *Label = MMI->addLandingPad(BB);
891 const TargetInstrDesc &II = TII.get(TargetOpcode::EH_LABEL);
892 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label);
894 // Mark exception register as live in.
895 unsigned Reg = TLI.getExceptionAddressRegister();
896 if (Reg) BB->addLiveIn(Reg);
898 // Mark exception selector register as live in.
899 Reg = TLI.getExceptionSelectorRegister();
900 if (Reg) BB->addLiveIn(Reg);
902 // FIXME: Hack around an exception handling flaw (PR1508): the personality
903 // function and list of typeids logically belong to the invoke (or, if you
904 // like, the basic block containing the invoke), and need to be associated
905 // with it in the dwarf exception handling tables. Currently however the
906 // information is provided by an intrinsic (eh.selector) that can be moved
907 // to unexpected places by the optimizers: if the unwind edge is critical,
908 // then breaking it can result in the intrinsics being in the successor of
909 // the landing pad, not the landing pad itself. This results
910 // in exceptions not being caught because no typeids are associated with
911 // the invoke. This may not be the only way things can go wrong, but it
912 // is the only way we try to work around for the moment.
913 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
915 if (Br && Br->isUnconditional()) { // Critical edge?
916 BasicBlock::iterator I, E;
917 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
918 if (isa<EHSelectorInst>(I))
922 // No catch info found - try to extract some from the successor.
923 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo);
927 // Before doing SelectionDAG ISel, see if FastISel has been requested.
928 if (FastIS && !SuppressFastISel) {
929 // Emit code for any incoming arguments. This must happen before
930 // beginning FastISel on the entry block.
931 if (LLVMBB == &Fn.getEntryBlock()) {
932 CurDAG->setRoot(SDB->getControlRoot());
936 FastIS->startNewBlock(BB);
937 // Do FastISel on as many instructions as possible.
938 for (; BI != End; ++BI) {
939 // Just before the terminator instruction, insert instructions to
940 // feed PHI nodes in successor blocks.
941 if (isa<TerminatorInst>(BI))
942 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) {
943 ++NumFastIselFailures;
944 ResetDebugLoc(SDB, FastIS);
945 if (EnableFastISelVerbose || EnableFastISelAbort) {
946 dbgs() << "FastISel miss: ";
949 assert(!EnableFastISelAbort &&
950 "FastISel didn't handle a PHI in a successor");
954 SetDebugLoc(BI, SDB, FastIS, &MF);
956 // Try to select the instruction with FastISel.
957 if (FastIS->SelectInstruction(BI)) {
958 ResetDebugLoc(SDB, FastIS);
962 // Clear out the debug location so that it doesn't carry over to
963 // unrelated instructions.
964 ResetDebugLoc(SDB, FastIS);
966 // Then handle certain instructions as single-LLVM-Instruction blocks.
967 if (isa<CallInst>(BI)) {
968 ++NumFastIselFailures;
969 if (EnableFastISelVerbose || EnableFastISelAbort) {
970 dbgs() << "FastISel missed call: ";
974 if (!BI->getType()->isVoidTy()) {
975 unsigned &R = FuncInfo->ValueMap[BI];
977 R = FuncInfo->CreateRegForValue(BI);
980 bool HadTailCall = false;
981 SelectBasicBlock(LLVMBB, BI, llvm::next(BI), HadTailCall);
983 // If the call was emitted as a tail call, we're done with the block.
989 // If the instruction was codegen'd with multiple blocks,
990 // inform the FastISel object where to resume inserting.
991 FastIS->setCurrentBlock(BB);
995 // Otherwise, give up on FastISel for the rest of the block.
996 // For now, be a little lenient about non-branch terminators.
997 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
998 ++NumFastIselFailures;
999 if (EnableFastISelVerbose || EnableFastISelAbort) {
1000 dbgs() << "FastISel miss: ";
1003 if (EnableFastISelAbort)
1004 // The "fast" selector couldn't handle something and bailed.
1005 // For the purpose of debugging, just abort.
1006 llvm_unreachable("FastISel didn't select the entire block");
1012 // Run SelectionDAG instruction selection on the remainder of the block
1013 // not handled by FastISel. If FastISel is not run, this is the entire
1017 SelectBasicBlock(LLVMBB, BI, End, HadTailCall);
1027 SelectionDAGISel::FinishBasicBlock() {
1029 DEBUG(dbgs() << "Target-post-processed machine code:\n");
1032 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1033 << SDB->PHINodesToUpdate.size() << "\n");
1034 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i)
1035 dbgs() << "Node " << i << " : ("
1036 << SDB->PHINodesToUpdate[i].first
1037 << ", " << SDB->PHINodesToUpdate[i].second << ")\n");
1039 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1040 // PHI nodes in successors.
1041 if (SDB->SwitchCases.empty() &&
1042 SDB->JTCases.empty() &&
1043 SDB->BitTestCases.empty()) {
1044 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
1045 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
1046 assert(PHI->isPHI() &&
1047 "This is not a machine PHI node that we are updating!");
1048 if (!BB->isSuccessor(PHI->getParent()))
1050 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
1052 PHI->addOperand(MachineOperand::CreateMBB(BB));
1054 SDB->PHINodesToUpdate.clear();
1058 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1059 // Lower header first, if it wasn't already lowered
1060 if (!SDB->BitTestCases[i].Emitted) {
1061 // Set the current basic block to the mbb we wish to insert the code into
1062 BB = SDB->BitTestCases[i].Parent;
1063 SDB->setCurrentBasicBlock(BB);
1065 SDB->visitBitTestHeader(SDB->BitTestCases[i]);
1066 CurDAG->setRoot(SDB->getRoot());
1067 CodeGenAndEmitDAG();
1071 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1072 // Set the current basic block to the mbb we wish to insert the code into
1073 BB = SDB->BitTestCases[i].Cases[j].ThisBB;
1074 SDB->setCurrentBasicBlock(BB);
1077 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
1078 SDB->BitTestCases[i].Reg,
1079 SDB->BitTestCases[i].Cases[j]);
1081 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
1082 SDB->BitTestCases[i].Reg,
1083 SDB->BitTestCases[i].Cases[j]);
1086 CurDAG->setRoot(SDB->getRoot());
1087 CodeGenAndEmitDAG();
1092 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
1093 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
1094 MachineBasicBlock *PHIBB = PHI->getParent();
1095 assert(PHI->isPHI() &&
1096 "This is not a machine PHI node that we are updating!");
1097 // This is "default" BB. We have two jumps to it. From "header" BB and
1098 // from last "case" BB.
1099 if (PHIBB == SDB->BitTestCases[i].Default) {
1100 PHI->addOperand(MachineOperand::
1101 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1102 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
1103 PHI->addOperand(MachineOperand::
1104 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1105 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
1108 // One of "cases" BB.
1109 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1111 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1112 if (cBB->isSuccessor(PHIBB)) {
1113 PHI->addOperand(MachineOperand::
1114 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1115 PHI->addOperand(MachineOperand::CreateMBB(cBB));
1120 SDB->BitTestCases.clear();
1122 // If the JumpTable record is filled in, then we need to emit a jump table.
1123 // Updating the PHI nodes is tricky in this case, since we need to determine
1124 // whether the PHI is a successor of the range check MBB or the jump table MBB
1125 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1126 // Lower header first, if it wasn't already lowered
1127 if (!SDB->JTCases[i].first.Emitted) {
1128 // Set the current basic block to the mbb we wish to insert the code into
1129 BB = SDB->JTCases[i].first.HeaderBB;
1130 SDB->setCurrentBasicBlock(BB);
1132 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first);
1133 CurDAG->setRoot(SDB->getRoot());
1134 CodeGenAndEmitDAG();
1138 // Set the current basic block to the mbb we wish to insert the code into
1139 BB = SDB->JTCases[i].second.MBB;
1140 SDB->setCurrentBasicBlock(BB);
1142 SDB->visitJumpTable(SDB->JTCases[i].second);
1143 CurDAG->setRoot(SDB->getRoot());
1144 CodeGenAndEmitDAG();
1148 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
1149 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
1150 MachineBasicBlock *PHIBB = PHI->getParent();
1151 assert(PHI->isPHI() &&
1152 "This is not a machine PHI node that we are updating!");
1153 // "default" BB. We can go there only from header BB.
1154 if (PHIBB == SDB->JTCases[i].second.Default) {
1156 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1158 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1160 // JT BB. Just iterate over successors here
1161 if (BB->isSuccessor(PHIBB)) {
1163 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1164 PHI->addOperand(MachineOperand::CreateMBB(BB));
1168 SDB->JTCases.clear();
1170 // If the switch block involved a branch to one of the actual successors, we
1171 // need to update PHI nodes in that block.
1172 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
1173 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
1174 assert(PHI->isPHI() &&
1175 "This is not a machine PHI node that we are updating!");
1176 if (BB->isSuccessor(PHI->getParent())) {
1177 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
1179 PHI->addOperand(MachineOperand::CreateMBB(BB));
1183 // If we generated any switch lowering information, build and codegen any
1184 // additional DAGs necessary.
1185 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1186 // Set the current basic block to the mbb we wish to insert the code into
1187 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB;
1188 SDB->setCurrentBasicBlock(BB);
1191 SDB->visitSwitchCase(SDB->SwitchCases[i]);
1192 CurDAG->setRoot(SDB->getRoot());
1193 CodeGenAndEmitDAG();
1195 // Handle any PHI nodes in successors of this chunk, as if we were coming
1196 // from the original BB before switch expansion. Note that PHI nodes can
1197 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1198 // handle them the right number of times.
1199 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
1200 // If new BB's are created during scheduling, the edges may have been
1201 // updated. That is, the edge from ThisBB to BB may have been split and
1202 // BB's predecessor is now another block.
1203 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI =
1204 SDB->EdgeMapping.find(BB);
1205 if (EI != SDB->EdgeMapping.end())
1206 ThisBB = EI->second;
1208 // BB may have been removed from the CFG if a branch was constant folded.
1209 if (ThisBB->isSuccessor(BB)) {
1210 for (MachineBasicBlock::iterator Phi = BB->begin();
1211 Phi != BB->end() && Phi->isPHI();
1213 // This value for this PHI node is recorded in PHINodesToUpdate.
1214 for (unsigned pn = 0; ; ++pn) {
1215 assert(pn != SDB->PHINodesToUpdate.size() &&
1216 "Didn't find PHI entry!");
1217 if (SDB->PHINodesToUpdate[pn].first == Phi) {
1218 Phi->addOperand(MachineOperand::
1219 CreateReg(SDB->PHINodesToUpdate[pn].second,
1221 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1228 // Don't process RHS if same block as LHS.
1229 if (BB == SDB->SwitchCases[i].FalseBB)
1230 SDB->SwitchCases[i].FalseBB = 0;
1232 // If we haven't handled the RHS, do so now. Otherwise, we're done.
1233 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB;
1234 SDB->SwitchCases[i].FalseBB = 0;
1236 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0);
1239 SDB->SwitchCases.clear();
1241 SDB->PHINodesToUpdate.clear();
1245 /// Create the scheduler. If a specific scheduler was specified
1246 /// via the SchedulerRegistry, use it, otherwise select the
1247 /// one preferred by the target.
1249 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1250 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1254 RegisterScheduler::setDefault(Ctor);
1257 return Ctor(this, OptLevel);
1260 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1261 return new ScheduleHazardRecognizer();
1264 //===----------------------------------------------------------------------===//
1265 // Helper functions used by the generated instruction selector.
1266 //===----------------------------------------------------------------------===//
1267 // Calls to these methods are generated by tblgen.
1269 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1270 /// the dag combiner simplified the 255, we still want to match. RHS is the
1271 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1272 /// specified in the .td file (e.g. 255).
1273 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1274 int64_t DesiredMaskS) const {
1275 const APInt &ActualMask = RHS->getAPIntValue();
1276 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1278 // If the actual mask exactly matches, success!
1279 if (ActualMask == DesiredMask)
1282 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1283 if (ActualMask.intersects(~DesiredMask))
1286 // Otherwise, the DAG Combiner may have proven that the value coming in is
1287 // either already zero or is not demanded. Check for known zero input bits.
1288 APInt NeededMask = DesiredMask & ~ActualMask;
1289 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1292 // TODO: check to see if missing bits are just not demanded.
1294 // Otherwise, this pattern doesn't match.
1298 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1299 /// the dag combiner simplified the 255, we still want to match. RHS is the
1300 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1301 /// specified in the .td file (e.g. 255).
1302 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1303 int64_t DesiredMaskS) const {
1304 const APInt &ActualMask = RHS->getAPIntValue();
1305 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1307 // If the actual mask exactly matches, success!
1308 if (ActualMask == DesiredMask)
1311 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1312 if (ActualMask.intersects(~DesiredMask))
1315 // Otherwise, the DAG Combiner may have proven that the value coming in is
1316 // either already zero or is not demanded. Check for known zero input bits.
1317 APInt NeededMask = DesiredMask & ~ActualMask;
1319 APInt KnownZero, KnownOne;
1320 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1322 // If all the missing bits in the or are already known to be set, match!
1323 if ((NeededMask & KnownOne) == NeededMask)
1326 // TODO: check to see if missing bits are just not demanded.
1328 // Otherwise, this pattern doesn't match.
1333 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1334 /// by tblgen. Others should not call it.
1335 void SelectionDAGISel::
1336 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1337 std::vector<SDValue> InOps;
1338 std::swap(InOps, Ops);
1340 Ops.push_back(InOps[0]); // input chain.
1341 Ops.push_back(InOps[1]); // input asm string.
1343 unsigned i = 2, e = InOps.size();
1344 if (InOps[e-1].getValueType() == MVT::Flag)
1345 --e; // Don't process a flag operand if it is here.
1348 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1349 if ((Flags & 7) != 4 /*MEM*/) {
1350 // Just skip over this operand, copying the operands verbatim.
1351 Ops.insert(Ops.end(), InOps.begin()+i,
1352 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1353 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1355 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1356 "Memory operand with multiple values?");
1357 // Otherwise, this is a memory operand. Ask the target to select it.
1358 std::vector<SDValue> SelOps;
1359 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) {
1360 llvm_report_error("Could not match memory address. Inline asm"
1364 // Add this to the output node.
1365 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3),
1367 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1372 // Add the flag input back if present.
1373 if (e != InOps.size())
1374 Ops.push_back(InOps.back());
1377 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1380 static SDNode *findFlagUse(SDNode *N) {
1381 unsigned FlagResNo = N->getNumValues()-1;
1382 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1383 SDUse &Use = I.getUse();
1384 if (Use.getResNo() == FlagResNo)
1385 return Use.getUser();
1390 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1391 /// This function recursively traverses up the operand chain, ignoring
1393 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1394 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1395 bool IgnoreChains) {
1396 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1397 // greater than all of its (recursive) operands. If we scan to a point where
1398 // 'use' is smaller than the node we're scanning for, then we know we will
1401 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1402 // happen because we scan down to newly selected nodes in the case of flag
1404 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1407 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1408 // won't fail if we scan it again.
1409 if (!Visited.insert(Use))
1412 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1413 // Ignore chain uses, they are validated by HandleMergeInputChains.
1414 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1417 SDNode *N = Use->getOperand(i).getNode();
1419 if (Use == ImmedUse || Use == Root)
1420 continue; // We are not looking for immediate use.
1425 // Traverse up the operand chain.
1426 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1432 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1433 /// operand node N of U during instruction selection that starts at Root.
1434 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1435 SDNode *Root) const {
1436 if (OptLevel == CodeGenOpt::None) return false;
1437 return N.hasOneUse();
1440 /// IsLegalToFold - Returns true if the specific operand node N of
1441 /// U can be folded during instruction selection that starts at Root.
1442 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1443 bool IgnoreChains) const {
1444 if (OptLevel == CodeGenOpt::None) return false;
1446 // If Root use can somehow reach N through a path that that doesn't contain
1447 // U then folding N would create a cycle. e.g. In the following
1448 // diagram, Root can reach N through X. If N is folded into into Root, then
1449 // X is both a predecessor and a successor of U.
1460 // * indicates nodes to be folded together.
1462 // If Root produces a flag, then it gets (even more) interesting. Since it
1463 // will be "glued" together with its flag use in the scheduler, we need to
1464 // check if it might reach N.
1483 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1484 // (call it Fold), then X is a predecessor of FU and a successor of
1485 // Fold. But since Fold and FU are flagged together, this will create
1486 // a cycle in the scheduling graph.
1488 // If the node has flags, walk down the graph to the "lowest" node in the
1490 EVT VT = Root->getValueType(Root->getNumValues()-1);
1491 while (VT == MVT::Flag) {
1492 SDNode *FU = findFlagUse(Root);
1496 VT = Root->getValueType(Root->getNumValues()-1);
1498 // If our query node has a flag result with a use, we've walked up it. If
1499 // the user (which has already been selected) has a chain or indirectly uses
1500 // the chain, our WalkChainUsers predicate will not consider it. Because of
1501 // this, we cannot ignore chains in this predicate.
1502 IgnoreChains = false;
1506 SmallPtrSet<SDNode*, 16> Visited;
1507 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1510 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1511 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1512 SelectInlineAsmMemoryOperands(Ops);
1514 std::vector<EVT> VTs;
1515 VTs.push_back(MVT::Other);
1516 VTs.push_back(MVT::Flag);
1517 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1518 VTs, &Ops[0], Ops.size());
1520 return New.getNode();
1523 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1524 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1527 /// GetVBR - decode a vbr encoding whose top bit is set.
1528 ALWAYS_INLINE static uint64_t
1529 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1530 assert(Val >= 128 && "Not a VBR");
1531 Val &= 127; // Remove first vbr bit.
1536 NextBits = MatcherTable[Idx++];
1537 Val |= (NextBits&127) << Shift;
1539 } while (NextBits & 128);
1545 /// UpdateChainsAndFlags - When a match is complete, this method updates uses of
1546 /// interior flag and chain results to use the new flag and chain results.
1547 void SelectionDAGISel::
1548 UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
1549 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1551 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched,
1552 bool isMorphNodeTo) {
1553 SmallVector<SDNode*, 4> NowDeadNodes;
1555 ISelUpdater ISU(ISelPosition);
1557 // Now that all the normal results are replaced, we replace the chain and
1558 // flag results if present.
1559 if (!ChainNodesMatched.empty()) {
1560 assert(InputChain.getNode() != 0 &&
1561 "Matched input chains but didn't produce a chain");
1562 // Loop over all of the nodes we matched that produced a chain result.
1563 // Replace all the chain results with the final chain we ended up with.
1564 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1565 SDNode *ChainNode = ChainNodesMatched[i];
1567 // If this node was already deleted, don't look at it.
1568 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1571 // Don't replace the results of the root node if we're doing a
1573 if (ChainNode == NodeToMatch && isMorphNodeTo)
1576 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1577 if (ChainVal.getValueType() == MVT::Flag)
1578 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1579 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1580 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1582 // If the node became dead and we haven't already seen it, delete it.
1583 if (ChainNode->use_empty() &&
1584 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1585 NowDeadNodes.push_back(ChainNode);
1589 // If the result produces a flag, update any flag results in the matched
1590 // pattern with the flag result.
1591 if (InputFlag.getNode() != 0) {
1592 // Handle any interior nodes explicitly marked.
1593 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) {
1594 SDNode *FRN = FlagResultNodesMatched[i];
1596 // If this node was already deleted, don't look at it.
1597 if (FRN->getOpcode() == ISD::DELETED_NODE)
1600 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag &&
1601 "Doesn't have a flag result");
1602 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1605 // If the node became dead and we haven't already seen it, delete it.
1606 if (FRN->use_empty() &&
1607 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1608 NowDeadNodes.push_back(FRN);
1612 if (!NowDeadNodes.empty())
1613 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1615 DEBUG(errs() << "ISEL: Match complete!\n");
1621 CR_LeadsToInteriorNode
1624 /// WalkChainUsers - Walk down the users of the specified chained node that is
1625 /// part of the pattern we're matching, looking at all of the users we find.
1626 /// This determines whether something is an interior node, whether we have a
1627 /// non-pattern node in between two pattern nodes (which prevent folding because
1628 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1629 /// between pattern nodes (in which case the TF becomes part of the pattern).
1631 /// The walk we do here is guaranteed to be small because we quickly get down to
1632 /// already selected nodes "below" us.
1634 WalkChainUsers(SDNode *ChainedNode,
1635 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1636 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1637 ChainResult Result = CR_Simple;
1639 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1640 E = ChainedNode->use_end(); UI != E; ++UI) {
1641 // Make sure the use is of the chain, not some other value we produce.
1642 if (UI.getUse().getValueType() != MVT::Other) continue;
1646 // If we see an already-selected machine node, then we've gone beyond the
1647 // pattern that we're selecting down into the already selected chunk of the
1649 if (User->isMachineOpcode() ||
1650 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1653 if (User->getOpcode() == ISD::CopyToReg ||
1654 User->getOpcode() == ISD::CopyFromReg ||
1655 User->getOpcode() == ISD::INLINEASM ||
1656 User->getOpcode() == ISD::EH_LABEL) {
1657 // If their node ID got reset to -1 then they've already been selected.
1658 // Treat them like a MachineOpcode.
1659 if (User->getNodeId() == -1)
1663 // If we have a TokenFactor, we handle it specially.
1664 if (User->getOpcode() != ISD::TokenFactor) {
1665 // If the node isn't a token factor and isn't part of our pattern, then it
1666 // must be a random chained node in between two nodes we're selecting.
1667 // This happens when we have something like:
1672 // Because we structurally match the load/store as a read/modify/write,
1673 // but the call is chained between them. We cannot fold in this case
1674 // because it would induce a cycle in the graph.
1675 if (!std::count(ChainedNodesInPattern.begin(),
1676 ChainedNodesInPattern.end(), User))
1677 return CR_InducesCycle;
1679 // Otherwise we found a node that is part of our pattern. For example in:
1683 // This would happen when we're scanning down from the load and see the
1684 // store as a user. Record that there is a use of ChainedNode that is
1685 // part of the pattern and keep scanning uses.
1686 Result = CR_LeadsToInteriorNode;
1687 InteriorChainedNodes.push_back(User);
1691 // If we found a TokenFactor, there are two cases to consider: first if the
1692 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1693 // uses of the TF are in our pattern) we just want to ignore it. Second,
1694 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1700 // | \ DAG's like cheese
1703 // [TokenFactor] [Op]
1710 // In this case, the TokenFactor becomes part of our match and we rewrite it
1711 // as a new TokenFactor.
1713 // To distinguish these two cases, do a recursive walk down the uses.
1714 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1716 // If the uses of the TokenFactor are just already-selected nodes, ignore
1717 // it, it is "below" our pattern.
1719 case CR_InducesCycle:
1720 // If the uses of the TokenFactor lead to nodes that are not part of our
1721 // pattern that are not selected, folding would turn this into a cycle,
1723 return CR_InducesCycle;
1724 case CR_LeadsToInteriorNode:
1725 break; // Otherwise, keep processing.
1728 // Okay, we know we're in the interesting interior case. The TokenFactor
1729 // is now going to be considered part of the pattern so that we rewrite its
1730 // uses (it may have uses that are not part of the pattern) with the
1731 // ultimate chain result of the generated code. We will also add its chain
1732 // inputs as inputs to the ultimate TokenFactor we create.
1733 Result = CR_LeadsToInteriorNode;
1734 ChainedNodesInPattern.push_back(User);
1735 InteriorChainedNodes.push_back(User);
1742 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1743 /// operation for when the pattern matched at least one node with a chains. The
1744 /// input vector contains a list of all of the chained nodes that we match. We
1745 /// must determine if this is a valid thing to cover (i.e. matching it won't
1746 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1747 /// be used as the input node chain for the generated nodes.
1749 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1750 SelectionDAG *CurDAG) {
1751 // Walk all of the chained nodes we've matched, recursively scanning down the
1752 // users of the chain result. This adds any TokenFactor nodes that are caught
1753 // in between chained nodes to the chained and interior nodes list.
1754 SmallVector<SDNode*, 3> InteriorChainedNodes;
1755 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1756 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1757 InteriorChainedNodes) == CR_InducesCycle)
1758 return SDValue(); // Would induce a cycle.
1761 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1762 // that we are interested in. Form our input TokenFactor node.
1763 SmallVector<SDValue, 3> InputChains;
1764 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1765 // Add the input chain of this node to the InputChains list (which will be
1766 // the operands of the generated TokenFactor) if it's not an interior node.
1767 SDNode *N = ChainNodesMatched[i];
1768 if (N->getOpcode() != ISD::TokenFactor) {
1769 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1772 // Otherwise, add the input chain.
1773 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1774 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1775 InputChains.push_back(InChain);
1779 // If we have a token factor, we want to add all inputs of the token factor
1780 // that are not part of the pattern we're matching.
1781 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1782 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1783 N->getOperand(op).getNode()))
1784 InputChains.push_back(N->getOperand(op));
1789 if (InputChains.size() == 1)
1790 return InputChains[0];
1791 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1792 MVT::Other, &InputChains[0], InputChains.size());
1795 /// MorphNode - Handle morphing a node in place for the selector.
1796 SDNode *SelectionDAGISel::
1797 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1798 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1799 // It is possible we're using MorphNodeTo to replace a node with no
1800 // normal results with one that has a normal result (or we could be
1801 // adding a chain) and the input could have flags and chains as well.
1802 // In this case we need to shift the operands down.
1803 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1804 // than the old isel though.
1805 int OldFlagResultNo = -1, OldChainResultNo = -1;
1807 unsigned NTMNumResults = Node->getNumValues();
1808 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) {
1809 OldFlagResultNo = NTMNumResults-1;
1810 if (NTMNumResults != 1 &&
1811 Node->getValueType(NTMNumResults-2) == MVT::Other)
1812 OldChainResultNo = NTMNumResults-2;
1813 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1814 OldChainResultNo = NTMNumResults-1;
1816 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1817 // that this deletes operands of the old node that become dead.
1818 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1820 // MorphNodeTo can operate in two ways: if an existing node with the
1821 // specified operands exists, it can just return it. Otherwise, it
1822 // updates the node in place to have the requested operands.
1824 // If we updated the node in place, reset the node ID. To the isel,
1825 // this should be just like a newly allocated machine node.
1829 unsigned ResNumResults = Res->getNumValues();
1830 // Move the flag if needed.
1831 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 &&
1832 (unsigned)OldFlagResultNo != ResNumResults-1)
1833 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo),
1834 SDValue(Res, ResNumResults-1));
1836 if ((EmitNodeInfo & OPFL_FlagOutput) != 0)
1839 // Move the chain reference if needed.
1840 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1841 (unsigned)OldChainResultNo != ResNumResults-1)
1842 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1843 SDValue(Res, ResNumResults-1));
1845 // Otherwise, no replacement happened because the node already exists. Replace
1846 // Uses of the old node with the new one.
1848 CurDAG->ReplaceAllUsesWith(Node, Res);
1853 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1854 ALWAYS_INLINE static bool
1855 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1856 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) {
1857 // Accept if it is exactly the same as a previously recorded node.
1858 unsigned RecNo = MatcherTable[MatcherIndex++];
1859 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1860 return N == RecordedNodes[RecNo];
1863 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1864 ALWAYS_INLINE static bool
1865 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1866 SelectionDAGISel &SDISel) {
1867 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1870 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1871 ALWAYS_INLINE static bool
1872 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1873 SelectionDAGISel &SDISel, SDNode *N) {
1874 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1877 ALWAYS_INLINE static bool
1878 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1880 uint16_t Opc = MatcherTable[MatcherIndex++];
1881 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1882 return N->getOpcode() == Opc;
1885 ALWAYS_INLINE static bool
1886 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1887 SDValue N, const TargetLowering &TLI) {
1888 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1889 if (N.getValueType() == VT) return true;
1891 // Handle the case when VT is iPTR.
1892 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1895 ALWAYS_INLINE static bool
1896 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1897 SDValue N, const TargetLowering &TLI,
1899 if (ChildNo >= N.getNumOperands())
1900 return false; // Match fails if out of range child #.
1901 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1905 ALWAYS_INLINE static bool
1906 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1908 return cast<CondCodeSDNode>(N)->get() ==
1909 (ISD::CondCode)MatcherTable[MatcherIndex++];
1912 ALWAYS_INLINE static bool
1913 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1914 SDValue N, const TargetLowering &TLI) {
1915 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1916 if (cast<VTSDNode>(N)->getVT() == VT)
1919 // Handle the case when VT is iPTR.
1920 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1923 ALWAYS_INLINE static bool
1924 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1926 int64_t Val = MatcherTable[MatcherIndex++];
1928 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1930 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1931 return C != 0 && C->getSExtValue() == Val;
1934 ALWAYS_INLINE static bool
1935 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1936 SDValue N, SelectionDAGISel &SDISel) {
1937 int64_t Val = MatcherTable[MatcherIndex++];
1939 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1941 if (N->getOpcode() != ISD::AND) return false;
1943 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1944 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1947 ALWAYS_INLINE static bool
1948 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1949 SDValue N, SelectionDAGISel &SDISel) {
1950 int64_t Val = MatcherTable[MatcherIndex++];
1952 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1954 if (N->getOpcode() != ISD::OR) return false;
1956 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1957 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1960 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1961 /// scope, evaluate the current node. If the current predicate is known to
1962 /// fail, set Result=true and return anything. If the current predicate is
1963 /// known to pass, set Result=false and return the MatcherIndex to continue
1964 /// with. If the current predicate is unknown, set Result=false and return the
1965 /// MatcherIndex to continue with.
1966 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1967 unsigned Index, SDValue N,
1968 bool &Result, SelectionDAGISel &SDISel,
1969 SmallVectorImpl<SDValue> &RecordedNodes){
1970 switch (Table[Index++]) {
1973 return Index-1; // Could not evaluate this predicate.
1974 case SelectionDAGISel::OPC_CheckSame:
1975 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1977 case SelectionDAGISel::OPC_CheckPatternPredicate:
1978 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1980 case SelectionDAGISel::OPC_CheckPredicate:
1981 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1983 case SelectionDAGISel::OPC_CheckOpcode:
1984 Result = !::CheckOpcode(Table, Index, N.getNode());
1986 case SelectionDAGISel::OPC_CheckType:
1987 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1989 case SelectionDAGISel::OPC_CheckChild0Type:
1990 case SelectionDAGISel::OPC_CheckChild1Type:
1991 case SelectionDAGISel::OPC_CheckChild2Type:
1992 case SelectionDAGISel::OPC_CheckChild3Type:
1993 case SelectionDAGISel::OPC_CheckChild4Type:
1994 case SelectionDAGISel::OPC_CheckChild5Type:
1995 case SelectionDAGISel::OPC_CheckChild6Type:
1996 case SelectionDAGISel::OPC_CheckChild7Type:
1997 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1998 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
2000 case SelectionDAGISel::OPC_CheckCondCode:
2001 Result = !::CheckCondCode(Table, Index, N);
2003 case SelectionDAGISel::OPC_CheckValueType:
2004 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2006 case SelectionDAGISel::OPC_CheckInteger:
2007 Result = !::CheckInteger(Table, Index, N);
2009 case SelectionDAGISel::OPC_CheckAndImm:
2010 Result = !::CheckAndImm(Table, Index, N, SDISel);
2012 case SelectionDAGISel::OPC_CheckOrImm:
2013 Result = !::CheckOrImm(Table, Index, N, SDISel);
2020 /// FailIndex - If this match fails, this is the index to continue with.
2023 /// NodeStack - The node stack when the scope was formed.
2024 SmallVector<SDValue, 4> NodeStack;
2026 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2027 unsigned NumRecordedNodes;
2029 /// NumMatchedMemRefs - The number of matched memref entries.
2030 unsigned NumMatchedMemRefs;
2032 /// InputChain/InputFlag - The current chain/flag
2033 SDValue InputChain, InputFlag;
2035 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2036 bool HasChainNodesMatched, HasFlagResultNodesMatched;
2039 SDNode *SelectionDAGISel::
2040 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2041 unsigned TableSize) {
2042 // FIXME: Should these even be selected? Handle these cases in the caller?
2043 switch (NodeToMatch->getOpcode()) {
2046 case ISD::EntryToken: // These nodes remain the same.
2047 case ISD::BasicBlock:
2049 //case ISD::VALUETYPE:
2050 //case ISD::CONDCODE:
2051 case ISD::HANDLENODE:
2052 case ISD::TargetConstant:
2053 case ISD::TargetConstantFP:
2054 case ISD::TargetConstantPool:
2055 case ISD::TargetFrameIndex:
2056 case ISD::TargetExternalSymbol:
2057 case ISD::TargetBlockAddress:
2058 case ISD::TargetJumpTable:
2059 case ISD::TargetGlobalTLSAddress:
2060 case ISD::TargetGlobalAddress:
2061 case ISD::TokenFactor:
2062 case ISD::CopyFromReg:
2063 case ISD::CopyToReg:
2065 NodeToMatch->setNodeId(-1); // Mark selected.
2067 case ISD::AssertSext:
2068 case ISD::AssertZext:
2069 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2070 NodeToMatch->getOperand(0));
2072 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2073 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2076 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2078 // Set up the node stack with NodeToMatch as the only node on the stack.
2079 SmallVector<SDValue, 8> NodeStack;
2080 SDValue N = SDValue(NodeToMatch, 0);
2081 NodeStack.push_back(N);
2083 // MatchScopes - Scopes used when matching, if a match failure happens, this
2084 // indicates where to continue checking.
2085 SmallVector<MatchScope, 8> MatchScopes;
2087 // RecordedNodes - This is the set of nodes that have been recorded by the
2089 SmallVector<SDValue, 8> RecordedNodes;
2091 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2093 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2095 // These are the current input chain and flag for use when generating nodes.
2096 // Various Emit operations change these. For example, emitting a copytoreg
2097 // uses and updates these.
2098 SDValue InputChain, InputFlag;
2100 // ChainNodesMatched - If a pattern matches nodes that have input/output
2101 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2102 // which ones they are. The result is captured into this list so that we can
2103 // update the chain results when the pattern is complete.
2104 SmallVector<SDNode*, 3> ChainNodesMatched;
2105 SmallVector<SDNode*, 3> FlagResultNodesMatched;
2107 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2108 NodeToMatch->dump(CurDAG);
2111 // Determine where to start the interpreter. Normally we start at opcode #0,
2112 // but if the state machine starts with an OPC_SwitchOpcode, then we
2113 // accelerate the first lookup (which is guaranteed to be hot) with the
2114 // OpcodeOffset table.
2115 unsigned MatcherIndex = 0;
2117 if (!OpcodeOffset.empty()) {
2118 // Already computed the OpcodeOffset table, just index into it.
2119 if (N.getOpcode() < OpcodeOffset.size())
2120 MatcherIndex = OpcodeOffset[N.getOpcode()];
2121 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2123 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2124 // Otherwise, the table isn't computed, but the state machine does start
2125 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2126 // is the first time we're selecting an instruction.
2129 // Get the size of this case.
2130 unsigned CaseSize = MatcherTable[Idx++];
2132 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2133 if (CaseSize == 0) break;
2135 // Get the opcode, add the index to the table.
2136 uint16_t Opc = MatcherTable[Idx++];
2137 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2138 if (Opc >= OpcodeOffset.size())
2139 OpcodeOffset.resize((Opc+1)*2);
2140 OpcodeOffset[Opc] = Idx;
2144 // Okay, do the lookup for the first opcode.
2145 if (N.getOpcode() < OpcodeOffset.size())
2146 MatcherIndex = OpcodeOffset[N.getOpcode()];
2150 assert(MatcherIndex < TableSize && "Invalid index");
2152 unsigned CurrentOpcodeIndex = MatcherIndex;
2154 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2157 // Okay, the semantics of this operation are that we should push a scope
2158 // then evaluate the first child. However, pushing a scope only to have
2159 // the first check fail (which then pops it) is inefficient. If we can
2160 // determine immediately that the first check (or first several) will
2161 // immediately fail, don't even bother pushing a scope for them.
2165 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2166 if (NumToSkip & 128)
2167 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2168 // Found the end of the scope with no match.
2169 if (NumToSkip == 0) {
2174 FailIndex = MatcherIndex+NumToSkip;
2176 unsigned MatcherIndexOfPredicate = MatcherIndex;
2177 (void)MatcherIndexOfPredicate; // silence warning.
2179 // If we can't evaluate this predicate without pushing a scope (e.g. if
2180 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2181 // push the scope and evaluate the full predicate chain.
2183 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2184 Result, *this, RecordedNodes);
2188 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2189 << "index " << MatcherIndexOfPredicate
2190 << ", continuing at " << FailIndex << "\n");
2191 ++NumDAGIselRetries;
2193 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2194 // move to the next case.
2195 MatcherIndex = FailIndex;
2198 // If the whole scope failed to match, bail.
2199 if (FailIndex == 0) break;
2201 // Push a MatchScope which indicates where to go if the first child fails
2203 MatchScope NewEntry;
2204 NewEntry.FailIndex = FailIndex;
2205 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2206 NewEntry.NumRecordedNodes = RecordedNodes.size();
2207 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2208 NewEntry.InputChain = InputChain;
2209 NewEntry.InputFlag = InputFlag;
2210 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2211 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty();
2212 MatchScopes.push_back(NewEntry);
2215 case OPC_RecordNode:
2216 // Remember this node, it may end up being an operand in the pattern.
2217 RecordedNodes.push_back(N);
2220 case OPC_RecordChild0: case OPC_RecordChild1:
2221 case OPC_RecordChild2: case OPC_RecordChild3:
2222 case OPC_RecordChild4: case OPC_RecordChild5:
2223 case OPC_RecordChild6: case OPC_RecordChild7: {
2224 unsigned ChildNo = Opcode-OPC_RecordChild0;
2225 if (ChildNo >= N.getNumOperands())
2226 break; // Match fails if out of range child #.
2228 RecordedNodes.push_back(N->getOperand(ChildNo));
2231 case OPC_RecordMemRef:
2232 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2235 case OPC_CaptureFlagInput:
2236 // If the current node has an input flag, capture it in InputFlag.
2237 if (N->getNumOperands() != 0 &&
2238 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag)
2239 InputFlag = N->getOperand(N->getNumOperands()-1);
2242 case OPC_MoveChild: {
2243 unsigned ChildNo = MatcherTable[MatcherIndex++];
2244 if (ChildNo >= N.getNumOperands())
2245 break; // Match fails if out of range child #.
2246 N = N.getOperand(ChildNo);
2247 NodeStack.push_back(N);
2251 case OPC_MoveParent:
2252 // Pop the current node off the NodeStack.
2253 NodeStack.pop_back();
2254 assert(!NodeStack.empty() && "Node stack imbalance!");
2255 N = NodeStack.back();
2259 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2261 case OPC_CheckPatternPredicate:
2262 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2264 case OPC_CheckPredicate:
2265 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2269 case OPC_CheckComplexPat: {
2270 unsigned CPNum = MatcherTable[MatcherIndex++];
2271 unsigned RecNo = MatcherTable[MatcherIndex++];
2272 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2273 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum,
2278 case OPC_CheckOpcode:
2279 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2283 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2286 case OPC_SwitchOpcode: {
2287 unsigned CurNodeOpcode = N.getOpcode();
2288 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2291 // Get the size of this case.
2292 CaseSize = MatcherTable[MatcherIndex++];
2294 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2295 if (CaseSize == 0) break;
2297 uint16_t Opc = MatcherTable[MatcherIndex++];
2298 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2300 // If the opcode matches, then we will execute this case.
2301 if (CurNodeOpcode == Opc)
2304 // Otherwise, skip over this case.
2305 MatcherIndex += CaseSize;
2308 // If no cases matched, bail out.
2309 if (CaseSize == 0) break;
2311 // Otherwise, execute the case we found.
2312 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2313 << " to " << MatcherIndex << "\n");
2317 case OPC_SwitchType: {
2318 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy;
2319 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2322 // Get the size of this case.
2323 CaseSize = MatcherTable[MatcherIndex++];
2325 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2326 if (CaseSize == 0) break;
2328 MVT::SimpleValueType CaseVT =
2329 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2330 if (CaseVT == MVT::iPTR)
2331 CaseVT = TLI.getPointerTy().SimpleTy;
2333 // If the VT matches, then we will execute this case.
2334 if (CurNodeVT == CaseVT)
2337 // Otherwise, skip over this case.
2338 MatcherIndex += CaseSize;
2341 // If no cases matched, bail out.
2342 if (CaseSize == 0) break;
2344 // Otherwise, execute the case we found.
2345 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2346 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2349 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2350 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2351 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2352 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2353 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2354 Opcode-OPC_CheckChild0Type))
2357 case OPC_CheckCondCode:
2358 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2360 case OPC_CheckValueType:
2361 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2363 case OPC_CheckInteger:
2364 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2366 case OPC_CheckAndImm:
2367 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2369 case OPC_CheckOrImm:
2370 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2373 case OPC_CheckFoldableChainNode: {
2374 assert(NodeStack.size() != 1 && "No parent node");
2375 // Verify that all intermediate nodes between the root and this one have
2377 bool HasMultipleUses = false;
2378 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2379 if (!NodeStack[i].hasOneUse()) {
2380 HasMultipleUses = true;
2383 if (HasMultipleUses) break;
2385 // Check to see that the target thinks this is profitable to fold and that
2386 // we can fold it without inducing cycles in the graph.
2387 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2389 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2390 NodeToMatch, true/*We validate our own chains*/))
2395 case OPC_EmitInteger: {
2396 MVT::SimpleValueType VT =
2397 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2398 int64_t Val = MatcherTable[MatcherIndex++];
2400 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2401 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT));
2404 case OPC_EmitRegister: {
2405 MVT::SimpleValueType VT =
2406 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2407 unsigned RegNo = MatcherTable[MatcherIndex++];
2408 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT));
2412 case OPC_EmitConvertToTarget: {
2413 // Convert from IMM/FPIMM to target version.
2414 unsigned RecNo = MatcherTable[MatcherIndex++];
2415 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2416 SDValue Imm = RecordedNodes[RecNo];
2418 if (Imm->getOpcode() == ISD::Constant) {
2419 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2420 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2421 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2422 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2423 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2426 RecordedNodes.push_back(Imm);
2430 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2431 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2432 // These are space-optimized forms of OPC_EmitMergeInputChains.
2433 assert(InputChain.getNode() == 0 &&
2434 "EmitMergeInputChains should be the first chain producing node");
2435 assert(ChainNodesMatched.empty() &&
2436 "Should only have one EmitMergeInputChains per match");
2438 // Read all of the chained nodes.
2439 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2440 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2441 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2443 // FIXME: What if other value results of the node have uses not matched
2445 if (ChainNodesMatched.back() != NodeToMatch &&
2446 !RecordedNodes[RecNo].hasOneUse()) {
2447 ChainNodesMatched.clear();
2451 // Merge the input chains if they are not intra-pattern references.
2452 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2454 if (InputChain.getNode() == 0)
2455 break; // Failed to merge.
2459 case OPC_EmitMergeInputChains: {
2460 assert(InputChain.getNode() == 0 &&
2461 "EmitMergeInputChains should be the first chain producing node");
2462 // This node gets a list of nodes we matched in the input that have
2463 // chains. We want to token factor all of the input chains to these nodes
2464 // together. However, if any of the input chains is actually one of the
2465 // nodes matched in this pattern, then we have an intra-match reference.
2466 // Ignore these because the newly token factored chain should not refer to
2468 unsigned NumChains = MatcherTable[MatcherIndex++];
2469 assert(NumChains != 0 && "Can't TF zero chains");
2471 assert(ChainNodesMatched.empty() &&
2472 "Should only have one EmitMergeInputChains per match");
2474 // Read all of the chained nodes.
2475 for (unsigned i = 0; i != NumChains; ++i) {
2476 unsigned RecNo = MatcherTable[MatcherIndex++];
2477 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2478 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2480 // FIXME: What if other value results of the node have uses not matched
2482 if (ChainNodesMatched.back() != NodeToMatch &&
2483 !RecordedNodes[RecNo].hasOneUse()) {
2484 ChainNodesMatched.clear();
2489 // If the inner loop broke out, the match fails.
2490 if (ChainNodesMatched.empty())
2493 // Merge the input chains if they are not intra-pattern references.
2494 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2496 if (InputChain.getNode() == 0)
2497 break; // Failed to merge.
2502 case OPC_EmitCopyToReg: {
2503 unsigned RecNo = MatcherTable[MatcherIndex++];
2504 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2505 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2507 if (InputChain.getNode() == 0)
2508 InputChain = CurDAG->getEntryNode();
2510 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2511 DestPhysReg, RecordedNodes[RecNo],
2514 InputFlag = InputChain.getValue(1);
2518 case OPC_EmitNodeXForm: {
2519 unsigned XFormNo = MatcherTable[MatcherIndex++];
2520 unsigned RecNo = MatcherTable[MatcherIndex++];
2521 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2522 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo));
2527 case OPC_MorphNodeTo: {
2528 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2529 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2530 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2531 // Get the result VT list.
2532 unsigned NumVTs = MatcherTable[MatcherIndex++];
2533 SmallVector<EVT, 4> VTs;
2534 for (unsigned i = 0; i != NumVTs; ++i) {
2535 MVT::SimpleValueType VT =
2536 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2537 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2541 if (EmitNodeInfo & OPFL_Chain)
2542 VTs.push_back(MVT::Other);
2543 if (EmitNodeInfo & OPFL_FlagOutput)
2544 VTs.push_back(MVT::Flag);
2546 // This is hot code, so optimize the two most common cases of 1 and 2
2549 if (VTs.size() == 1)
2550 VTList = CurDAG->getVTList(VTs[0]);
2551 else if (VTs.size() == 2)
2552 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2554 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2556 // Get the operand list.
2557 unsigned NumOps = MatcherTable[MatcherIndex++];
2558 SmallVector<SDValue, 8> Ops;
2559 for (unsigned i = 0; i != NumOps; ++i) {
2560 unsigned RecNo = MatcherTable[MatcherIndex++];
2562 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2564 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2565 Ops.push_back(RecordedNodes[RecNo]);
2568 // If there are variadic operands to add, handle them now.
2569 if (EmitNodeInfo & OPFL_VariadicInfo) {
2570 // Determine the start index to copy from.
2571 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2572 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2573 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2574 "Invalid variadic node");
2575 // Copy all of the variadic operands, not including a potential flag
2577 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2579 SDValue V = NodeToMatch->getOperand(i);
2580 if (V.getValueType() == MVT::Flag) break;
2585 // If this has chain/flag inputs, add them.
2586 if (EmitNodeInfo & OPFL_Chain)
2587 Ops.push_back(InputChain);
2588 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0)
2589 Ops.push_back(InputFlag);
2593 if (Opcode != OPC_MorphNodeTo) {
2594 // If this is a normal EmitNode command, just create the new node and
2595 // add the results to the RecordedNodes list.
2596 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2597 VTList, Ops.data(), Ops.size());
2599 // Add all the non-flag/non-chain results to the RecordedNodes list.
2600 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2601 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
2602 RecordedNodes.push_back(SDValue(Res, i));
2606 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2610 // If the node had chain/flag results, update our notion of the current
2612 if (EmitNodeInfo & OPFL_FlagOutput) {
2613 InputFlag = SDValue(Res, VTs.size()-1);
2614 if (EmitNodeInfo & OPFL_Chain)
2615 InputChain = SDValue(Res, VTs.size()-2);
2616 } else if (EmitNodeInfo & OPFL_Chain)
2617 InputChain = SDValue(Res, VTs.size()-1);
2619 // If the OPFL_MemRefs flag is set on this node, slap all of the
2620 // accumulated memrefs onto it.
2622 // FIXME: This is vastly incorrect for patterns with multiple outputs
2623 // instructions that access memory and for ComplexPatterns that match
2625 if (EmitNodeInfo & OPFL_MemRefs) {
2626 MachineSDNode::mmo_iterator MemRefs =
2627 MF->allocateMemRefsArray(MatchedMemRefs.size());
2628 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2629 cast<MachineSDNode>(Res)
2630 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2634 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2635 << " node: "; Res->dump(CurDAG); errs() << "\n");
2637 // If this was a MorphNodeTo then we're completely done!
2638 if (Opcode == OPC_MorphNodeTo) {
2639 // Update chain and flag uses.
2640 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2641 InputFlag, FlagResultNodesMatched, true);
2648 case OPC_MarkFlagResults: {
2649 unsigned NumNodes = MatcherTable[MatcherIndex++];
2651 // Read and remember all the flag-result nodes.
2652 for (unsigned i = 0; i != NumNodes; ++i) {
2653 unsigned RecNo = MatcherTable[MatcherIndex++];
2655 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2657 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2658 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2663 case OPC_CompleteMatch: {
2664 // The match has been completed, and any new nodes (if any) have been
2665 // created. Patch up references to the matched dag to use the newly
2667 unsigned NumResults = MatcherTable[MatcherIndex++];
2669 for (unsigned i = 0; i != NumResults; ++i) {
2670 unsigned ResSlot = MatcherTable[MatcherIndex++];
2672 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2674 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2675 SDValue Res = RecordedNodes[ResSlot];
2677 assert(i < NodeToMatch->getNumValues() &&
2678 NodeToMatch->getValueType(i) != MVT::Other &&
2679 NodeToMatch->getValueType(i) != MVT::Flag &&
2680 "Invalid number of results to complete!");
2681 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2682 NodeToMatch->getValueType(i) == MVT::iPTR ||
2683 Res.getValueType() == MVT::iPTR ||
2684 NodeToMatch->getValueType(i).getSizeInBits() ==
2685 Res.getValueType().getSizeInBits()) &&
2686 "invalid replacement");
2687 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2690 // If the root node defines a flag, add it to the flag nodes to update
2692 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag)
2693 FlagResultNodesMatched.push_back(NodeToMatch);
2695 // Update chain and flag uses.
2696 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2697 InputFlag, FlagResultNodesMatched, false);
2699 assert(NodeToMatch->use_empty() &&
2700 "Didn't replace all uses of the node?");
2702 // FIXME: We just return here, which interacts correctly with SelectRoot
2703 // above. We should fix this to not return an SDNode* anymore.
2708 // If the code reached this point, then the match failed. See if there is
2709 // another child to try in the current 'Scope', otherwise pop it until we
2710 // find a case to check.
2711 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2712 ++NumDAGIselRetries;
2714 if (MatchScopes.empty()) {
2715 CannotYetSelect(NodeToMatch);
2719 // Restore the interpreter state back to the point where the scope was
2721 MatchScope &LastScope = MatchScopes.back();
2722 RecordedNodes.resize(LastScope.NumRecordedNodes);
2724 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2725 N = NodeStack.back();
2727 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2728 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2729 MatcherIndex = LastScope.FailIndex;
2731 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2733 InputChain = LastScope.InputChain;
2734 InputFlag = LastScope.InputFlag;
2735 if (!LastScope.HasChainNodesMatched)
2736 ChainNodesMatched.clear();
2737 if (!LastScope.HasFlagResultNodesMatched)
2738 FlagResultNodesMatched.clear();
2740 // Check to see what the offset is at the new MatcherIndex. If it is zero
2741 // we have reached the end of this scope, otherwise we have another child
2742 // in the current scope to try.
2743 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2744 if (NumToSkip & 128)
2745 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2747 // If we have another child in this scope to match, update FailIndex and
2749 if (NumToSkip != 0) {
2750 LastScope.FailIndex = MatcherIndex+NumToSkip;
2754 // End of this scope, pop it and try the next child in the containing
2756 MatchScopes.pop_back();
2763 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2765 raw_string_ostream Msg(msg);
2766 Msg << "Cannot yet select: ";
2768 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2769 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2770 N->getOpcode() != ISD::INTRINSIC_VOID) {
2771 N->printrFull(Msg, CurDAG);
2773 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2775 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2776 if (iid < Intrinsic::num_intrinsics)
2777 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2778 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2779 Msg << "target intrinsic %" << TII->getName(iid);
2781 Msg << "unknown intrinsic #" << iid;
2783 llvm_report_error(Msg.str());
2786 char SelectionDAGISel::ID = 0;