1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "ScheduleDAGSDNodes.h"
17 #include "SelectionDAGBuilder.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/CFG.h"
23 #include "llvm/Analysis/TargetTransformInfo.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/GCMetadata.h"
27 #include "llvm/CodeGen/GCStrategy.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
34 #include "llvm/CodeGen/SchedulerRegistry.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/DebugInfo.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/InlineAsm.h"
40 #include "llvm/IR/Instructions.h"
41 #include "llvm/IR/IntrinsicInst.h"
42 #include "llvm/IR/Intrinsics.h"
43 #include "llvm/IR/LLVMContext.h"
44 #include "llvm/IR/Module.h"
45 #include "llvm/Support/Compiler.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/ErrorHandling.h"
48 #include "llvm/Support/Timer.h"
49 #include "llvm/Support/raw_ostream.h"
50 #include "llvm/Target/TargetInstrInfo.h"
51 #include "llvm/Target/TargetIntrinsicInfo.h"
52 #include "llvm/Target/TargetLibraryInfo.h"
53 #include "llvm/Target/TargetLowering.h"
54 #include "llvm/Target/TargetMachine.h"
55 #include "llvm/Target/TargetOptions.h"
56 #include "llvm/Target/TargetRegisterInfo.h"
57 #include "llvm/Target/TargetSubtargetInfo.h"
58 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
62 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
63 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
64 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
65 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
66 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
67 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
68 STATISTIC(NumFastIselFailLowerArguments,
69 "Number of entry blocks where fast isel failed to lower arguments");
73 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
74 cl::desc("Enable extra verbose messages in the \"fast\" "
75 "instruction selector"));
78 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
79 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
80 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
81 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
82 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
83 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
84 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
86 // Standard binary operators...
87 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
88 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
89 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
90 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
91 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
92 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
93 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
94 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
95 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
96 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
97 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
98 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
100 // Logical operators...
101 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
102 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
103 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
105 // Memory instructions...
106 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
107 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
108 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
109 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
110 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
111 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
112 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
114 // Convert instructions...
115 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
116 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
117 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
118 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
119 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
120 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
121 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
122 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
123 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
124 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
125 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
126 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
128 // Other instructions...
129 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
130 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
131 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
132 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
133 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
134 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
135 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
136 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
137 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
138 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
139 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
140 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
141 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
142 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
143 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
147 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
148 cl::desc("Enable verbose messages in the \"fast\" "
149 "instruction selector"));
151 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
152 cl::desc("Enable abort calls when \"fast\" instruction selection "
153 "fails to lower an instruction"));
155 EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden,
156 cl::desc("Enable abort calls when \"fast\" instruction selection "
157 "fails to lower a formal argument"));
161 cl::desc("use Machine Branch Probability Info"),
162 cl::init(true), cl::Hidden);
166 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
167 cl::desc("Pop up a window to show dags before the first "
168 "dag combine pass"));
170 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
171 cl::desc("Pop up a window to show dags before legalize types"));
173 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
174 cl::desc("Pop up a window to show dags before legalize"));
176 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
177 cl::desc("Pop up a window to show dags before the second "
178 "dag combine pass"));
180 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
181 cl::desc("Pop up a window to show dags before the post legalize types"
182 " dag combine pass"));
184 ViewISelDAGs("view-isel-dags", cl::Hidden,
185 cl::desc("Pop up a window to show isel dags as they are selected"));
187 ViewSchedDAGs("view-sched-dags", cl::Hidden,
188 cl::desc("Pop up a window to show sched dags as they are processed"));
190 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
191 cl::desc("Pop up a window to show SUnit dags after they are processed"));
193 static const bool ViewDAGCombine1 = false,
194 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
195 ViewDAGCombine2 = false,
196 ViewDAGCombineLT = false,
197 ViewISelDAGs = false, ViewSchedDAGs = false,
198 ViewSUnitDAGs = false;
201 //===---------------------------------------------------------------------===//
203 /// RegisterScheduler class - Track the registration of instruction schedulers.
205 //===---------------------------------------------------------------------===//
206 MachinePassRegistry RegisterScheduler::Registry;
208 //===---------------------------------------------------------------------===//
210 /// ISHeuristic command line option for instruction schedulers.
212 //===---------------------------------------------------------------------===//
213 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
214 RegisterPassParser<RegisterScheduler> >
215 ISHeuristic("pre-RA-sched",
216 cl::init(&createDefaultScheduler),
217 cl::desc("Instruction schedulers available (before register"
220 static RegisterScheduler
221 defaultListDAGScheduler("default", "Best scheduler for the target",
222 createDefaultScheduler);
225 //===--------------------------------------------------------------------===//
226 /// createDefaultScheduler - This creates an instruction scheduler appropriate
228 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
229 CodeGenOpt::Level OptLevel) {
230 const TargetLowering *TLI = IS->getTargetLowering();
231 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>();
233 if (OptLevel == CodeGenOpt::None || ST.useMachineScheduler() ||
234 TLI->getSchedulingPreference() == Sched::Source)
235 return createSourceListDAGScheduler(IS, OptLevel);
236 if (TLI->getSchedulingPreference() == Sched::RegPressure)
237 return createBURRListDAGScheduler(IS, OptLevel);
238 if (TLI->getSchedulingPreference() == Sched::Hybrid)
239 return createHybridListDAGScheduler(IS, OptLevel);
240 if (TLI->getSchedulingPreference() == Sched::VLIW)
241 return createVLIWDAGScheduler(IS, OptLevel);
242 assert(TLI->getSchedulingPreference() == Sched::ILP &&
243 "Unknown sched type!");
244 return createILPListDAGScheduler(IS, OptLevel);
248 // EmitInstrWithCustomInserter - This method should be implemented by targets
249 // that mark instructions with the 'usesCustomInserter' flag. These
250 // instructions are special in various ways, which require special support to
251 // insert. The specified MachineInstr is created but not inserted into any
252 // basic blocks, and this method is called to expand it into a sequence of
253 // instructions, potentially also creating new basic blocks and control flow.
254 // When new basic blocks are inserted and the edges from MBB to its successors
255 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
258 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
259 MachineBasicBlock *MBB) const {
261 dbgs() << "If a target marks an instruction with "
262 "'usesCustomInserter', it must implement "
263 "TargetLowering::EmitInstrWithCustomInserter!";
268 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
269 SDNode *Node) const {
270 assert(!MI->hasPostISelHook() &&
271 "If a target marks an instruction with 'hasPostISelHook', "
272 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
275 //===----------------------------------------------------------------------===//
276 // SelectionDAGISel code
277 //===----------------------------------------------------------------------===//
279 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
280 CodeGenOpt::Level OL) :
281 MachineFunctionPass(ID), TM(tm),
282 FuncInfo(new FunctionLoweringInfo(TM)),
283 CurDAG(new SelectionDAG(tm, OL)),
284 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
288 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
289 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
290 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
291 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry());
294 SelectionDAGISel::~SelectionDAGISel() {
300 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
301 AU.addRequired<AliasAnalysis>();
302 AU.addPreserved<AliasAnalysis>();
303 AU.addRequired<GCModuleInfo>();
304 AU.addPreserved<GCModuleInfo>();
305 AU.addRequired<TargetLibraryInfo>();
306 if (UseMBPI && OptLevel != CodeGenOpt::None)
307 AU.addRequired<BranchProbabilityInfo>();
308 MachineFunctionPass::getAnalysisUsage(AU);
311 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
312 /// may trap on it. In this case we have to split the edge so that the path
313 /// through the predecessor block that doesn't go to the phi block doesn't
314 /// execute the possibly trapping instruction.
316 /// This is required for correctness, so it must be done at -O0.
318 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
319 // Loop for blocks with phi nodes.
320 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
321 PHINode *PN = dyn_cast<PHINode>(BB->begin());
322 if (PN == 0) continue;
325 // For each block with a PHI node, check to see if any of the input values
326 // are potentially trapping constant expressions. Constant expressions are
327 // the only potentially trapping value that can occur as the argument to a
329 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
330 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
331 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
332 if (CE == 0 || !CE->canTrap()) continue;
334 // The only case we have to worry about is when the edge is critical.
335 // Since this block has a PHI Node, we assume it has multiple input
336 // edges: check to see if the pred has multiple successors.
337 BasicBlock *Pred = PN->getIncomingBlock(i);
338 if (Pred->getTerminator()->getNumSuccessors() == 1)
341 // Okay, we have to split this edge.
342 SplitCriticalEdge(Pred->getTerminator(),
343 GetSuccessorNumber(Pred, BB), SDISel, true);
349 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
350 // Do some sanity-checking on the command-line options.
351 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
352 "-fast-isel-verbose requires -fast-isel");
353 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
354 "-fast-isel-abort requires -fast-isel");
356 const Function &Fn = *mf.getFunction();
357 const TargetInstrInfo &TII = *TM.getInstrInfo();
358 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
361 RegInfo = &MF->getRegInfo();
362 AA = &getAnalysis<AliasAnalysis>();
363 LibInfo = &getAnalysis<TargetLibraryInfo>();
364 TTI = getAnalysisIfAvailable<TargetTransformInfo>();
365 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
367 TargetSubtargetInfo &ST =
368 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>());
369 ST.resetSubtargetFeatures(MF);
370 TM.resetTargetOptions(MF);
372 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
374 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
376 CurDAG->init(*MF, TTI);
377 FuncInfo->set(Fn, *MF);
379 if (UseMBPI && OptLevel != CodeGenOpt::None)
380 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
384 SDB->init(GFI, *AA, LibInfo);
386 MF->setHasMSInlineAsm(false);
387 SelectAllBasicBlocks(Fn);
389 // If the first basic block in the function has live ins that need to be
390 // copied into vregs, emit the copies into the top of the block before
391 // emitting the code for the block.
392 MachineBasicBlock *EntryMBB = MF->begin();
393 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
395 DenseMap<unsigned, unsigned> LiveInMap;
396 if (!FuncInfo->ArgDbgValues.empty())
397 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
398 E = RegInfo->livein_end(); LI != E; ++LI)
400 LiveInMap.insert(std::make_pair(LI->first, LI->second));
402 // Insert DBG_VALUE instructions for function arguments to the entry block.
403 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
404 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
405 bool hasFI = MI->getOperand(0).isFI();
406 unsigned Reg = hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
407 if (TargetRegisterInfo::isPhysicalRegister(Reg))
408 EntryMBB->insert(EntryMBB->begin(), MI);
410 MachineInstr *Def = RegInfo->getVRegDef(Reg);
412 MachineBasicBlock::iterator InsertPos = Def;
413 // FIXME: VR def may not be in entry block.
414 Def->getParent()->insert(llvm::next(InsertPos), MI);
416 DEBUG(dbgs() << "Dropping debug info for dead vreg"
417 << TargetRegisterInfo::virtReg2Index(Reg) << "\n");
420 // If Reg is live-in then update debug info to track its copy in a vreg.
421 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
422 if (LDI != LiveInMap.end()) {
423 assert(!hasFI && "There's no handling of frame pointer updating here yet "
425 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
426 MachineBasicBlock::iterator InsertPos = Def;
427 const MDNode *Variable =
428 MI->getOperand(MI->getNumOperands()-1).getMetadata();
429 bool IsIndirect = MI->isIndirectDebugValue();
430 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
431 // Def is never a terminator here, so it is ok to increment InsertPos.
432 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
433 TII.get(TargetOpcode::DBG_VALUE),
435 LDI->second, Offset, Variable);
437 // If this vreg is directly copied into an exported register then
438 // that COPY instructions also need DBG_VALUE, if it is the only
439 // user of LDI->second.
440 MachineInstr *CopyUseMI = NULL;
441 for (MachineRegisterInfo::use_iterator
442 UI = RegInfo->use_begin(LDI->second);
443 MachineInstr *UseMI = UI.skipInstruction();) {
444 if (UseMI->isDebugValue()) continue;
445 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
446 CopyUseMI = UseMI; continue;
448 // Otherwise this is another use or second copy use.
449 CopyUseMI = NULL; break;
452 MachineInstr *NewMI =
453 BuildMI(*MF, CopyUseMI->getDebugLoc(),
454 TII.get(TargetOpcode::DBG_VALUE),
456 CopyUseMI->getOperand(0).getReg(),
458 MachineBasicBlock::iterator Pos = CopyUseMI;
459 EntryMBB->insertAfter(Pos, NewMI);
464 // Determine if there are any calls in this machine function.
465 MachineFrameInfo *MFI = MF->getFrameInfo();
466 for (MachineFunction::const_iterator I = MF->begin(), E = MF->end(); I != E;
469 if (MFI->hasCalls() && MF->hasMSInlineAsm())
472 const MachineBasicBlock *MBB = I;
473 for (MachineBasicBlock::const_iterator II = MBB->begin(), IE = MBB->end();
475 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
476 if ((MCID.isCall() && !MCID.isReturn()) ||
477 II->isStackAligningInlineAsm()) {
478 MFI->setHasCalls(true);
480 if (II->isMSInlineAsm()) {
481 MF->setHasMSInlineAsm(true);
486 // Determine if there is a call to setjmp in the machine function.
487 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
489 // Replace forward-declared registers with the registers containing
490 // the desired value.
491 MachineRegisterInfo &MRI = MF->getRegInfo();
492 for (DenseMap<unsigned, unsigned>::iterator
493 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
495 unsigned From = I->first;
496 unsigned To = I->second;
497 // If To is also scheduled to be replaced, find what its ultimate
500 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
504 // Make sure the new register has a sufficiently constrained register class.
505 if (TargetRegisterInfo::isVirtualRegister(From) &&
506 TargetRegisterInfo::isVirtualRegister(To))
507 MRI.constrainRegClass(To, MRI.getRegClass(From));
509 MRI.replaceRegWith(From, To);
512 // Freeze the set of reserved registers now that MachineFrameInfo has been
513 // set up. All the information required by getReservedRegs() should be
515 MRI.freezeReservedRegs(*MF);
517 // Release function-specific state. SDB and CurDAG are already cleared
524 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
525 BasicBlock::const_iterator End,
527 // Lower all of the non-terminator instructions. If a call is emitted
528 // as a tail call, cease emitting nodes for this block. Terminators
529 // are handled below.
530 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
533 // Make sure the root of the DAG is up-to-date.
534 CurDAG->setRoot(SDB->getControlRoot());
535 HadTailCall = SDB->HasTailCall;
538 // Final step, emit the lowered DAG as machine code.
542 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
543 SmallPtrSet<SDNode*, 128> VisitedNodes;
544 SmallVector<SDNode*, 128> Worklist;
546 Worklist.push_back(CurDAG->getRoot().getNode());
552 SDNode *N = Worklist.pop_back_val();
554 // If we've already seen this node, ignore it.
555 if (!VisitedNodes.insert(N))
558 // Otherwise, add all chain operands to the worklist.
559 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
560 if (N->getOperand(i).getValueType() == MVT::Other)
561 Worklist.push_back(N->getOperand(i).getNode());
563 // If this is a CopyToReg with a vreg dest, process it.
564 if (N->getOpcode() != ISD::CopyToReg)
567 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
568 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
571 // Ignore non-scalar or non-integer values.
572 SDValue Src = N->getOperand(2);
573 EVT SrcVT = Src.getValueType();
574 if (!SrcVT.isInteger() || SrcVT.isVector())
577 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
578 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne);
579 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
580 } while (!Worklist.empty());
583 void SelectionDAGISel::CodeGenAndEmitDAG() {
584 std::string GroupName;
585 if (TimePassesIsEnabled)
586 GroupName = "Instruction Selection and Scheduling";
587 std::string BlockName;
588 int BlockNumber = -1;
591 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
592 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
596 BlockNumber = FuncInfo->MBB->getNumber();
597 BlockName = MF->getName().str() + ":" +
598 FuncInfo->MBB->getBasicBlock()->getName().str();
600 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
601 << " '" << BlockName << "'\n"; CurDAG->dump());
603 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
605 // Run the DAG combiner in pre-legalize mode.
607 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
608 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
611 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
612 << " '" << BlockName << "'\n"; CurDAG->dump());
614 // Second step, hack on the DAG until it only uses operations and types that
615 // the target supports.
616 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
621 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
622 Changed = CurDAG->LegalizeTypes();
625 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
626 << " '" << BlockName << "'\n"; CurDAG->dump());
629 if (ViewDAGCombineLT)
630 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
632 // Run the DAG combiner in post-type-legalize mode.
634 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
635 TimePassesIsEnabled);
636 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
639 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
640 << " '" << BlockName << "'\n"; CurDAG->dump());
645 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
646 Changed = CurDAG->LegalizeVectors();
651 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
652 CurDAG->LegalizeTypes();
655 if (ViewDAGCombineLT)
656 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
658 // Run the DAG combiner in post-type-legalize mode.
660 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
661 TimePassesIsEnabled);
662 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
665 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
666 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
669 CurDAG->NewNodesMustHaveLegalTypes = true;
671 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
674 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
678 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
679 << " '" << BlockName << "'\n"; CurDAG->dump());
681 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
683 // Run the DAG combiner in post-legalize mode.
685 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
686 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
689 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
690 << " '" << BlockName << "'\n"; CurDAG->dump());
692 if (OptLevel != CodeGenOpt::None)
693 ComputeLiveOutVRegInfo();
695 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
697 // Third, instruction select all of the operations to machine code, adding the
698 // code to the MachineBasicBlock.
700 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
701 DoInstructionSelection();
704 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
705 << " '" << BlockName << "'\n"; CurDAG->dump());
707 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
709 // Schedule machine code.
710 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
712 NamedRegionTimer T("Instruction Scheduling", GroupName,
713 TimePassesIsEnabled);
714 Scheduler->Run(CurDAG, FuncInfo->MBB);
717 if (ViewSUnitDAGs) Scheduler->viewGraph();
719 // Emit machine code to BB. This can change 'BB' to the last block being
721 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
723 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
725 // FuncInfo->InsertPt is passed by reference and set to the end of the
726 // scheduled instructions.
727 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
730 // If the block was split, make sure we update any references that are used to
731 // update PHI nodes later on.
732 if (FirstMBB != LastMBB)
733 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
735 // Free the scheduler state.
737 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
738 TimePassesIsEnabled);
742 // Free the SelectionDAG state, now that we're finished with it.
747 /// ISelUpdater - helper class to handle updates of the instruction selection
749 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
750 SelectionDAG::allnodes_iterator &ISelPosition;
752 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
753 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
755 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
756 /// deleted is the current ISelPosition node, update ISelPosition.
758 virtual void NodeDeleted(SDNode *N, SDNode *E) {
759 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
763 } // end anonymous namespace
765 void SelectionDAGISel::DoInstructionSelection() {
766 DEBUG(dbgs() << "===== Instruction selection begins: BB#"
767 << FuncInfo->MBB->getNumber()
768 << " '" << FuncInfo->MBB->getName() << "'\n");
772 // Select target instructions for the DAG.
774 // Number all nodes with a topological order and set DAGSize.
775 DAGSize = CurDAG->AssignTopologicalOrder();
777 // Create a dummy node (which is not added to allnodes), that adds
778 // a reference to the root node, preventing it from being deleted,
779 // and tracking any changes of the root.
780 HandleSDNode Dummy(CurDAG->getRoot());
781 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
784 // Make sure that ISelPosition gets properly updated when nodes are deleted
785 // in calls made from this function.
786 ISelUpdater ISU(*CurDAG, ISelPosition);
788 // The AllNodes list is now topological-sorted. Visit the
789 // nodes by starting at the end of the list (the root of the
790 // graph) and preceding back toward the beginning (the entry
792 while (ISelPosition != CurDAG->allnodes_begin()) {
793 SDNode *Node = --ISelPosition;
794 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
795 // but there are currently some corner cases that it misses. Also, this
796 // makes it theoretically possible to disable the DAGCombiner.
797 if (Node->use_empty())
800 SDNode *ResNode = Select(Node);
802 // FIXME: This is pretty gross. 'Select' should be changed to not return
803 // anything at all and this code should be nuked with a tactical strike.
805 // If node should not be replaced, continue with the next one.
806 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
810 ReplaceUses(Node, ResNode);
813 // If after the replacement this node is not used any more,
814 // remove this dead node.
815 if (Node->use_empty()) // Don't delete EntryToken, etc.
816 CurDAG->RemoveDeadNode(Node);
819 CurDAG->setRoot(Dummy.getValue());
822 DEBUG(dbgs() << "===== Instruction selection ends:\n");
824 PostprocessISelDAG();
827 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
828 /// do other setup for EH landing-pad blocks.
829 void SelectionDAGISel::PrepareEHLandingPad() {
830 MachineBasicBlock *MBB = FuncInfo->MBB;
832 // Add a label to mark the beginning of the landing pad. Deletion of the
833 // landing pad can thus be detected via the MachineModuleInfo.
834 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
836 // Assign the call site to the landing pad's begin label.
837 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
839 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
840 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
843 // Mark exception register as live in.
844 const TargetLowering *TLI = getTargetLowering();
845 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy());
846 if (unsigned Reg = TLI->getExceptionPointerRegister())
847 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
849 // Mark exception selector register as live in.
850 if (unsigned Reg = TLI->getExceptionSelectorRegister())
851 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC);
854 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
855 /// side-effect free and is either dead or folded into a generated instruction.
856 /// Return false if it needs to be emitted.
857 static bool isFoldedOrDeadInstruction(const Instruction *I,
858 FunctionLoweringInfo *FuncInfo) {
859 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
860 !isa<TerminatorInst>(I) && // Terminators aren't folded.
861 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
862 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
863 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
867 // Collect per Instruction statistics for fast-isel misses. Only those
868 // instructions that cause the bail are accounted for. It does not account for
869 // instructions higher in the block. Thus, summing the per instructions stats
870 // will not add up to what is reported by NumFastIselFailures.
871 static void collectFailStats(const Instruction *I) {
872 switch (I->getOpcode()) {
873 default: assert (0 && "<Invalid operator> ");
876 case Instruction::Ret: NumFastIselFailRet++; return;
877 case Instruction::Br: NumFastIselFailBr++; return;
878 case Instruction::Switch: NumFastIselFailSwitch++; return;
879 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
880 case Instruction::Invoke: NumFastIselFailInvoke++; return;
881 case Instruction::Resume: NumFastIselFailResume++; return;
882 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
884 // Standard binary operators...
885 case Instruction::Add: NumFastIselFailAdd++; return;
886 case Instruction::FAdd: NumFastIselFailFAdd++; return;
887 case Instruction::Sub: NumFastIselFailSub++; return;
888 case Instruction::FSub: NumFastIselFailFSub++; return;
889 case Instruction::Mul: NumFastIselFailMul++; return;
890 case Instruction::FMul: NumFastIselFailFMul++; return;
891 case Instruction::UDiv: NumFastIselFailUDiv++; return;
892 case Instruction::SDiv: NumFastIselFailSDiv++; return;
893 case Instruction::FDiv: NumFastIselFailFDiv++; return;
894 case Instruction::URem: NumFastIselFailURem++; return;
895 case Instruction::SRem: NumFastIselFailSRem++; return;
896 case Instruction::FRem: NumFastIselFailFRem++; return;
898 // Logical operators...
899 case Instruction::And: NumFastIselFailAnd++; return;
900 case Instruction::Or: NumFastIselFailOr++; return;
901 case Instruction::Xor: NumFastIselFailXor++; return;
903 // Memory instructions...
904 case Instruction::Alloca: NumFastIselFailAlloca++; return;
905 case Instruction::Load: NumFastIselFailLoad++; return;
906 case Instruction::Store: NumFastIselFailStore++; return;
907 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
908 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
909 case Instruction::Fence: NumFastIselFailFence++; return;
910 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
912 // Convert instructions...
913 case Instruction::Trunc: NumFastIselFailTrunc++; return;
914 case Instruction::ZExt: NumFastIselFailZExt++; return;
915 case Instruction::SExt: NumFastIselFailSExt++; return;
916 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
917 case Instruction::FPExt: NumFastIselFailFPExt++; return;
918 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
919 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
920 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
921 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
922 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
923 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
924 case Instruction::BitCast: NumFastIselFailBitCast++; return;
926 // Other instructions...
927 case Instruction::ICmp: NumFastIselFailICmp++; return;
928 case Instruction::FCmp: NumFastIselFailFCmp++; return;
929 case Instruction::PHI: NumFastIselFailPHI++; return;
930 case Instruction::Select: NumFastIselFailSelect++; return;
931 case Instruction::Call: NumFastIselFailCall++; return;
932 case Instruction::Shl: NumFastIselFailShl++; return;
933 case Instruction::LShr: NumFastIselFailLShr++; return;
934 case Instruction::AShr: NumFastIselFailAShr++; return;
935 case Instruction::VAArg: NumFastIselFailVAArg++; return;
936 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
937 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
938 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
939 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
940 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
941 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
946 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
947 // Initialize the Fast-ISel state, if needed.
948 FastISel *FastIS = 0;
949 if (TM.Options.EnableFastISel)
950 FastIS = getTargetLowering()->createFastISel(*FuncInfo, LibInfo);
952 // Iterate over all basic blocks in the function.
953 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
954 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
955 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
956 const BasicBlock *LLVMBB = *I;
958 if (OptLevel != CodeGenOpt::None) {
959 bool AllPredsVisited = true;
960 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
962 if (!FuncInfo->VisitedBBs.count(*PI)) {
963 AllPredsVisited = false;
968 if (AllPredsVisited) {
969 for (BasicBlock::const_iterator I = LLVMBB->begin();
970 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
971 FuncInfo->ComputePHILiveOutRegInfo(PN);
973 for (BasicBlock::const_iterator I = LLVMBB->begin();
974 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
975 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
978 FuncInfo->VisitedBBs.insert(LLVMBB);
981 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
982 BasicBlock::const_iterator const End = LLVMBB->end();
983 BasicBlock::const_iterator BI = End;
985 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
986 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
988 // Setup an EH landing-pad block.
989 FuncInfo->ExceptionPointerVirtReg = 0;
990 FuncInfo->ExceptionSelectorVirtReg = 0;
991 if (FuncInfo->MBB->isLandingPad())
992 PrepareEHLandingPad();
994 // Before doing SelectionDAG ISel, see if FastISel has been requested.
996 FastIS->startNewBlock();
998 // Emit code for any incoming arguments. This must happen before
999 // beginning FastISel on the entry block.
1000 if (LLVMBB == &Fn.getEntryBlock()) {
1003 // Lower any arguments needed in this block if this is the entry block.
1004 if (!FastIS->LowerArguments()) {
1005 // Fast isel failed to lower these arguments
1006 ++NumFastIselFailLowerArguments;
1007 if (EnableFastISelAbortArgs)
1008 llvm_unreachable("FastISel didn't lower all arguments");
1010 // Use SelectionDAG argument lowering
1012 CurDAG->setRoot(SDB->getControlRoot());
1014 CodeGenAndEmitDAG();
1017 // If we inserted any instructions at the beginning, make a note of
1018 // where they are, so we can be sure to emit subsequent instructions
1020 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1021 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
1023 FastIS->setLastLocalValue(0);
1026 unsigned NumFastIselRemaining = std::distance(Begin, End);
1027 // Do FastISel on as many instructions as possible.
1028 for (; BI != Begin; --BI) {
1029 const Instruction *Inst = llvm::prior(BI);
1031 // If we no longer require this instruction, skip it.
1032 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1033 --NumFastIselRemaining;
1037 // Bottom-up: reset the insert pos at the top, after any local-value
1039 FastIS->recomputeInsertPt();
1041 // Try to select the instruction with FastISel.
1042 if (FastIS->SelectInstruction(Inst)) {
1043 --NumFastIselRemaining;
1044 ++NumFastIselSuccess;
1045 // If fast isel succeeded, skip over all the folded instructions, and
1046 // then see if there is a load right before the selected instructions.
1047 // Try to fold the load if so.
1048 const Instruction *BeforeInst = Inst;
1049 while (BeforeInst != Begin) {
1050 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst));
1051 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1054 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1055 BeforeInst->hasOneUse() &&
1056 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) {
1057 // If we succeeded, don't re-select the load.
1058 BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
1059 --NumFastIselRemaining;
1060 ++NumFastIselSuccess;
1066 if (EnableFastISelVerbose2)
1067 collectFailStats(Inst);
1070 // Then handle certain instructions as single-LLVM-Instruction blocks.
1071 if (isa<CallInst>(Inst)) {
1073 if (EnableFastISelVerbose || EnableFastISelAbort) {
1074 dbgs() << "FastISel missed call: ";
1078 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1079 unsigned &R = FuncInfo->ValueMap[Inst];
1081 R = FuncInfo->CreateRegs(Inst->getType());
1084 bool HadTailCall = false;
1085 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1086 SelectBasicBlock(Inst, BI, HadTailCall);
1088 // If the call was emitted as a tail call, we're done with the block.
1089 // We also need to delete any previously emitted instructions.
1091 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1096 // Recompute NumFastIselRemaining as Selection DAG instruction
1097 // selection may have handled the call, input args, etc.
1098 unsigned RemainingNow = std::distance(Begin, BI);
1099 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1100 NumFastIselRemaining = RemainingNow;
1104 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
1105 // Don't abort, and use a different message for terminator misses.
1106 NumFastIselFailures += NumFastIselRemaining;
1107 if (EnableFastISelVerbose || EnableFastISelAbort) {
1108 dbgs() << "FastISel missed terminator: ";
1112 NumFastIselFailures += NumFastIselRemaining;
1113 if (EnableFastISelVerbose || EnableFastISelAbort) {
1114 dbgs() << "FastISel miss: ";
1117 if (EnableFastISelAbort)
1118 // The "fast" selector couldn't handle something and bailed.
1119 // For the purpose of debugging, just abort.
1120 llvm_unreachable("FastISel didn't select the entire block");
1125 FastIS->recomputeInsertPt();
1127 // Lower any arguments needed in this block if this is the entry block.
1128 if (LLVMBB == &Fn.getEntryBlock()) {
1137 ++NumFastIselBlocks;
1140 // Run SelectionDAG instruction selection on the remainder of the block
1141 // not handled by FastISel. If FastISel is not run, this is the entire
1144 SelectBasicBlock(Begin, BI, HadTailCall);
1148 FuncInfo->PHINodesToUpdate.clear();
1152 SDB->clearDanglingDebugInfo();
1153 SDB->SPDescriptor.resetPerFunctionState();
1156 /// Given that the input MI is before a partial terminator sequence TSeq, return
1157 /// true if M + TSeq also a partial terminator sequence.
1159 /// A Terminator sequence is a sequence of MachineInstrs which at this point in
1160 /// lowering copy vregs into physical registers, which are then passed into
1161 /// terminator instructors so we can satisfy ABI constraints. A partial
1162 /// terminator sequence is an improper subset of a terminator sequence (i.e. it
1163 /// may be the whole terminator sequence).
1164 static bool MIIsInTerminatorSequence(const MachineInstr *MI) {
1165 // If we do not have a copy or an implicit def, we return true if and only if
1166 // MI is a debug value.
1167 if (!MI->isCopy() && !MI->isImplicitDef())
1168 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the
1169 // physical registers if there is debug info associated with the terminator
1170 // of our mbb. We want to include said debug info in our terminator
1171 // sequence, so we return true in that case.
1172 return MI->isDebugValue();
1174 // We have left the terminator sequence if we are not doing one of the
1177 // 1. Copying a vreg into a physical register.
1178 // 2. Copying a vreg into a vreg.
1179 // 3. Defining a register via an implicit def.
1181 // OPI should always be a register definition...
1182 MachineInstr::const_mop_iterator OPI = MI->operands_begin();
1183 if (!OPI->isReg() || !OPI->isDef())
1186 // Defining any register via an implicit def is always ok.
1187 if (MI->isImplicitDef())
1190 // Grab the copy source...
1191 MachineInstr::const_mop_iterator OPI2 = OPI;
1193 assert(OPI2 != MI->operands_end()
1194 && "Should have a copy implying we should have 2 arguments.");
1196 // Make sure that the copy dest is not a vreg when the copy source is a
1197 // physical register.
1198 if (!OPI2->isReg() ||
1199 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) &&
1200 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg())))
1206 /// Find the split point at which to splice the end of BB into its success stack
1207 /// protector check machine basic block.
1209 /// On many platforms, due to ABI constraints, terminators, even before register
1210 /// allocation, use physical registers. This creates an issue for us since
1211 /// physical registers at this point can not travel across basic
1212 /// blocks. Luckily, selectiondag always moves physical registers into vregs
1213 /// when they enter functions and moves them through a sequence of copies back
1214 /// into the physical registers right before the terminator creating a
1215 /// ``Terminator Sequence''. This function is searching for the beginning of the
1216 /// terminator sequence so that we can ensure that we splice off not just the
1217 /// terminator, but additionally the copies that move the vregs into the
1218 /// physical registers.
1219 static MachineBasicBlock::iterator
1220 FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) {
1221 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator();
1223 if (SplitPoint == BB->begin())
1226 MachineBasicBlock::iterator Start = BB->begin();
1227 MachineBasicBlock::iterator Previous = SplitPoint;
1230 while (MIIsInTerminatorSequence(Previous)) {
1231 SplitPoint = Previous;
1232 if (Previous == Start)
1241 SelectionDAGISel::FinishBasicBlock() {
1243 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1244 << FuncInfo->PHINodesToUpdate.size() << "\n";
1245 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1246 dbgs() << "Node " << i << " : ("
1247 << FuncInfo->PHINodesToUpdate[i].first
1248 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1250 const bool MustUpdatePHINodes = SDB->SwitchCases.empty() &&
1251 SDB->JTCases.empty() &&
1252 SDB->BitTestCases.empty();
1254 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1255 // PHI nodes in successors.
1256 if (MustUpdatePHINodes) {
1257 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1258 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1259 assert(PHI->isPHI() &&
1260 "This is not a machine PHI node that we are updating!");
1261 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1263 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1267 // Handle stack protector.
1268 if (SDB->SPDescriptor.shouldEmitStackProtector()) {
1269 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB();
1270 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB();
1272 // Find the split point to split the parent mbb. At the same time copy all
1273 // physical registers used in the tail of parent mbb into virtual registers
1274 // before the split point and back into physical registers after the split
1275 // point. This prevents us needing to deal with Live-ins and many other
1276 // register allocation issues caused by us splitting the parent mbb. The
1277 // register allocator will clean up said virtual copies later on.
1278 MachineBasicBlock::iterator SplitPoint =
1279 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc());
1281 // Splice the terminator of ParentMBB into SuccessMBB.
1282 SuccessMBB->splice(SuccessMBB->end(), ParentMBB,
1286 // Add compare/jump on neq/jump to the parent BB.
1287 FuncInfo->MBB = ParentMBB;
1288 FuncInfo->InsertPt = ParentMBB->end();
1289 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB);
1290 CurDAG->setRoot(SDB->getRoot());
1292 CodeGenAndEmitDAG();
1294 // CodeGen Failure MBB if we have not codegened it yet.
1295 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB();
1296 if (!FailureMBB->size()) {
1297 FuncInfo->MBB = FailureMBB;
1298 FuncInfo->InsertPt = FailureMBB->end();
1299 SDB->visitSPDescriptorFailure(SDB->SPDescriptor);
1300 CurDAG->setRoot(SDB->getRoot());
1302 CodeGenAndEmitDAG();
1305 // Clear the Per-BB State.
1306 SDB->SPDescriptor.resetPerBBState();
1309 // If we updated PHI Nodes, return early.
1310 if (MustUpdatePHINodes)
1313 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1314 // Lower header first, if it wasn't already lowered
1315 if (!SDB->BitTestCases[i].Emitted) {
1316 // Set the current basic block to the mbb we wish to insert the code into
1317 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1318 FuncInfo->InsertPt = FuncInfo->MBB->end();
1320 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1321 CurDAG->setRoot(SDB->getRoot());
1323 CodeGenAndEmitDAG();
1326 uint32_t UnhandledWeight = 0;
1327 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1328 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1330 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1331 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1332 // Set the current basic block to the mbb we wish to insert the code into
1333 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1334 FuncInfo->InsertPt = FuncInfo->MBB->end();
1337 SDB->visitBitTestCase(SDB->BitTestCases[i],
1338 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1340 SDB->BitTestCases[i].Reg,
1341 SDB->BitTestCases[i].Cases[j],
1344 SDB->visitBitTestCase(SDB->BitTestCases[i],
1345 SDB->BitTestCases[i].Default,
1347 SDB->BitTestCases[i].Reg,
1348 SDB->BitTestCases[i].Cases[j],
1352 CurDAG->setRoot(SDB->getRoot());
1354 CodeGenAndEmitDAG();
1358 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1360 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1361 MachineBasicBlock *PHIBB = PHI->getParent();
1362 assert(PHI->isPHI() &&
1363 "This is not a machine PHI node that we are updating!");
1364 // This is "default" BB. We have two jumps to it. From "header" BB and
1365 // from last "case" BB.
1366 if (PHIBB == SDB->BitTestCases[i].Default)
1367 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1368 .addMBB(SDB->BitTestCases[i].Parent)
1369 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1370 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1371 // One of "cases" BB.
1372 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1374 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1375 if (cBB->isSuccessor(PHIBB))
1376 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1380 SDB->BitTestCases.clear();
1382 // If the JumpTable record is filled in, then we need to emit a jump table.
1383 // Updating the PHI nodes is tricky in this case, since we need to determine
1384 // whether the PHI is a successor of the range check MBB or the jump table MBB
1385 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1386 // Lower header first, if it wasn't already lowered
1387 if (!SDB->JTCases[i].first.Emitted) {
1388 // Set the current basic block to the mbb we wish to insert the code into
1389 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1390 FuncInfo->InsertPt = FuncInfo->MBB->end();
1392 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1394 CurDAG->setRoot(SDB->getRoot());
1396 CodeGenAndEmitDAG();
1399 // Set the current basic block to the mbb we wish to insert the code into
1400 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1401 FuncInfo->InsertPt = FuncInfo->MBB->end();
1403 SDB->visitJumpTable(SDB->JTCases[i].second);
1404 CurDAG->setRoot(SDB->getRoot());
1406 CodeGenAndEmitDAG();
1409 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1411 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1412 MachineBasicBlock *PHIBB = PHI->getParent();
1413 assert(PHI->isPHI() &&
1414 "This is not a machine PHI node that we are updating!");
1415 // "default" BB. We can go there only from header BB.
1416 if (PHIBB == SDB->JTCases[i].second.Default)
1417 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1418 .addMBB(SDB->JTCases[i].first.HeaderBB);
1419 // JT BB. Just iterate over successors here
1420 if (FuncInfo->MBB->isSuccessor(PHIBB))
1421 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1424 SDB->JTCases.clear();
1426 // If the switch block involved a branch to one of the actual successors, we
1427 // need to update PHI nodes in that block.
1428 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1429 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1430 assert(PHI->isPHI() &&
1431 "This is not a machine PHI node that we are updating!");
1432 if (FuncInfo->MBB->isSuccessor(PHI->getParent()))
1433 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1436 // If we generated any switch lowering information, build and codegen any
1437 // additional DAGs necessary.
1438 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1439 // Set the current basic block to the mbb we wish to insert the code into
1440 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1441 FuncInfo->InsertPt = FuncInfo->MBB->end();
1443 // Determine the unique successors.
1444 SmallVector<MachineBasicBlock *, 2> Succs;
1445 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1446 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1447 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1449 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1450 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1451 CurDAG->setRoot(SDB->getRoot());
1453 CodeGenAndEmitDAG();
1455 // Remember the last block, now that any splitting is done, for use in
1456 // populating PHI nodes in successors.
1457 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1459 // Handle any PHI nodes in successors of this chunk, as if we were coming
1460 // from the original BB before switch expansion. Note that PHI nodes can
1461 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1462 // handle them the right number of times.
1463 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1464 FuncInfo->MBB = Succs[i];
1465 FuncInfo->InsertPt = FuncInfo->MBB->end();
1466 // FuncInfo->MBB may have been removed from the CFG if a branch was
1468 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1469 for (MachineBasicBlock::iterator
1470 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1471 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1472 MachineInstrBuilder PHI(*MF, MBBI);
1473 // This value for this PHI node is recorded in PHINodesToUpdate.
1474 for (unsigned pn = 0; ; ++pn) {
1475 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1476 "Didn't find PHI entry!");
1477 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1478 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1486 SDB->SwitchCases.clear();
1490 /// Create the scheduler. If a specific scheduler was specified
1491 /// via the SchedulerRegistry, use it, otherwise select the
1492 /// one preferred by the target.
1494 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1495 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1499 RegisterScheduler::setDefault(Ctor);
1502 return Ctor(this, OptLevel);
1505 //===----------------------------------------------------------------------===//
1506 // Helper functions used by the generated instruction selector.
1507 //===----------------------------------------------------------------------===//
1508 // Calls to these methods are generated by tblgen.
1510 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1511 /// the dag combiner simplified the 255, we still want to match. RHS is the
1512 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1513 /// specified in the .td file (e.g. 255).
1514 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1515 int64_t DesiredMaskS) const {
1516 const APInt &ActualMask = RHS->getAPIntValue();
1517 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1519 // If the actual mask exactly matches, success!
1520 if (ActualMask == DesiredMask)
1523 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1524 if (ActualMask.intersects(~DesiredMask))
1527 // Otherwise, the DAG Combiner may have proven that the value coming in is
1528 // either already zero or is not demanded. Check for known zero input bits.
1529 APInt NeededMask = DesiredMask & ~ActualMask;
1530 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1533 // TODO: check to see if missing bits are just not demanded.
1535 // Otherwise, this pattern doesn't match.
1539 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1540 /// the dag combiner simplified the 255, we still want to match. RHS is the
1541 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1542 /// specified in the .td file (e.g. 255).
1543 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1544 int64_t DesiredMaskS) const {
1545 const APInt &ActualMask = RHS->getAPIntValue();
1546 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1548 // If the actual mask exactly matches, success!
1549 if (ActualMask == DesiredMask)
1552 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1553 if (ActualMask.intersects(~DesiredMask))
1556 // Otherwise, the DAG Combiner may have proven that the value coming in is
1557 // either already zero or is not demanded. Check for known zero input bits.
1558 APInt NeededMask = DesiredMask & ~ActualMask;
1560 APInt KnownZero, KnownOne;
1561 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne);
1563 // If all the missing bits in the or are already known to be set, match!
1564 if ((NeededMask & KnownOne) == NeededMask)
1567 // TODO: check to see if missing bits are just not demanded.
1569 // Otherwise, this pattern doesn't match.
1574 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1575 /// by tblgen. Others should not call it.
1576 void SelectionDAGISel::
1577 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1578 std::vector<SDValue> InOps;
1579 std::swap(InOps, Ops);
1581 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1582 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1583 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1584 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1586 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1587 if (InOps[e-1].getValueType() == MVT::Glue)
1588 --e; // Don't process a glue operand if it is here.
1591 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1592 if (!InlineAsm::isMemKind(Flags)) {
1593 // Just skip over this operand, copying the operands verbatim.
1594 Ops.insert(Ops.end(), InOps.begin()+i,
1595 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1596 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1598 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1599 "Memory operand with multiple values?");
1600 // Otherwise, this is a memory operand. Ask the target to select it.
1601 std::vector<SDValue> SelOps;
1602 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1603 report_fatal_error("Could not match memory address. Inline asm"
1606 // Add this to the output node.
1608 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1609 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1610 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1615 // Add the glue input back if present.
1616 if (e != InOps.size())
1617 Ops.push_back(InOps.back());
1620 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1623 static SDNode *findGlueUse(SDNode *N) {
1624 unsigned FlagResNo = N->getNumValues()-1;
1625 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1626 SDUse &Use = I.getUse();
1627 if (Use.getResNo() == FlagResNo)
1628 return Use.getUser();
1633 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1634 /// This function recursively traverses up the operand chain, ignoring
1636 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1637 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1638 bool IgnoreChains) {
1639 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1640 // greater than all of its (recursive) operands. If we scan to a point where
1641 // 'use' is smaller than the node we're scanning for, then we know we will
1644 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1645 // happen because we scan down to newly selected nodes in the case of glue
1647 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1650 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1651 // won't fail if we scan it again.
1652 if (!Visited.insert(Use))
1655 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1656 // Ignore chain uses, they are validated by HandleMergeInputChains.
1657 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1660 SDNode *N = Use->getOperand(i).getNode();
1662 if (Use == ImmedUse || Use == Root)
1663 continue; // We are not looking for immediate use.
1668 // Traverse up the operand chain.
1669 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1675 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1676 /// operand node N of U during instruction selection that starts at Root.
1677 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1678 SDNode *Root) const {
1679 if (OptLevel == CodeGenOpt::None) return false;
1680 return N.hasOneUse();
1683 /// IsLegalToFold - Returns true if the specific operand node N of
1684 /// U can be folded during instruction selection that starts at Root.
1685 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1686 CodeGenOpt::Level OptLevel,
1687 bool IgnoreChains) {
1688 if (OptLevel == CodeGenOpt::None) return false;
1690 // If Root use can somehow reach N through a path that that doesn't contain
1691 // U then folding N would create a cycle. e.g. In the following
1692 // diagram, Root can reach N through X. If N is folded into into Root, then
1693 // X is both a predecessor and a successor of U.
1704 // * indicates nodes to be folded together.
1706 // If Root produces glue, then it gets (even more) interesting. Since it
1707 // will be "glued" together with its glue use in the scheduler, we need to
1708 // check if it might reach N.
1727 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1728 // (call it Fold), then X is a predecessor of GU and a successor of
1729 // Fold. But since Fold and GU are glued together, this will create
1730 // a cycle in the scheduling graph.
1732 // If the node has glue, walk down the graph to the "lowest" node in the
1734 EVT VT = Root->getValueType(Root->getNumValues()-1);
1735 while (VT == MVT::Glue) {
1736 SDNode *GU = findGlueUse(Root);
1740 VT = Root->getValueType(Root->getNumValues()-1);
1742 // If our query node has a glue result with a use, we've walked up it. If
1743 // the user (which has already been selected) has a chain or indirectly uses
1744 // the chain, our WalkChainUsers predicate will not consider it. Because of
1745 // this, we cannot ignore chains in this predicate.
1746 IgnoreChains = false;
1750 SmallPtrSet<SDNode*, 16> Visited;
1751 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1754 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1755 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1756 SelectInlineAsmMemoryOperands(Ops);
1758 EVT VTs[] = { MVT::Other, MVT::Glue };
1759 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N),
1760 VTs, &Ops[0], Ops.size());
1762 return New.getNode();
1765 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1766 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1769 /// GetVBR - decode a vbr encoding whose top bit is set.
1770 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1771 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1772 assert(Val >= 128 && "Not a VBR");
1773 Val &= 127; // Remove first vbr bit.
1778 NextBits = MatcherTable[Idx++];
1779 Val |= (NextBits&127) << Shift;
1781 } while (NextBits & 128);
1787 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1788 /// interior glue and chain results to use the new glue and chain results.
1789 void SelectionDAGISel::
1790 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1791 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1793 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1794 bool isMorphNodeTo) {
1795 SmallVector<SDNode*, 4> NowDeadNodes;
1797 // Now that all the normal results are replaced, we replace the chain and
1798 // glue results if present.
1799 if (!ChainNodesMatched.empty()) {
1800 assert(InputChain.getNode() != 0 &&
1801 "Matched input chains but didn't produce a chain");
1802 // Loop over all of the nodes we matched that produced a chain result.
1803 // Replace all the chain results with the final chain we ended up with.
1804 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1805 SDNode *ChainNode = ChainNodesMatched[i];
1807 // If this node was already deleted, don't look at it.
1808 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1811 // Don't replace the results of the root node if we're doing a
1813 if (ChainNode == NodeToMatch && isMorphNodeTo)
1816 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1817 if (ChainVal.getValueType() == MVT::Glue)
1818 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1819 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1820 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
1822 // If the node became dead and we haven't already seen it, delete it.
1823 if (ChainNode->use_empty() &&
1824 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1825 NowDeadNodes.push_back(ChainNode);
1829 // If the result produces glue, update any glue results in the matched
1830 // pattern with the glue result.
1831 if (InputGlue.getNode() != 0) {
1832 // Handle any interior nodes explicitly marked.
1833 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1834 SDNode *FRN = GlueResultNodesMatched[i];
1836 // If this node was already deleted, don't look at it.
1837 if (FRN->getOpcode() == ISD::DELETED_NODE)
1840 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1841 "Doesn't have a glue result");
1842 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1845 // If the node became dead and we haven't already seen it, delete it.
1846 if (FRN->use_empty() &&
1847 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1848 NowDeadNodes.push_back(FRN);
1852 if (!NowDeadNodes.empty())
1853 CurDAG->RemoveDeadNodes(NowDeadNodes);
1855 DEBUG(dbgs() << "ISEL: Match complete!\n");
1861 CR_LeadsToInteriorNode
1864 /// WalkChainUsers - Walk down the users of the specified chained node that is
1865 /// part of the pattern we're matching, looking at all of the users we find.
1866 /// This determines whether something is an interior node, whether we have a
1867 /// non-pattern node in between two pattern nodes (which prevent folding because
1868 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1869 /// between pattern nodes (in which case the TF becomes part of the pattern).
1871 /// The walk we do here is guaranteed to be small because we quickly get down to
1872 /// already selected nodes "below" us.
1874 WalkChainUsers(const SDNode *ChainedNode,
1875 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1876 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1877 ChainResult Result = CR_Simple;
1879 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1880 E = ChainedNode->use_end(); UI != E; ++UI) {
1881 // Make sure the use is of the chain, not some other value we produce.
1882 if (UI.getUse().getValueType() != MVT::Other) continue;
1886 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1889 // If we see an already-selected machine node, then we've gone beyond the
1890 // pattern that we're selecting down into the already selected chunk of the
1892 unsigned UserOpcode = User->getOpcode();
1893 if (User->isMachineOpcode() ||
1894 UserOpcode == ISD::CopyToReg ||
1895 UserOpcode == ISD::CopyFromReg ||
1896 UserOpcode == ISD::INLINEASM ||
1897 UserOpcode == ISD::EH_LABEL ||
1898 UserOpcode == ISD::LIFETIME_START ||
1899 UserOpcode == ISD::LIFETIME_END) {
1900 // If their node ID got reset to -1 then they've already been selected.
1901 // Treat them like a MachineOpcode.
1902 if (User->getNodeId() == -1)
1906 // If we have a TokenFactor, we handle it specially.
1907 if (User->getOpcode() != ISD::TokenFactor) {
1908 // If the node isn't a token factor and isn't part of our pattern, then it
1909 // must be a random chained node in between two nodes we're selecting.
1910 // This happens when we have something like:
1915 // Because we structurally match the load/store as a read/modify/write,
1916 // but the call is chained between them. We cannot fold in this case
1917 // because it would induce a cycle in the graph.
1918 if (!std::count(ChainedNodesInPattern.begin(),
1919 ChainedNodesInPattern.end(), User))
1920 return CR_InducesCycle;
1922 // Otherwise we found a node that is part of our pattern. For example in:
1926 // This would happen when we're scanning down from the load and see the
1927 // store as a user. Record that there is a use of ChainedNode that is
1928 // part of the pattern and keep scanning uses.
1929 Result = CR_LeadsToInteriorNode;
1930 InteriorChainedNodes.push_back(User);
1934 // If we found a TokenFactor, there are two cases to consider: first if the
1935 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1936 // uses of the TF are in our pattern) we just want to ignore it. Second,
1937 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1943 // | \ DAG's like cheese
1946 // [TokenFactor] [Op]
1953 // In this case, the TokenFactor becomes part of our match and we rewrite it
1954 // as a new TokenFactor.
1956 // To distinguish these two cases, do a recursive walk down the uses.
1957 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1959 // If the uses of the TokenFactor are just already-selected nodes, ignore
1960 // it, it is "below" our pattern.
1962 case CR_InducesCycle:
1963 // If the uses of the TokenFactor lead to nodes that are not part of our
1964 // pattern that are not selected, folding would turn this into a cycle,
1966 return CR_InducesCycle;
1967 case CR_LeadsToInteriorNode:
1968 break; // Otherwise, keep processing.
1971 // Okay, we know we're in the interesting interior case. The TokenFactor
1972 // is now going to be considered part of the pattern so that we rewrite its
1973 // uses (it may have uses that are not part of the pattern) with the
1974 // ultimate chain result of the generated code. We will also add its chain
1975 // inputs as inputs to the ultimate TokenFactor we create.
1976 Result = CR_LeadsToInteriorNode;
1977 ChainedNodesInPattern.push_back(User);
1978 InteriorChainedNodes.push_back(User);
1985 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1986 /// operation for when the pattern matched at least one node with a chains. The
1987 /// input vector contains a list of all of the chained nodes that we match. We
1988 /// must determine if this is a valid thing to cover (i.e. matching it won't
1989 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1990 /// be used as the input node chain for the generated nodes.
1992 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1993 SelectionDAG *CurDAG) {
1994 // Walk all of the chained nodes we've matched, recursively scanning down the
1995 // users of the chain result. This adds any TokenFactor nodes that are caught
1996 // in between chained nodes to the chained and interior nodes list.
1997 SmallVector<SDNode*, 3> InteriorChainedNodes;
1998 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1999 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
2000 InteriorChainedNodes) == CR_InducesCycle)
2001 return SDValue(); // Would induce a cycle.
2004 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
2005 // that we are interested in. Form our input TokenFactor node.
2006 SmallVector<SDValue, 3> InputChains;
2007 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2008 // Add the input chain of this node to the InputChains list (which will be
2009 // the operands of the generated TokenFactor) if it's not an interior node.
2010 SDNode *N = ChainNodesMatched[i];
2011 if (N->getOpcode() != ISD::TokenFactor) {
2012 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
2015 // Otherwise, add the input chain.
2016 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
2017 assert(InChain.getValueType() == MVT::Other && "Not a chain");
2018 InputChains.push_back(InChain);
2022 // If we have a token factor, we want to add all inputs of the token factor
2023 // that are not part of the pattern we're matching.
2024 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
2025 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
2026 N->getOperand(op).getNode()))
2027 InputChains.push_back(N->getOperand(op));
2031 if (InputChains.size() == 1)
2032 return InputChains[0];
2033 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
2034 MVT::Other, &InputChains[0], InputChains.size());
2037 /// MorphNode - Handle morphing a node in place for the selector.
2038 SDNode *SelectionDAGISel::
2039 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
2040 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
2041 // It is possible we're using MorphNodeTo to replace a node with no
2042 // normal results with one that has a normal result (or we could be
2043 // adding a chain) and the input could have glue and chains as well.
2044 // In this case we need to shift the operands down.
2045 // FIXME: This is a horrible hack and broken in obscure cases, no worse
2046 // than the old isel though.
2047 int OldGlueResultNo = -1, OldChainResultNo = -1;
2049 unsigned NTMNumResults = Node->getNumValues();
2050 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
2051 OldGlueResultNo = NTMNumResults-1;
2052 if (NTMNumResults != 1 &&
2053 Node->getValueType(NTMNumResults-2) == MVT::Other)
2054 OldChainResultNo = NTMNumResults-2;
2055 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
2056 OldChainResultNo = NTMNumResults-1;
2058 // Call the underlying SelectionDAG routine to do the transmogrification. Note
2059 // that this deletes operands of the old node that become dead.
2060 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
2062 // MorphNodeTo can operate in two ways: if an existing node with the
2063 // specified operands exists, it can just return it. Otherwise, it
2064 // updates the node in place to have the requested operands.
2066 // If we updated the node in place, reset the node ID. To the isel,
2067 // this should be just like a newly allocated machine node.
2071 unsigned ResNumResults = Res->getNumValues();
2072 // Move the glue if needed.
2073 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
2074 (unsigned)OldGlueResultNo != ResNumResults-1)
2075 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
2076 SDValue(Res, ResNumResults-1));
2078 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
2081 // Move the chain reference if needed.
2082 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
2083 (unsigned)OldChainResultNo != ResNumResults-1)
2084 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2085 SDValue(Res, ResNumResults-1));
2087 // Otherwise, no replacement happened because the node already exists. Replace
2088 // Uses of the old node with the new one.
2090 CurDAG->ReplaceAllUsesWith(Node, Res);
2095 /// CheckSame - Implements OP_CheckSame.
2096 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2097 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2099 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2100 // Accept if it is exactly the same as a previously recorded node.
2101 unsigned RecNo = MatcherTable[MatcherIndex++];
2102 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2103 return N == RecordedNodes[RecNo].first;
2106 /// CheckChildSame - Implements OP_CheckChildXSame.
2107 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2108 CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2110 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes,
2112 if (ChildNo >= N.getNumOperands())
2113 return false; // Match fails if out of range child #.
2114 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo),
2118 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2119 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2120 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2121 const SelectionDAGISel &SDISel) {
2122 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2125 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2126 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2127 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2128 const SelectionDAGISel &SDISel, SDNode *N) {
2129 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2132 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2133 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2135 uint16_t Opc = MatcherTable[MatcherIndex++];
2136 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2137 return N->getOpcode() == Opc;
2140 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2141 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2142 SDValue N, const TargetLowering *TLI) {
2143 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2144 if (N.getValueType() == VT) return true;
2146 // Handle the case when VT is iPTR.
2147 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy();
2150 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2151 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2152 SDValue N, const TargetLowering *TLI,
2154 if (ChildNo >= N.getNumOperands())
2155 return false; // Match fails if out of range child #.
2156 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2159 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2160 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2162 return cast<CondCodeSDNode>(N)->get() ==
2163 (ISD::CondCode)MatcherTable[MatcherIndex++];
2166 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2167 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2168 SDValue N, const TargetLowering *TLI) {
2169 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2170 if (cast<VTSDNode>(N)->getVT() == VT)
2173 // Handle the case when VT is iPTR.
2174 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy();
2177 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2178 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2180 int64_t Val = MatcherTable[MatcherIndex++];
2182 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2184 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2185 return C != 0 && C->getSExtValue() == Val;
2188 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2189 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2190 SDValue N, const SelectionDAGISel &SDISel) {
2191 int64_t Val = MatcherTable[MatcherIndex++];
2193 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2195 if (N->getOpcode() != ISD::AND) return false;
2197 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2198 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2201 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2202 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2203 SDValue N, const SelectionDAGISel &SDISel) {
2204 int64_t Val = MatcherTable[MatcherIndex++];
2206 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2208 if (N->getOpcode() != ISD::OR) return false;
2210 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2211 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2214 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2215 /// scope, evaluate the current node. If the current predicate is known to
2216 /// fail, set Result=true and return anything. If the current predicate is
2217 /// known to pass, set Result=false and return the MatcherIndex to continue
2218 /// with. If the current predicate is unknown, set Result=false and return the
2219 /// MatcherIndex to continue with.
2220 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2221 unsigned Index, SDValue N,
2223 const SelectionDAGISel &SDISel,
2224 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2225 switch (Table[Index++]) {
2228 return Index-1; // Could not evaluate this predicate.
2229 case SelectionDAGISel::OPC_CheckSame:
2230 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2232 case SelectionDAGISel::OPC_CheckChild0Same:
2233 case SelectionDAGISel::OPC_CheckChild1Same:
2234 case SelectionDAGISel::OPC_CheckChild2Same:
2235 case SelectionDAGISel::OPC_CheckChild3Same:
2236 Result = !::CheckChildSame(Table, Index, N, RecordedNodes,
2237 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same);
2239 case SelectionDAGISel::OPC_CheckPatternPredicate:
2240 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2242 case SelectionDAGISel::OPC_CheckPredicate:
2243 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2245 case SelectionDAGISel::OPC_CheckOpcode:
2246 Result = !::CheckOpcode(Table, Index, N.getNode());
2248 case SelectionDAGISel::OPC_CheckType:
2249 Result = !::CheckType(Table, Index, N, SDISel.getTargetLowering());
2251 case SelectionDAGISel::OPC_CheckChild0Type:
2252 case SelectionDAGISel::OPC_CheckChild1Type:
2253 case SelectionDAGISel::OPC_CheckChild2Type:
2254 case SelectionDAGISel::OPC_CheckChild3Type:
2255 case SelectionDAGISel::OPC_CheckChild4Type:
2256 case SelectionDAGISel::OPC_CheckChild5Type:
2257 case SelectionDAGISel::OPC_CheckChild6Type:
2258 case SelectionDAGISel::OPC_CheckChild7Type:
2259 Result = !::CheckChildType(Table, Index, N, SDISel.getTargetLowering(),
2260 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
2262 case SelectionDAGISel::OPC_CheckCondCode:
2263 Result = !::CheckCondCode(Table, Index, N);
2265 case SelectionDAGISel::OPC_CheckValueType:
2266 Result = !::CheckValueType(Table, Index, N, SDISel.getTargetLowering());
2268 case SelectionDAGISel::OPC_CheckInteger:
2269 Result = !::CheckInteger(Table, Index, N);
2271 case SelectionDAGISel::OPC_CheckAndImm:
2272 Result = !::CheckAndImm(Table, Index, N, SDISel);
2274 case SelectionDAGISel::OPC_CheckOrImm:
2275 Result = !::CheckOrImm(Table, Index, N, SDISel);
2283 /// FailIndex - If this match fails, this is the index to continue with.
2286 /// NodeStack - The node stack when the scope was formed.
2287 SmallVector<SDValue, 4> NodeStack;
2289 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2290 unsigned NumRecordedNodes;
2292 /// NumMatchedMemRefs - The number of matched memref entries.
2293 unsigned NumMatchedMemRefs;
2295 /// InputChain/InputGlue - The current chain/glue
2296 SDValue InputChain, InputGlue;
2298 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2299 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2304 SDNode *SelectionDAGISel::
2305 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2306 unsigned TableSize) {
2307 // FIXME: Should these even be selected? Handle these cases in the caller?
2308 switch (NodeToMatch->getOpcode()) {
2311 case ISD::EntryToken: // These nodes remain the same.
2312 case ISD::BasicBlock:
2314 case ISD::RegisterMask:
2315 //case ISD::VALUETYPE:
2316 //case ISD::CONDCODE:
2317 case ISD::HANDLENODE:
2318 case ISD::MDNODE_SDNODE:
2319 case ISD::TargetConstant:
2320 case ISD::TargetConstantFP:
2321 case ISD::TargetConstantPool:
2322 case ISD::TargetFrameIndex:
2323 case ISD::TargetExternalSymbol:
2324 case ISD::TargetBlockAddress:
2325 case ISD::TargetJumpTable:
2326 case ISD::TargetGlobalTLSAddress:
2327 case ISD::TargetGlobalAddress:
2328 case ISD::TokenFactor:
2329 case ISD::CopyFromReg:
2330 case ISD::CopyToReg:
2332 case ISD::LIFETIME_START:
2333 case ISD::LIFETIME_END:
2334 NodeToMatch->setNodeId(-1); // Mark selected.
2336 case ISD::AssertSext:
2337 case ISD::AssertZext:
2338 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2339 NodeToMatch->getOperand(0));
2341 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2342 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2345 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2347 // Set up the node stack with NodeToMatch as the only node on the stack.
2348 SmallVector<SDValue, 8> NodeStack;
2349 SDValue N = SDValue(NodeToMatch, 0);
2350 NodeStack.push_back(N);
2352 // MatchScopes - Scopes used when matching, if a match failure happens, this
2353 // indicates where to continue checking.
2354 SmallVector<MatchScope, 8> MatchScopes;
2356 // RecordedNodes - This is the set of nodes that have been recorded by the
2357 // state machine. The second value is the parent of the node, or null if the
2358 // root is recorded.
2359 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2361 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2363 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2365 // These are the current input chain and glue for use when generating nodes.
2366 // Various Emit operations change these. For example, emitting a copytoreg
2367 // uses and updates these.
2368 SDValue InputChain, InputGlue;
2370 // ChainNodesMatched - If a pattern matches nodes that have input/output
2371 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2372 // which ones they are. The result is captured into this list so that we can
2373 // update the chain results when the pattern is complete.
2374 SmallVector<SDNode*, 3> ChainNodesMatched;
2375 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2377 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: ";
2378 NodeToMatch->dump(CurDAG);
2381 // Determine where to start the interpreter. Normally we start at opcode #0,
2382 // but if the state machine starts with an OPC_SwitchOpcode, then we
2383 // accelerate the first lookup (which is guaranteed to be hot) with the
2384 // OpcodeOffset table.
2385 unsigned MatcherIndex = 0;
2387 if (!OpcodeOffset.empty()) {
2388 // Already computed the OpcodeOffset table, just index into it.
2389 if (N.getOpcode() < OpcodeOffset.size())
2390 MatcherIndex = OpcodeOffset[N.getOpcode()];
2391 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n");
2393 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2394 // Otherwise, the table isn't computed, but the state machine does start
2395 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2396 // is the first time we're selecting an instruction.
2399 // Get the size of this case.
2400 unsigned CaseSize = MatcherTable[Idx++];
2402 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2403 if (CaseSize == 0) break;
2405 // Get the opcode, add the index to the table.
2406 uint16_t Opc = MatcherTable[Idx++];
2407 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2408 if (Opc >= OpcodeOffset.size())
2409 OpcodeOffset.resize((Opc+1)*2);
2410 OpcodeOffset[Opc] = Idx;
2414 // Okay, do the lookup for the first opcode.
2415 if (N.getOpcode() < OpcodeOffset.size())
2416 MatcherIndex = OpcodeOffset[N.getOpcode()];
2420 assert(MatcherIndex < TableSize && "Invalid index");
2422 unsigned CurrentOpcodeIndex = MatcherIndex;
2424 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2427 // Okay, the semantics of this operation are that we should push a scope
2428 // then evaluate the first child. However, pushing a scope only to have
2429 // the first check fail (which then pops it) is inefficient. If we can
2430 // determine immediately that the first check (or first several) will
2431 // immediately fail, don't even bother pushing a scope for them.
2435 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2436 if (NumToSkip & 128)
2437 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2438 // Found the end of the scope with no match.
2439 if (NumToSkip == 0) {
2444 FailIndex = MatcherIndex+NumToSkip;
2446 unsigned MatcherIndexOfPredicate = MatcherIndex;
2447 (void)MatcherIndexOfPredicate; // silence warning.
2449 // If we can't evaluate this predicate without pushing a scope (e.g. if
2450 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2451 // push the scope and evaluate the full predicate chain.
2453 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2454 Result, *this, RecordedNodes);
2458 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at "
2459 << "index " << MatcherIndexOfPredicate
2460 << ", continuing at " << FailIndex << "\n");
2461 ++NumDAGIselRetries;
2463 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2464 // move to the next case.
2465 MatcherIndex = FailIndex;
2468 // If the whole scope failed to match, bail.
2469 if (FailIndex == 0) break;
2471 // Push a MatchScope which indicates where to go if the first child fails
2473 MatchScope NewEntry;
2474 NewEntry.FailIndex = FailIndex;
2475 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2476 NewEntry.NumRecordedNodes = RecordedNodes.size();
2477 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2478 NewEntry.InputChain = InputChain;
2479 NewEntry.InputGlue = InputGlue;
2480 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2481 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2482 MatchScopes.push_back(NewEntry);
2485 case OPC_RecordNode: {
2486 // Remember this node, it may end up being an operand in the pattern.
2488 if (NodeStack.size() > 1)
2489 Parent = NodeStack[NodeStack.size()-2].getNode();
2490 RecordedNodes.push_back(std::make_pair(N, Parent));
2494 case OPC_RecordChild0: case OPC_RecordChild1:
2495 case OPC_RecordChild2: case OPC_RecordChild3:
2496 case OPC_RecordChild4: case OPC_RecordChild5:
2497 case OPC_RecordChild6: case OPC_RecordChild7: {
2498 unsigned ChildNo = Opcode-OPC_RecordChild0;
2499 if (ChildNo >= N.getNumOperands())
2500 break; // Match fails if out of range child #.
2502 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2506 case OPC_RecordMemRef:
2507 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2510 case OPC_CaptureGlueInput:
2511 // If the current node has an input glue, capture it in InputGlue.
2512 if (N->getNumOperands() != 0 &&
2513 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2514 InputGlue = N->getOperand(N->getNumOperands()-1);
2517 case OPC_MoveChild: {
2518 unsigned ChildNo = MatcherTable[MatcherIndex++];
2519 if (ChildNo >= N.getNumOperands())
2520 break; // Match fails if out of range child #.
2521 N = N.getOperand(ChildNo);
2522 NodeStack.push_back(N);
2526 case OPC_MoveParent:
2527 // Pop the current node off the NodeStack.
2528 NodeStack.pop_back();
2529 assert(!NodeStack.empty() && "Node stack imbalance!");
2530 N = NodeStack.back();
2534 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2537 case OPC_CheckChild0Same: case OPC_CheckChild1Same:
2538 case OPC_CheckChild2Same: case OPC_CheckChild3Same:
2539 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes,
2540 Opcode-OPC_CheckChild0Same))
2544 case OPC_CheckPatternPredicate:
2545 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2547 case OPC_CheckPredicate:
2548 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2552 case OPC_CheckComplexPat: {
2553 unsigned CPNum = MatcherTable[MatcherIndex++];
2554 unsigned RecNo = MatcherTable[MatcherIndex++];
2555 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2556 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2557 RecordedNodes[RecNo].first, CPNum,
2562 case OPC_CheckOpcode:
2563 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2567 if (!::CheckType(MatcherTable, MatcherIndex, N, getTargetLowering()))
2571 case OPC_SwitchOpcode: {
2572 unsigned CurNodeOpcode = N.getOpcode();
2573 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2576 // Get the size of this case.
2577 CaseSize = MatcherTable[MatcherIndex++];
2579 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2580 if (CaseSize == 0) break;
2582 uint16_t Opc = MatcherTable[MatcherIndex++];
2583 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2585 // If the opcode matches, then we will execute this case.
2586 if (CurNodeOpcode == Opc)
2589 // Otherwise, skip over this case.
2590 MatcherIndex += CaseSize;
2593 // If no cases matched, bail out.
2594 if (CaseSize == 0) break;
2596 // Otherwise, execute the case we found.
2597 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart
2598 << " to " << MatcherIndex << "\n");
2602 case OPC_SwitchType: {
2603 MVT CurNodeVT = N.getSimpleValueType();
2604 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2607 // Get the size of this case.
2608 CaseSize = MatcherTable[MatcherIndex++];
2610 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2611 if (CaseSize == 0) break;
2613 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2614 if (CaseVT == MVT::iPTR)
2615 CaseVT = getTargetLowering()->getPointerTy();
2617 // If the VT matches, then we will execute this case.
2618 if (CurNodeVT == CaseVT)
2621 // Otherwise, skip over this case.
2622 MatcherIndex += CaseSize;
2625 // If no cases matched, bail out.
2626 if (CaseSize == 0) break;
2628 // Otherwise, execute the case we found.
2629 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2630 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2633 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2634 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2635 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2636 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2637 if (!::CheckChildType(MatcherTable, MatcherIndex, N, getTargetLowering(),
2638 Opcode-OPC_CheckChild0Type))
2641 case OPC_CheckCondCode:
2642 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2644 case OPC_CheckValueType:
2645 if (!::CheckValueType(MatcherTable, MatcherIndex, N, getTargetLowering()))
2648 case OPC_CheckInteger:
2649 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2651 case OPC_CheckAndImm:
2652 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2654 case OPC_CheckOrImm:
2655 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2658 case OPC_CheckFoldableChainNode: {
2659 assert(NodeStack.size() != 1 && "No parent node");
2660 // Verify that all intermediate nodes between the root and this one have
2662 bool HasMultipleUses = false;
2663 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2664 if (!NodeStack[i].hasOneUse()) {
2665 HasMultipleUses = true;
2668 if (HasMultipleUses) break;
2670 // Check to see that the target thinks this is profitable to fold and that
2671 // we can fold it without inducing cycles in the graph.
2672 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2674 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2675 NodeToMatch, OptLevel,
2676 true/*We validate our own chains*/))
2681 case OPC_EmitInteger: {
2682 MVT::SimpleValueType VT =
2683 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2684 int64_t Val = MatcherTable[MatcherIndex++];
2686 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2687 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2688 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2691 case OPC_EmitRegister: {
2692 MVT::SimpleValueType VT =
2693 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2694 unsigned RegNo = MatcherTable[MatcherIndex++];
2695 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2696 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2699 case OPC_EmitRegister2: {
2700 // For targets w/ more than 256 register names, the register enum
2701 // values are stored in two bytes in the matcher table (just like
2703 MVT::SimpleValueType VT =
2704 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2705 unsigned RegNo = MatcherTable[MatcherIndex++];
2706 RegNo |= MatcherTable[MatcherIndex++] << 8;
2707 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2708 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2712 case OPC_EmitConvertToTarget: {
2713 // Convert from IMM/FPIMM to target version.
2714 unsigned RecNo = MatcherTable[MatcherIndex++];
2715 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget");
2716 SDValue Imm = RecordedNodes[RecNo].first;
2718 if (Imm->getOpcode() == ISD::Constant) {
2719 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
2720 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true);
2721 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2722 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2723 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true);
2726 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2730 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2731 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2732 // These are space-optimized forms of OPC_EmitMergeInputChains.
2733 assert(InputChain.getNode() == 0 &&
2734 "EmitMergeInputChains should be the first chain producing node");
2735 assert(ChainNodesMatched.empty() &&
2736 "Should only have one EmitMergeInputChains per match");
2738 // Read all of the chained nodes.
2739 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2740 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
2741 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2743 // FIXME: What if other value results of the node have uses not matched
2745 if (ChainNodesMatched.back() != NodeToMatch &&
2746 !RecordedNodes[RecNo].first.hasOneUse()) {
2747 ChainNodesMatched.clear();
2751 // Merge the input chains if they are not intra-pattern references.
2752 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2754 if (InputChain.getNode() == 0)
2755 break; // Failed to merge.
2759 case OPC_EmitMergeInputChains: {
2760 assert(InputChain.getNode() == 0 &&
2761 "EmitMergeInputChains should be the first chain producing node");
2762 // This node gets a list of nodes we matched in the input that have
2763 // chains. We want to token factor all of the input chains to these nodes
2764 // together. However, if any of the input chains is actually one of the
2765 // nodes matched in this pattern, then we have an intra-match reference.
2766 // Ignore these because the newly token factored chain should not refer to
2768 unsigned NumChains = MatcherTable[MatcherIndex++];
2769 assert(NumChains != 0 && "Can't TF zero chains");
2771 assert(ChainNodesMatched.empty() &&
2772 "Should only have one EmitMergeInputChains per match");
2774 // Read all of the chained nodes.
2775 for (unsigned i = 0; i != NumChains; ++i) {
2776 unsigned RecNo = MatcherTable[MatcherIndex++];
2777 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
2778 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2780 // FIXME: What if other value results of the node have uses not matched
2782 if (ChainNodesMatched.back() != NodeToMatch &&
2783 !RecordedNodes[RecNo].first.hasOneUse()) {
2784 ChainNodesMatched.clear();
2789 // If the inner loop broke out, the match fails.
2790 if (ChainNodesMatched.empty())
2793 // Merge the input chains if they are not intra-pattern references.
2794 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2796 if (InputChain.getNode() == 0)
2797 break; // Failed to merge.
2802 case OPC_EmitCopyToReg: {
2803 unsigned RecNo = MatcherTable[MatcherIndex++];
2804 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg");
2805 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2807 if (InputChain.getNode() == 0)
2808 InputChain = CurDAG->getEntryNode();
2810 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
2811 DestPhysReg, RecordedNodes[RecNo].first,
2814 InputGlue = InputChain.getValue(1);
2818 case OPC_EmitNodeXForm: {
2819 unsigned XFormNo = MatcherTable[MatcherIndex++];
2820 unsigned RecNo = MatcherTable[MatcherIndex++];
2821 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm");
2822 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2823 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2828 case OPC_MorphNodeTo: {
2829 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2830 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2831 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2832 // Get the result VT list.
2833 unsigned NumVTs = MatcherTable[MatcherIndex++];
2834 SmallVector<EVT, 4> VTs;
2835 for (unsigned i = 0; i != NumVTs; ++i) {
2836 MVT::SimpleValueType VT =
2837 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2838 if (VT == MVT::iPTR) VT = getTargetLowering()->getPointerTy().SimpleTy;
2842 if (EmitNodeInfo & OPFL_Chain)
2843 VTs.push_back(MVT::Other);
2844 if (EmitNodeInfo & OPFL_GlueOutput)
2845 VTs.push_back(MVT::Glue);
2847 // This is hot code, so optimize the two most common cases of 1 and 2
2850 if (VTs.size() == 1)
2851 VTList = CurDAG->getVTList(VTs[0]);
2852 else if (VTs.size() == 2)
2853 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2855 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2857 // Get the operand list.
2858 unsigned NumOps = MatcherTable[MatcherIndex++];
2859 SmallVector<SDValue, 8> Ops;
2860 for (unsigned i = 0; i != NumOps; ++i) {
2861 unsigned RecNo = MatcherTable[MatcherIndex++];
2863 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2865 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2866 Ops.push_back(RecordedNodes[RecNo].first);
2869 // If there are variadic operands to add, handle them now.
2870 if (EmitNodeInfo & OPFL_VariadicInfo) {
2871 // Determine the start index to copy from.
2872 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2873 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2874 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2875 "Invalid variadic node");
2876 // Copy all of the variadic operands, not including a potential glue
2878 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2880 SDValue V = NodeToMatch->getOperand(i);
2881 if (V.getValueType() == MVT::Glue) break;
2886 // If this has chain/glue inputs, add them.
2887 if (EmitNodeInfo & OPFL_Chain)
2888 Ops.push_back(InputChain);
2889 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2890 Ops.push_back(InputGlue);
2894 if (Opcode != OPC_MorphNodeTo) {
2895 // If this is a normal EmitNode command, just create the new node and
2896 // add the results to the RecordedNodes list.
2897 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
2900 // Add all the non-glue/non-chain results to the RecordedNodes list.
2901 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2902 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2903 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2907 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
2908 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2911 // NodeToMatch was eliminated by CSE when the target changed the DAG.
2912 // We will visit the equivalent node later.
2913 DEBUG(dbgs() << "Node was eliminated by CSE\n");
2917 // If the node had chain/glue results, update our notion of the current
2919 if (EmitNodeInfo & OPFL_GlueOutput) {
2920 InputGlue = SDValue(Res, VTs.size()-1);
2921 if (EmitNodeInfo & OPFL_Chain)
2922 InputChain = SDValue(Res, VTs.size()-2);
2923 } else if (EmitNodeInfo & OPFL_Chain)
2924 InputChain = SDValue(Res, VTs.size()-1);
2926 // If the OPFL_MemRefs glue is set on this node, slap all of the
2927 // accumulated memrefs onto it.
2929 // FIXME: This is vastly incorrect for patterns with multiple outputs
2930 // instructions that access memory and for ComplexPatterns that match
2932 if (EmitNodeInfo & OPFL_MemRefs) {
2933 // Only attach load or store memory operands if the generated
2934 // instruction may load or store.
2935 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc);
2936 bool mayLoad = MCID.mayLoad();
2937 bool mayStore = MCID.mayStore();
2939 unsigned NumMemRefs = 0;
2940 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
2941 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2942 if ((*I)->isLoad()) {
2945 } else if ((*I)->isStore()) {
2953 MachineSDNode::mmo_iterator MemRefs =
2954 MF->allocateMemRefsArray(NumMemRefs);
2956 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
2957 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
2958 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2959 if ((*I)->isLoad()) {
2962 } else if ((*I)->isStore()) {
2970 cast<MachineSDNode>(Res)
2971 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
2975 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2976 << " node: "; Res->dump(CurDAG); dbgs() << "\n");
2978 // If this was a MorphNodeTo then we're completely done!
2979 if (Opcode == OPC_MorphNodeTo) {
2980 // Update chain and glue uses.
2981 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2982 InputGlue, GlueResultNodesMatched, true);
2989 case OPC_MarkGlueResults: {
2990 unsigned NumNodes = MatcherTable[MatcherIndex++];
2992 // Read and remember all the glue-result nodes.
2993 for (unsigned i = 0; i != NumNodes; ++i) {
2994 unsigned RecNo = MatcherTable[MatcherIndex++];
2996 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2998 assert(RecNo < RecordedNodes.size() && "Invalid MarkGlueResults");
2999 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3004 case OPC_CompleteMatch: {
3005 // The match has been completed, and any new nodes (if any) have been
3006 // created. Patch up references to the matched dag to use the newly
3008 unsigned NumResults = MatcherTable[MatcherIndex++];
3010 for (unsigned i = 0; i != NumResults; ++i) {
3011 unsigned ResSlot = MatcherTable[MatcherIndex++];
3013 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
3015 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch");
3016 SDValue Res = RecordedNodes[ResSlot].first;
3018 assert(i < NodeToMatch->getNumValues() &&
3019 NodeToMatch->getValueType(i) != MVT::Other &&
3020 NodeToMatch->getValueType(i) != MVT::Glue &&
3021 "Invalid number of results to complete!");
3022 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
3023 NodeToMatch->getValueType(i) == MVT::iPTR ||
3024 Res.getValueType() == MVT::iPTR ||
3025 NodeToMatch->getValueType(i).getSizeInBits() ==
3026 Res.getValueType().getSizeInBits()) &&
3027 "invalid replacement");
3028 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
3031 // If the root node defines glue, add it to the glue nodes to update list.
3032 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
3033 GlueResultNodesMatched.push_back(NodeToMatch);
3035 // Update chain and glue uses.
3036 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3037 InputGlue, GlueResultNodesMatched, false);
3039 assert(NodeToMatch->use_empty() &&
3040 "Didn't replace all uses of the node?");
3042 // FIXME: We just return here, which interacts correctly with SelectRoot
3043 // above. We should fix this to not return an SDNode* anymore.
3048 // If the code reached this point, then the match failed. See if there is
3049 // another child to try in the current 'Scope', otherwise pop it until we
3050 // find a case to check.
3051 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
3052 ++NumDAGIselRetries;
3054 if (MatchScopes.empty()) {
3055 CannotYetSelect(NodeToMatch);
3059 // Restore the interpreter state back to the point where the scope was
3061 MatchScope &LastScope = MatchScopes.back();
3062 RecordedNodes.resize(LastScope.NumRecordedNodes);
3064 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
3065 N = NodeStack.back();
3067 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
3068 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
3069 MatcherIndex = LastScope.FailIndex;
3071 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n");
3073 InputChain = LastScope.InputChain;
3074 InputGlue = LastScope.InputGlue;
3075 if (!LastScope.HasChainNodesMatched)
3076 ChainNodesMatched.clear();
3077 if (!LastScope.HasGlueResultNodesMatched)
3078 GlueResultNodesMatched.clear();
3080 // Check to see what the offset is at the new MatcherIndex. If it is zero
3081 // we have reached the end of this scope, otherwise we have another child
3082 // in the current scope to try.
3083 unsigned NumToSkip = MatcherTable[MatcherIndex++];
3084 if (NumToSkip & 128)
3085 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
3087 // If we have another child in this scope to match, update FailIndex and
3089 if (NumToSkip != 0) {
3090 LastScope.FailIndex = MatcherIndex+NumToSkip;
3094 // End of this scope, pop it and try the next child in the containing
3096 MatchScopes.pop_back();
3103 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
3105 raw_string_ostream Msg(msg);
3106 Msg << "Cannot select: ";
3108 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
3109 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
3110 N->getOpcode() != ISD::INTRINSIC_VOID) {
3111 N->printrFull(Msg, CurDAG);
3112 Msg << "\nIn function: " << MF->getName();
3114 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3116 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3117 if (iid < Intrinsic::num_intrinsics)
3118 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3119 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3120 Msg << "target intrinsic %" << TII->getName(iid);
3122 Msg << "unknown intrinsic #" << iid;
3124 report_fatal_error(Msg.str());
3127 char SelectionDAGISel::ID = 0;