1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Function.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/Instructions.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/IntrinsicInst.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/FastISel.h"
32 #include "llvm/CodeGen/GCStrategy.h"
33 #include "llvm/CodeGen/GCMetadata.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
36 #include "llvm/CodeGen/MachineFrameInfo.h"
37 #include "llvm/CodeGen/MachineInstrBuilder.h"
38 #include "llvm/CodeGen/MachineJumpTableInfo.h"
39 #include "llvm/CodeGen/MachineModuleInfo.h"
40 #include "llvm/CodeGen/MachineRegisterInfo.h"
41 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
42 #include "llvm/CodeGen/SchedulerRegistry.h"
43 #include "llvm/CodeGen/SelectionDAG.h"
44 #include "llvm/CodeGen/DwarfWriter.h"
45 #include "llvm/Target/TargetRegisterInfo.h"
46 #include "llvm/Target/TargetData.h"
47 #include "llvm/Target/TargetFrameInfo.h"
48 #include "llvm/Target/TargetIntrinsicInfo.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetLowering.h"
51 #include "llvm/Target/TargetMachine.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "llvm/Support/Compiler.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/Timer.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include "llvm/ADT/Statistic.h"
63 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
64 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
67 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
68 cl::desc("Enable verbose messages in the \"fast\" "
69 "instruction selector"));
71 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
72 cl::desc("Enable abort calls when \"fast\" instruction fails"));
74 SchedLiveInCopies("schedule-livein-copies", cl::Hidden,
75 cl::desc("Schedule copies of livein registers"),
80 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
81 cl::desc("Pop up a window to show dags before the first "
84 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
85 cl::desc("Pop up a window to show dags before legalize types"));
87 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
88 cl::desc("Pop up a window to show dags before legalize"));
90 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
91 cl::desc("Pop up a window to show dags before the second "
94 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
95 cl::desc("Pop up a window to show dags before the post legalize types"
96 " dag combine pass"));
98 ViewISelDAGs("view-isel-dags", cl::Hidden,
99 cl::desc("Pop up a window to show isel dags as they are selected"));
101 ViewSchedDAGs("view-sched-dags", cl::Hidden,
102 cl::desc("Pop up a window to show sched dags as they are processed"));
104 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
105 cl::desc("Pop up a window to show SUnit dags after they are processed"));
107 static const bool ViewDAGCombine1 = false,
108 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
109 ViewDAGCombine2 = false,
110 ViewDAGCombineLT = false,
111 ViewISelDAGs = false, ViewSchedDAGs = false,
112 ViewSUnitDAGs = false;
115 //===---------------------------------------------------------------------===//
117 /// RegisterScheduler class - Track the registration of instruction schedulers.
119 //===---------------------------------------------------------------------===//
120 MachinePassRegistry RegisterScheduler::Registry;
122 //===---------------------------------------------------------------------===//
124 /// ISHeuristic command line option for instruction schedulers.
126 //===---------------------------------------------------------------------===//
127 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
128 RegisterPassParser<RegisterScheduler> >
129 ISHeuristic("pre-RA-sched",
130 cl::init(&createDefaultScheduler),
131 cl::desc("Instruction schedulers available (before register"
134 static RegisterScheduler
135 defaultListDAGScheduler("default", "Best scheduler for the target",
136 createDefaultScheduler);
139 //===--------------------------------------------------------------------===//
140 /// createDefaultScheduler - This creates an instruction scheduler appropriate
142 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
143 CodeGenOpt::Level OptLevel) {
144 const TargetLowering &TLI = IS->getTargetLowering();
146 if (OptLevel == CodeGenOpt::None)
147 return createFastDAGScheduler(IS, OptLevel);
148 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
149 return createTDListDAGScheduler(IS, OptLevel);
150 assert(TLI.getSchedulingPreference() ==
151 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
152 return createBURRListDAGScheduler(IS, OptLevel);
156 // EmitInstrWithCustomInserter - This method should be implemented by targets
157 // that mark instructions with the 'usesCustomInserter' flag. These
158 // instructions are special in various ways, which require special support to
159 // insert. The specified MachineInstr is created but not inserted into any
160 // basic blocks, and this method is called to expand it into a sequence of
161 // instructions, potentially also creating new basic blocks and control flow.
162 // When new basic blocks are inserted and the edges from MBB to its successors
163 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
165 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
166 MachineBasicBlock *MBB,
167 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
169 dbgs() << "If a target marks an instruction with "
170 "'usesCustomInserter', it must implement "
171 "TargetLowering::EmitInstrWithCustomInserter!";
177 /// EmitLiveInCopy - Emit a copy for a live in physical register. If the
178 /// physical register has only a single copy use, then coalesced the copy
180 static void EmitLiveInCopy(MachineBasicBlock *MBB,
181 MachineBasicBlock::iterator &InsertPos,
182 unsigned VirtReg, unsigned PhysReg,
183 const TargetRegisterClass *RC,
184 DenseMap<MachineInstr*, unsigned> &CopyRegMap,
185 const MachineRegisterInfo &MRI,
186 const TargetRegisterInfo &TRI,
187 const TargetInstrInfo &TII) {
188 unsigned NumUses = 0;
189 MachineInstr *UseMI = NULL;
190 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg),
191 UE = MRI.use_end(); UI != UE; ++UI) {
197 // If the number of uses is not one, or the use is not a move instruction,
198 // don't coalesce. Also, only coalesce away a virtual register to virtual
200 bool Coalesced = false;
201 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
203 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
204 TargetRegisterInfo::isVirtualRegister(DstReg)) {
209 // Now find an ideal location to insert the copy.
210 MachineBasicBlock::iterator Pos = InsertPos;
211 while (Pos != MBB->begin()) {
212 MachineInstr *PrevMI = prior(Pos);
213 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI);
214 // copyRegToReg might emit multiple instructions to do a copy.
215 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second;
216 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg))
217 // This is what the BB looks like right now:
222 // We want to insert "r1025 = mov r1". Inserting this copy below the
223 // move to r1024 makes it impossible for that move to be coalesced.
230 break; // Woot! Found a good location.
234 bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC);
235 assert(Emitted && "Unable to issue a live-in copy instruction!\n");
238 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg));
240 if (&*InsertPos == UseMI) ++InsertPos;
245 /// EmitLiveInCopies - If this is the first basic block in the function,
246 /// and if it has live ins that need to be copied into vregs, emit the
247 /// copies into the block.
248 static void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
249 const MachineRegisterInfo &MRI,
250 const TargetRegisterInfo &TRI,
251 const TargetInstrInfo &TII) {
252 if (SchedLiveInCopies) {
253 // Emit the copies at a heuristically-determined location in the block.
254 DenseMap<MachineInstr*, unsigned> CopyRegMap;
255 MachineBasicBlock::iterator InsertPos = EntryMBB->begin();
256 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
257 E = MRI.livein_end(); LI != E; ++LI)
259 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
260 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first,
261 RC, CopyRegMap, MRI, TRI, TII);
264 // Emit the copies into the top of the block.
265 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
266 E = MRI.livein_end(); LI != E; ++LI)
268 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
269 bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(),
270 LI->second, LI->first, RC, RC);
271 assert(Emitted && "Unable to issue a live-in copy instruction!\n");
277 //===----------------------------------------------------------------------===//
278 // SelectionDAGISel code
279 //===----------------------------------------------------------------------===//
281 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) :
282 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
283 FuncInfo(new FunctionLoweringInfo(TLI)),
284 CurDAG(new SelectionDAG(TLI, *FuncInfo)),
285 SDB(new SelectionDAGBuilder(*CurDAG, TLI, *FuncInfo, OL)),
291 SelectionDAGISel::~SelectionDAGISel() {
297 unsigned SelectionDAGISel::MakeReg(EVT VT) {
298 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
301 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
302 AU.addRequired<AliasAnalysis>();
303 AU.addPreserved<AliasAnalysis>();
304 AU.addRequired<GCModuleInfo>();
305 AU.addPreserved<GCModuleInfo>();
306 AU.addRequired<DwarfWriter>();
307 AU.addPreserved<DwarfWriter>();
308 MachineFunctionPass::getAnalysisUsage(AU);
311 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
312 Function &Fn = *mf.getFunction();
314 // Do some sanity-checking on the command-line options.
315 assert((!EnableFastISelVerbose || EnableFastISel) &&
316 "-fast-isel-verbose requires -fast-isel");
317 assert((!EnableFastISelAbort || EnableFastISel) &&
318 "-fast-isel-abort requires -fast-isel");
320 // Get alias analysis for load/store combining.
321 AA = &getAnalysis<AliasAnalysis>();
324 const TargetInstrInfo &TII = *TM.getInstrInfo();
325 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
328 GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn);
331 RegInfo = &MF->getRegInfo();
332 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
334 MachineModuleInfo *MMI = getAnalysisIfAvailable<MachineModuleInfo>();
335 DwarfWriter *DW = getAnalysisIfAvailable<DwarfWriter>();
336 CurDAG->init(*MF, MMI, DW);
337 FuncInfo->set(Fn, *MF, EnableFastISel);
340 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
341 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
343 FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
345 SelectAllBasicBlocks(Fn, *MF, MMI, TII);
347 // If the first basic block in the function has live ins that need to be
348 // copied into vregs, emit the copies into the top of the block before
349 // emitting the code for the block.
350 EmitLiveInCopies(MF->begin(), *RegInfo, TRI, TII);
352 // Add function live-ins to entry block live-in set.
353 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
354 E = RegInfo->livein_end(); I != E; ++I)
355 MF->begin()->addLiveIn(I->first);
358 assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() &&
359 "Not all catch info was assigned to a landing pad!");
367 /// SetDebugLoc - Update MF's and SDB's DebugLocs if debug information is
368 /// attached with this instruction.
369 static void SetDebugLoc(Instruction *I, SelectionDAGBuilder *SDB,
370 FastISel *FastIS, MachineFunction *MF) {
371 DebugLoc DL = I->getDebugLoc();
372 if (DL.isUnknown()) return;
374 SDB->setCurDebugLoc(DL);
377 FastIS->setCurDebugLoc(DL);
379 // If the function doesn't have a default debug location yet, set
380 // it. This is kind of a hack.
381 if (MF->getDefaultDebugLoc().isUnknown())
382 MF->setDefaultDebugLoc(DL);
385 /// ResetDebugLoc - Set MF's and SDB's DebugLocs to Unknown.
386 static void ResetDebugLoc(SelectionDAGBuilder *SDB, FastISel *FastIS) {
387 SDB->setCurDebugLoc(DebugLoc());
389 FastIS->setCurDebugLoc(DebugLoc());
392 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
393 BasicBlock::iterator Begin,
394 BasicBlock::iterator End,
396 SDB->setCurrentBasicBlock(BB);
398 // Lower all of the non-terminator instructions. If a call is emitted
399 // as a tail call, cease emitting nodes for this block.
400 for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) {
401 SetDebugLoc(I, SDB, 0, MF);
403 if (!isa<TerminatorInst>(I)) {
406 // Set the current debug location back to "unknown" so that it doesn't
407 // spuriously apply to subsequent instructions.
408 ResetDebugLoc(SDB, 0);
412 if (!SDB->HasTailCall) {
413 // Ensure that all instructions which are used outside of their defining
414 // blocks are available as virtual registers. Invoke is handled elsewhere.
415 for (BasicBlock::iterator I = Begin; I != End; ++I)
416 if (!isa<PHINode>(I) && !isa<InvokeInst>(I))
417 SDB->CopyToExportRegsIfNeeded(I);
419 // Handle PHI nodes in successor blocks.
420 if (End == LLVMBB->end()) {
421 HandlePHINodesInSuccessorBlocks(LLVMBB);
423 // Lower the terminator after the copies are emitted.
424 SetDebugLoc(LLVMBB->getTerminator(), SDB, 0, MF);
425 SDB->visit(*LLVMBB->getTerminator());
426 ResetDebugLoc(SDB, 0);
430 // Make sure the root of the DAG is up-to-date.
431 CurDAG->setRoot(SDB->getControlRoot());
433 // Final step, emit the lowered DAG as machine code.
435 HadTailCall = SDB->HasTailCall;
440 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
441 /// nodes from the worklist.
442 class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener {
443 SmallVector<SDNode*, 128> &Worklist;
444 SmallPtrSet<SDNode*, 128> &InWorklist;
446 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl,
447 SmallPtrSet<SDNode*, 128> &inwl)
448 : Worklist(wl), InWorklist(inwl) {}
450 void RemoveFromWorklist(SDNode *N) {
451 if (!InWorklist.erase(N)) return;
453 SmallVector<SDNode*, 128>::iterator I =
454 std::find(Worklist.begin(), Worklist.end(), N);
455 assert(I != Worklist.end() && "Not in worklist");
457 *I = Worklist.back();
461 virtual void NodeDeleted(SDNode *N, SDNode *E) {
462 RemoveFromWorklist(N);
465 virtual void NodeUpdated(SDNode *N) {
471 /// TrivialTruncElim - Eliminate some trivial nops that can result from
472 /// ShrinkDemandedOps: (trunc (ext n)) -> n.
473 static bool TrivialTruncElim(SDValue Op,
474 TargetLowering::TargetLoweringOpt &TLO) {
475 SDValue N0 = Op.getOperand(0);
476 EVT VT = Op.getValueType();
477 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
478 N0.getOpcode() == ISD::SIGN_EXTEND ||
479 N0.getOpcode() == ISD::ANY_EXTEND) &&
480 N0.getOperand(0).getValueType() == VT) {
481 return TLO.CombineTo(Op, N0.getOperand(0));
486 /// ShrinkDemandedOps - A late transformation pass that shrink expressions
487 /// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts
488 /// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
489 void SelectionDAGISel::ShrinkDemandedOps() {
490 SmallVector<SDNode*, 128> Worklist;
491 SmallPtrSet<SDNode*, 128> InWorklist;
493 // Add all the dag nodes to the worklist.
494 Worklist.reserve(CurDAG->allnodes_size());
495 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
496 E = CurDAG->allnodes_end(); I != E; ++I) {
497 Worklist.push_back(I);
498 InWorklist.insert(I);
501 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true);
502 while (!Worklist.empty()) {
503 SDNode *N = Worklist.pop_back_val();
506 if (N->use_empty() && N != CurDAG->getRoot().getNode()) {
507 // Deleting this node may make its operands dead, add them to the worklist
508 // if they aren't already there.
509 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
510 if (InWorklist.insert(N->getOperand(i).getNode()))
511 Worklist.push_back(N->getOperand(i).getNode());
513 CurDAG->DeleteNode(N);
517 // Run ShrinkDemandedOp on scalar binary operations.
518 if (N->getNumValues() != 1 ||
519 !N->getValueType(0).isSimple() || !N->getValueType(0).isInteger())
522 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
523 APInt Demanded = APInt::getAllOnesValue(BitWidth);
524 APInt KnownZero, KnownOne;
525 if (!TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded,
526 KnownZero, KnownOne, TLO) &&
527 (N->getOpcode() != ISD::TRUNCATE ||
528 !TrivialTruncElim(SDValue(N, 0), TLO)))
532 assert(!InWorklist.count(N) && "Already in worklist");
533 Worklist.push_back(N);
534 InWorklist.insert(N);
536 // Replace the old value with the new one.
537 DEBUG(errs() << "\nShrinkDemandedOps replacing ";
538 TLO.Old.getNode()->dump(CurDAG);
539 errs() << "\nWith: ";
540 TLO.New.getNode()->dump(CurDAG);
543 if (InWorklist.insert(TLO.New.getNode()))
544 Worklist.push_back(TLO.New.getNode());
546 SDOPsWorkListRemover DeadNodes(Worklist, InWorklist);
547 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
549 if (!TLO.Old.getNode()->use_empty()) continue;
551 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands();
553 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode();
554 if (OpNode->hasOneUse()) {
555 // Add OpNode to the end of the list to revisit.
556 DeadNodes.RemoveFromWorklist(OpNode);
557 Worklist.push_back(OpNode);
558 InWorklist.insert(OpNode);
562 DeadNodes.RemoveFromWorklist(TLO.Old.getNode());
563 CurDAG->DeleteNode(TLO.Old.getNode());
567 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
568 SmallPtrSet<SDNode*, 128> VisitedNodes;
569 SmallVector<SDNode*, 128> Worklist;
571 Worklist.push_back(CurDAG->getRoot().getNode());
578 SDNode *N = Worklist.pop_back_val();
580 // If we've already seen this node, ignore it.
581 if (!VisitedNodes.insert(N))
584 // Otherwise, add all chain operands to the worklist.
585 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
586 if (N->getOperand(i).getValueType() == MVT::Other)
587 Worklist.push_back(N->getOperand(i).getNode());
589 // If this is a CopyToReg with a vreg dest, process it.
590 if (N->getOpcode() != ISD::CopyToReg)
593 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
594 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
597 // Ignore non-scalar or non-integer values.
598 SDValue Src = N->getOperand(2);
599 EVT SrcVT = Src.getValueType();
600 if (!SrcVT.isInteger() || SrcVT.isVector())
603 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
604 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
605 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
607 // Only install this information if it tells us something.
608 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
609 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
610 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
611 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
612 FunctionLoweringInfo::LiveOutInfo &LOI =
613 FuncInfo->LiveOutRegInfo[DestReg];
614 LOI.NumSignBits = NumSignBits;
615 LOI.KnownOne = KnownOne;
616 LOI.KnownZero = KnownZero;
618 } while (!Worklist.empty());
621 void SelectionDAGISel::CodeGenAndEmitDAG() {
622 std::string GroupName;
623 if (TimePassesIsEnabled)
624 GroupName = "Instruction Selection and Scheduling";
625 std::string BlockName;
626 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
627 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
629 BlockName = MF->getFunction()->getNameStr() + ":" +
630 BB->getBasicBlock()->getNameStr();
632 DEBUG(dbgs() << "Initial selection DAG:\n");
633 DEBUG(CurDAG->dump());
635 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
637 // Run the DAG combiner in pre-legalize mode.
638 if (TimePassesIsEnabled) {
639 NamedRegionTimer T("DAG Combining 1", GroupName);
640 CurDAG->Combine(Unrestricted, *AA, OptLevel);
642 CurDAG->Combine(Unrestricted, *AA, OptLevel);
645 DEBUG(dbgs() << "Optimized lowered selection DAG:\n");
646 DEBUG(CurDAG->dump());
648 // Second step, hack on the DAG until it only uses operations and types that
649 // the target supports.
650 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
654 if (TimePassesIsEnabled) {
655 NamedRegionTimer T("Type Legalization", GroupName);
656 Changed = CurDAG->LegalizeTypes();
658 Changed = CurDAG->LegalizeTypes();
661 DEBUG(dbgs() << "Type-legalized selection DAG:\n");
662 DEBUG(CurDAG->dump());
665 if (ViewDAGCombineLT)
666 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
668 // Run the DAG combiner in post-type-legalize mode.
669 if (TimePassesIsEnabled) {
670 NamedRegionTimer T("DAG Combining after legalize types", GroupName);
671 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
673 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
676 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n");
677 DEBUG(CurDAG->dump());
680 if (TimePassesIsEnabled) {
681 NamedRegionTimer T("Vector Legalization", GroupName);
682 Changed = CurDAG->LegalizeVectors();
684 Changed = CurDAG->LegalizeVectors();
688 if (TimePassesIsEnabled) {
689 NamedRegionTimer T("Type Legalization 2", GroupName);
690 CurDAG->LegalizeTypes();
692 CurDAG->LegalizeTypes();
695 if (ViewDAGCombineLT)
696 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
698 // Run the DAG combiner in post-type-legalize mode.
699 if (TimePassesIsEnabled) {
700 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName);
701 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
703 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
706 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n");
707 DEBUG(CurDAG->dump());
710 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
712 if (TimePassesIsEnabled) {
713 NamedRegionTimer T("DAG Legalization", GroupName);
714 CurDAG->Legalize(OptLevel);
716 CurDAG->Legalize(OptLevel);
719 DEBUG(dbgs() << "Legalized selection DAG:\n");
720 DEBUG(CurDAG->dump());
722 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
724 // Run the DAG combiner in post-legalize mode.
725 if (TimePassesIsEnabled) {
726 NamedRegionTimer T("DAG Combining 2", GroupName);
727 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
729 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
732 DEBUG(dbgs() << "Optimized legalized selection DAG:\n");
733 DEBUG(CurDAG->dump());
735 if (OptLevel != CodeGenOpt::None) {
737 ComputeLiveOutVRegInfo();
740 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
742 // Third, instruction select all of the operations to machine code, adding the
743 // code to the MachineBasicBlock.
744 if (TimePassesIsEnabled) {
745 NamedRegionTimer T("Instruction Selection", GroupName);
746 DoInstructionSelection();
748 DoInstructionSelection();
751 DEBUG(dbgs() << "Selected selection DAG:\n");
752 DEBUG(CurDAG->dump());
754 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
756 // Schedule machine code.
757 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
758 if (TimePassesIsEnabled) {
759 NamedRegionTimer T("Instruction Scheduling", GroupName);
760 Scheduler->Run(CurDAG, BB, BB->end());
762 Scheduler->Run(CurDAG, BB, BB->end());
765 if (ViewSUnitDAGs) Scheduler->viewGraph();
767 // Emit machine code to BB. This can change 'BB' to the last block being
769 if (TimePassesIsEnabled) {
770 NamedRegionTimer T("Instruction Creation", GroupName);
771 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
773 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
776 // Free the scheduler state.
777 if (TimePassesIsEnabled) {
778 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
784 DEBUG(dbgs() << "Selected machine code:\n");
788 void SelectionDAGISel::DoInstructionSelection() {
789 DEBUG(errs() << "===== Instruction selection begins:\n");
793 // Select target instructions for the DAG.
795 // Number all nodes with a topological order and set DAGSize.
796 DAGSize = CurDAG->AssignTopologicalOrder();
798 // Create a dummy node (which is not added to allnodes), that adds
799 // a reference to the root node, preventing it from being deleted,
800 // and tracking any changes of the root.
801 HandleSDNode Dummy(CurDAG->getRoot());
802 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
805 // The AllNodes list is now topological-sorted. Visit the
806 // nodes by starting at the end of the list (the root of the
807 // graph) and preceding back toward the beginning (the entry
809 while (ISelPosition != CurDAG->allnodes_begin()) {
810 SDNode *Node = --ISelPosition;
811 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
812 // but there are currently some corner cases that it misses. Also, this
813 // makes it theoretically possible to disable the DAGCombiner.
814 if (Node->use_empty())
817 SDNode *ResNode = Select(Node);
819 // FIXME: This is pretty gross. 'Select' should be changed to not return
820 // anything at all and this code should be nuked with a tactical strike.
822 // If node should not be replaced, continue with the next one.
823 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
827 ReplaceUses(Node, ResNode);
829 // If after the replacement this node is not used any more,
830 // remove this dead node.
831 if (Node->use_empty()) { // Don't delete EntryToken, etc.
832 ISelUpdater ISU(ISelPosition);
833 CurDAG->RemoveDeadNode(Node, &ISU);
837 CurDAG->setRoot(Dummy.getValue());
839 DEBUG(errs() << "===== Instruction selection ends:\n");
841 PostprocessISelDAG();
845 void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
847 MachineModuleInfo *MMI,
848 const TargetInstrInfo &TII) {
849 // Initialize the Fast-ISel state, if needed.
850 FastISel *FastIS = 0;
852 FastIS = TLI.createFastISel(MF, MMI,
855 FuncInfo->StaticAllocaMap
857 , FuncInfo->CatchInfoLost
861 // Iterate over all basic blocks in the function.
862 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
863 BasicBlock *LLVMBB = &*I;
864 BB = FuncInfo->MBBMap[LLVMBB];
866 BasicBlock::iterator const Begin = LLVMBB->begin();
867 BasicBlock::iterator const End = LLVMBB->end();
868 BasicBlock::iterator BI = Begin;
870 // Lower any arguments needed in this block if this is the entry block.
871 bool SuppressFastISel = false;
872 if (LLVMBB == &Fn.getEntryBlock()) {
873 LowerArguments(LLVMBB);
875 // If any of the arguments has the byval attribute, forgo
876 // fast-isel in the entry block.
879 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end();
881 if (Fn.paramHasAttr(j, Attribute::ByVal)) {
882 if (EnableFastISelVerbose || EnableFastISelAbort)
883 dbgs() << "FastISel skips entry block due to byval argument\n";
884 SuppressFastISel = true;
890 if (MMI && BB->isLandingPad()) {
891 // Add a label to mark the beginning of the landing pad. Deletion of the
892 // landing pad can thus be detected via the MachineModuleInfo.
893 MCSymbol *Label = MMI->addLandingPad(BB);
895 const TargetInstrDesc &II = TII.get(TargetOpcode::EH_LABEL);
896 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label);
898 // Mark exception register as live in.
899 unsigned Reg = TLI.getExceptionAddressRegister();
900 if (Reg) BB->addLiveIn(Reg);
902 // Mark exception selector register as live in.
903 Reg = TLI.getExceptionSelectorRegister();
904 if (Reg) BB->addLiveIn(Reg);
906 // FIXME: Hack around an exception handling flaw (PR1508): the personality
907 // function and list of typeids logically belong to the invoke (or, if you
908 // like, the basic block containing the invoke), and need to be associated
909 // with it in the dwarf exception handling tables. Currently however the
910 // information is provided by an intrinsic (eh.selector) that can be moved
911 // to unexpected places by the optimizers: if the unwind edge is critical,
912 // then breaking it can result in the intrinsics being in the successor of
913 // the landing pad, not the landing pad itself. This results
914 // in exceptions not being caught because no typeids are associated with
915 // the invoke. This may not be the only way things can go wrong, but it
916 // is the only way we try to work around for the moment.
917 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
919 if (Br && Br->isUnconditional()) { // Critical edge?
920 BasicBlock::iterator I, E;
921 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
922 if (isa<EHSelectorInst>(I))
926 // No catch info found - try to extract some from the successor.
927 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, *FuncInfo);
931 // Before doing SelectionDAG ISel, see if FastISel has been requested.
932 if (FastIS && !SuppressFastISel) {
933 // Emit code for any incoming arguments. This must happen before
934 // beginning FastISel on the entry block.
935 if (LLVMBB == &Fn.getEntryBlock()) {
936 CurDAG->setRoot(SDB->getControlRoot());
940 FastIS->startNewBlock(BB);
941 // Do FastISel on as many instructions as possible.
942 for (; BI != End; ++BI) {
943 // Just before the terminator instruction, insert instructions to
944 // feed PHI nodes in successor blocks.
945 if (isa<TerminatorInst>(BI))
946 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) {
947 ++NumFastIselFailures;
948 ResetDebugLoc(SDB, FastIS);
949 if (EnableFastISelVerbose || EnableFastISelAbort) {
950 dbgs() << "FastISel miss: ";
953 assert(!EnableFastISelAbort &&
954 "FastISel didn't handle a PHI in a successor");
958 SetDebugLoc(BI, SDB, FastIS, &MF);
960 // Try to select the instruction with FastISel.
961 if (FastIS->SelectInstruction(BI)) {
962 ResetDebugLoc(SDB, FastIS);
966 // Clear out the debug location so that it doesn't carry over to
967 // unrelated instructions.
968 ResetDebugLoc(SDB, FastIS);
970 // Then handle certain instructions as single-LLVM-Instruction blocks.
971 if (isa<CallInst>(BI)) {
972 ++NumFastIselFailures;
973 if (EnableFastISelVerbose || EnableFastISelAbort) {
974 dbgs() << "FastISel missed call: ";
978 if (!BI->getType()->isVoidTy()) {
979 unsigned &R = FuncInfo->ValueMap[BI];
981 R = FuncInfo->CreateRegForValue(BI);
984 bool HadTailCall = false;
985 SelectBasicBlock(LLVMBB, BI, llvm::next(BI), HadTailCall);
987 // If the call was emitted as a tail call, we're done with the block.
993 // If the instruction was codegen'd with multiple blocks,
994 // inform the FastISel object where to resume inserting.
995 FastIS->setCurrentBlock(BB);
999 // Otherwise, give up on FastISel for the rest of the block.
1000 // For now, be a little lenient about non-branch terminators.
1001 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
1002 ++NumFastIselFailures;
1003 if (EnableFastISelVerbose || EnableFastISelAbort) {
1004 dbgs() << "FastISel miss: ";
1007 if (EnableFastISelAbort)
1008 // The "fast" selector couldn't handle something and bailed.
1009 // For the purpose of debugging, just abort.
1010 llvm_unreachable("FastISel didn't select the entire block");
1016 // Run SelectionDAG instruction selection on the remainder of the block
1017 // not handled by FastISel. If FastISel is not run, this is the entire
1021 SelectBasicBlock(LLVMBB, BI, End, HadTailCall);
1031 SelectionDAGISel::FinishBasicBlock() {
1033 DEBUG(dbgs() << "Target-post-processed machine code:\n");
1036 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1037 << SDB->PHINodesToUpdate.size() << "\n");
1038 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i)
1039 dbgs() << "Node " << i << " : ("
1040 << SDB->PHINodesToUpdate[i].first
1041 << ", " << SDB->PHINodesToUpdate[i].second << ")\n");
1043 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1044 // PHI nodes in successors.
1045 if (SDB->SwitchCases.empty() &&
1046 SDB->JTCases.empty() &&
1047 SDB->BitTestCases.empty()) {
1048 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
1049 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
1050 assert(PHI->isPHI() &&
1051 "This is not a machine PHI node that we are updating!");
1052 if (!BB->isSuccessor(PHI->getParent()))
1054 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
1056 PHI->addOperand(MachineOperand::CreateMBB(BB));
1058 SDB->PHINodesToUpdate.clear();
1062 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1063 // Lower header first, if it wasn't already lowered
1064 if (!SDB->BitTestCases[i].Emitted) {
1065 // Set the current basic block to the mbb we wish to insert the code into
1066 BB = SDB->BitTestCases[i].Parent;
1067 SDB->setCurrentBasicBlock(BB);
1069 SDB->visitBitTestHeader(SDB->BitTestCases[i]);
1070 CurDAG->setRoot(SDB->getRoot());
1071 CodeGenAndEmitDAG();
1075 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1076 // Set the current basic block to the mbb we wish to insert the code into
1077 BB = SDB->BitTestCases[i].Cases[j].ThisBB;
1078 SDB->setCurrentBasicBlock(BB);
1081 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
1082 SDB->BitTestCases[i].Reg,
1083 SDB->BitTestCases[i].Cases[j]);
1085 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
1086 SDB->BitTestCases[i].Reg,
1087 SDB->BitTestCases[i].Cases[j]);
1090 CurDAG->setRoot(SDB->getRoot());
1091 CodeGenAndEmitDAG();
1096 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
1097 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
1098 MachineBasicBlock *PHIBB = PHI->getParent();
1099 assert(PHI->isPHI() &&
1100 "This is not a machine PHI node that we are updating!");
1101 // This is "default" BB. We have two jumps to it. From "header" BB and
1102 // from last "case" BB.
1103 if (PHIBB == SDB->BitTestCases[i].Default) {
1104 PHI->addOperand(MachineOperand::
1105 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1106 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
1107 PHI->addOperand(MachineOperand::
1108 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1109 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
1112 // One of "cases" BB.
1113 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1115 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1116 if (cBB->isSuccessor(PHIBB)) {
1117 PHI->addOperand(MachineOperand::
1118 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1119 PHI->addOperand(MachineOperand::CreateMBB(cBB));
1124 SDB->BitTestCases.clear();
1126 // If the JumpTable record is filled in, then we need to emit a jump table.
1127 // Updating the PHI nodes is tricky in this case, since we need to determine
1128 // whether the PHI is a successor of the range check MBB or the jump table MBB
1129 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1130 // Lower header first, if it wasn't already lowered
1131 if (!SDB->JTCases[i].first.Emitted) {
1132 // Set the current basic block to the mbb we wish to insert the code into
1133 BB = SDB->JTCases[i].first.HeaderBB;
1134 SDB->setCurrentBasicBlock(BB);
1136 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first);
1137 CurDAG->setRoot(SDB->getRoot());
1138 CodeGenAndEmitDAG();
1142 // Set the current basic block to the mbb we wish to insert the code into
1143 BB = SDB->JTCases[i].second.MBB;
1144 SDB->setCurrentBasicBlock(BB);
1146 SDB->visitJumpTable(SDB->JTCases[i].second);
1147 CurDAG->setRoot(SDB->getRoot());
1148 CodeGenAndEmitDAG();
1152 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
1153 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
1154 MachineBasicBlock *PHIBB = PHI->getParent();
1155 assert(PHI->isPHI() &&
1156 "This is not a machine PHI node that we are updating!");
1157 // "default" BB. We can go there only from header BB.
1158 if (PHIBB == SDB->JTCases[i].second.Default) {
1160 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1162 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1164 // JT BB. Just iterate over successors here
1165 if (BB->isSuccessor(PHIBB)) {
1167 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1168 PHI->addOperand(MachineOperand::CreateMBB(BB));
1172 SDB->JTCases.clear();
1174 // If the switch block involved a branch to one of the actual successors, we
1175 // need to update PHI nodes in that block.
1176 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
1177 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
1178 assert(PHI->isPHI() &&
1179 "This is not a machine PHI node that we are updating!");
1180 if (BB->isSuccessor(PHI->getParent())) {
1181 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
1183 PHI->addOperand(MachineOperand::CreateMBB(BB));
1187 // If we generated any switch lowering information, build and codegen any
1188 // additional DAGs necessary.
1189 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1190 // Set the current basic block to the mbb we wish to insert the code into
1191 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB;
1192 SDB->setCurrentBasicBlock(BB);
1195 SDB->visitSwitchCase(SDB->SwitchCases[i]);
1196 CurDAG->setRoot(SDB->getRoot());
1197 CodeGenAndEmitDAG();
1199 // Handle any PHI nodes in successors of this chunk, as if we were coming
1200 // from the original BB before switch expansion. Note that PHI nodes can
1201 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1202 // handle them the right number of times.
1203 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
1204 // If new BB's are created during scheduling, the edges may have been
1205 // updated. That is, the edge from ThisBB to BB may have been split and
1206 // BB's predecessor is now another block.
1207 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI =
1208 SDB->EdgeMapping.find(BB);
1209 if (EI != SDB->EdgeMapping.end())
1210 ThisBB = EI->second;
1212 // BB may have been removed from the CFG if a branch was constant folded.
1213 if (ThisBB->isSuccessor(BB)) {
1214 for (MachineBasicBlock::iterator Phi = BB->begin();
1215 Phi != BB->end() && Phi->isPHI();
1217 // This value for this PHI node is recorded in PHINodesToUpdate.
1218 for (unsigned pn = 0; ; ++pn) {
1219 assert(pn != SDB->PHINodesToUpdate.size() &&
1220 "Didn't find PHI entry!");
1221 if (SDB->PHINodesToUpdate[pn].first == Phi) {
1222 Phi->addOperand(MachineOperand::
1223 CreateReg(SDB->PHINodesToUpdate[pn].second,
1225 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1232 // Don't process RHS if same block as LHS.
1233 if (BB == SDB->SwitchCases[i].FalseBB)
1234 SDB->SwitchCases[i].FalseBB = 0;
1236 // If we haven't handled the RHS, do so now. Otherwise, we're done.
1237 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB;
1238 SDB->SwitchCases[i].FalseBB = 0;
1240 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0);
1243 SDB->SwitchCases.clear();
1245 SDB->PHINodesToUpdate.clear();
1249 /// Create the scheduler. If a specific scheduler was specified
1250 /// via the SchedulerRegistry, use it, otherwise select the
1251 /// one preferred by the target.
1253 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1254 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1258 RegisterScheduler::setDefault(Ctor);
1261 return Ctor(this, OptLevel);
1264 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1265 return new ScheduleHazardRecognizer();
1268 //===----------------------------------------------------------------------===//
1269 // Helper functions used by the generated instruction selector.
1270 //===----------------------------------------------------------------------===//
1271 // Calls to these methods are generated by tblgen.
1273 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1274 /// the dag combiner simplified the 255, we still want to match. RHS is the
1275 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1276 /// specified in the .td file (e.g. 255).
1277 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1278 int64_t DesiredMaskS) const {
1279 const APInt &ActualMask = RHS->getAPIntValue();
1280 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1282 // If the actual mask exactly matches, success!
1283 if (ActualMask == DesiredMask)
1286 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1287 if (ActualMask.intersects(~DesiredMask))
1290 // Otherwise, the DAG Combiner may have proven that the value coming in is
1291 // either already zero or is not demanded. Check for known zero input bits.
1292 APInt NeededMask = DesiredMask & ~ActualMask;
1293 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1296 // TODO: check to see if missing bits are just not demanded.
1298 // Otherwise, this pattern doesn't match.
1302 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1303 /// the dag combiner simplified the 255, we still want to match. RHS is the
1304 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1305 /// specified in the .td file (e.g. 255).
1306 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1307 int64_t DesiredMaskS) const {
1308 const APInt &ActualMask = RHS->getAPIntValue();
1309 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1311 // If the actual mask exactly matches, success!
1312 if (ActualMask == DesiredMask)
1315 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1316 if (ActualMask.intersects(~DesiredMask))
1319 // Otherwise, the DAG Combiner may have proven that the value coming in is
1320 // either already zero or is not demanded. Check for known zero input bits.
1321 APInt NeededMask = DesiredMask & ~ActualMask;
1323 APInt KnownZero, KnownOne;
1324 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1326 // If all the missing bits in the or are already known to be set, match!
1327 if ((NeededMask & KnownOne) == NeededMask)
1330 // TODO: check to see if missing bits are just not demanded.
1332 // Otherwise, this pattern doesn't match.
1337 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1338 /// by tblgen. Others should not call it.
1339 void SelectionDAGISel::
1340 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1341 std::vector<SDValue> InOps;
1342 std::swap(InOps, Ops);
1344 Ops.push_back(InOps[0]); // input chain.
1345 Ops.push_back(InOps[1]); // input asm string.
1347 unsigned i = 2, e = InOps.size();
1348 if (InOps[e-1].getValueType() == MVT::Flag)
1349 --e; // Don't process a flag operand if it is here.
1352 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1353 if ((Flags & 7) != 4 /*MEM*/) {
1354 // Just skip over this operand, copying the operands verbatim.
1355 Ops.insert(Ops.end(), InOps.begin()+i,
1356 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1357 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1359 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1360 "Memory operand with multiple values?");
1361 // Otherwise, this is a memory operand. Ask the target to select it.
1362 std::vector<SDValue> SelOps;
1363 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) {
1364 llvm_report_error("Could not match memory address. Inline asm"
1368 // Add this to the output node.
1369 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3),
1371 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1376 // Add the flag input back if present.
1377 if (e != InOps.size())
1378 Ops.push_back(InOps.back());
1381 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1384 static SDNode *findFlagUse(SDNode *N) {
1385 unsigned FlagResNo = N->getNumValues()-1;
1386 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1387 SDUse &Use = I.getUse();
1388 if (Use.getResNo() == FlagResNo)
1389 return Use.getUser();
1394 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1395 /// This function recursively traverses up the operand chain, ignoring
1397 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1398 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1399 bool IgnoreChains) {
1400 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1401 // greater than all of its (recursive) operands. If we scan to a point where
1402 // 'use' is smaller than the node we're scanning for, then we know we will
1405 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1406 // happen because we scan down to newly selected nodes in the case of flag
1408 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1411 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1412 // won't fail if we scan it again.
1413 if (!Visited.insert(Use))
1416 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1417 // Ignore chain uses, they are validated by HandleMergeInputChains.
1418 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1421 SDNode *N = Use->getOperand(i).getNode();
1423 if (Use == ImmedUse || Use == Root)
1424 continue; // We are not looking for immediate use.
1429 // Traverse up the operand chain.
1430 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1436 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1437 /// operand node N of U during instruction selection that starts at Root.
1438 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1439 SDNode *Root) const {
1440 if (OptLevel == CodeGenOpt::None) return false;
1441 return N.hasOneUse();
1444 /// IsLegalToFold - Returns true if the specific operand node N of
1445 /// U can be folded during instruction selection that starts at Root.
1446 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1447 bool IgnoreChains) const {
1448 if (OptLevel == CodeGenOpt::None) return false;
1450 // If Root use can somehow reach N through a path that that doesn't contain
1451 // U then folding N would create a cycle. e.g. In the following
1452 // diagram, Root can reach N through X. If N is folded into into Root, then
1453 // X is both a predecessor and a successor of U.
1464 // * indicates nodes to be folded together.
1466 // If Root produces a flag, then it gets (even more) interesting. Since it
1467 // will be "glued" together with its flag use in the scheduler, we need to
1468 // check if it might reach N.
1487 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1488 // (call it Fold), then X is a predecessor of FU and a successor of
1489 // Fold. But since Fold and FU are flagged together, this will create
1490 // a cycle in the scheduling graph.
1492 // If the node has flags, walk down the graph to the "lowest" node in the
1494 EVT VT = Root->getValueType(Root->getNumValues()-1);
1495 while (VT == MVT::Flag) {
1496 SDNode *FU = findFlagUse(Root);
1500 VT = Root->getValueType(Root->getNumValues()-1);
1502 // If our query node has a flag result with a use, we've walked up it. If
1503 // the user (which has already been selected) has a chain or indirectly uses
1504 // the chain, our WalkChainUsers predicate will not consider it. Because of
1505 // this, we cannot ignore chains in this predicate.
1506 IgnoreChains = false;
1510 SmallPtrSet<SDNode*, 16> Visited;
1511 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1514 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1515 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1516 SelectInlineAsmMemoryOperands(Ops);
1518 std::vector<EVT> VTs;
1519 VTs.push_back(MVT::Other);
1520 VTs.push_back(MVT::Flag);
1521 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1522 VTs, &Ops[0], Ops.size());
1524 return New.getNode();
1527 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1528 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1531 /// GetVBR - decode a vbr encoding whose top bit is set.
1532 ALWAYS_INLINE static uint64_t
1533 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1534 assert(Val >= 128 && "Not a VBR");
1535 Val &= 127; // Remove first vbr bit.
1540 NextBits = MatcherTable[Idx++];
1541 Val |= (NextBits&127) << Shift;
1543 } while (NextBits & 128);
1549 /// UpdateChainsAndFlags - When a match is complete, this method updates uses of
1550 /// interior flag and chain results to use the new flag and chain results.
1551 void SelectionDAGISel::
1552 UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
1553 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1555 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched,
1556 bool isMorphNodeTo) {
1557 SmallVector<SDNode*, 4> NowDeadNodes;
1559 ISelUpdater ISU(ISelPosition);
1561 // Now that all the normal results are replaced, we replace the chain and
1562 // flag results if present.
1563 if (!ChainNodesMatched.empty()) {
1564 assert(InputChain.getNode() != 0 &&
1565 "Matched input chains but didn't produce a chain");
1566 // Loop over all of the nodes we matched that produced a chain result.
1567 // Replace all the chain results with the final chain we ended up with.
1568 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1569 SDNode *ChainNode = ChainNodesMatched[i];
1571 // If this node was already deleted, don't look at it.
1572 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1575 // Don't replace the results of the root node if we're doing a
1577 if (ChainNode == NodeToMatch && isMorphNodeTo)
1580 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1581 if (ChainVal.getValueType() == MVT::Flag)
1582 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1583 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1584 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1586 // If the node became dead and we haven't already seen it, delete it.
1587 if (ChainNode->use_empty() &&
1588 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1589 NowDeadNodes.push_back(ChainNode);
1593 // If the result produces a flag, update any flag results in the matched
1594 // pattern with the flag result.
1595 if (InputFlag.getNode() != 0) {
1596 // Handle any interior nodes explicitly marked.
1597 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) {
1598 SDNode *FRN = FlagResultNodesMatched[i];
1600 // If this node was already deleted, don't look at it.
1601 if (FRN->getOpcode() == ISD::DELETED_NODE)
1604 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag &&
1605 "Doesn't have a flag result");
1606 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1609 // If the node became dead and we haven't already seen it, delete it.
1610 if (FRN->use_empty() &&
1611 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1612 NowDeadNodes.push_back(FRN);
1616 if (!NowDeadNodes.empty())
1617 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1619 DEBUG(errs() << "ISEL: Match complete!\n");
1625 CR_LeadsToInteriorNode
1628 /// WalkChainUsers - Walk down the users of the specified chained node that is
1629 /// part of the pattern we're matching, looking at all of the users we find.
1630 /// This determines whether something is an interior node, whether we have a
1631 /// non-pattern node in between two pattern nodes (which prevent folding because
1632 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1633 /// between pattern nodes (in which case the TF becomes part of the pattern).
1635 /// The walk we do here is guaranteed to be small because we quickly get down to
1636 /// already selected nodes "below" us.
1638 WalkChainUsers(SDNode *ChainedNode,
1639 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1640 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1641 ChainResult Result = CR_Simple;
1643 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1644 E = ChainedNode->use_end(); UI != E; ++UI) {
1645 // Make sure the use is of the chain, not some other value we produce.
1646 if (UI.getUse().getValueType() != MVT::Other) continue;
1650 // If we see an already-selected machine node, then we've gone beyond the
1651 // pattern that we're selecting down into the already selected chunk of the
1653 if (User->isMachineOpcode() ||
1654 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1657 if (User->getOpcode() == ISD::CopyToReg ||
1658 User->getOpcode() == ISD::CopyFromReg ||
1659 User->getOpcode() == ISD::INLINEASM ||
1660 User->getOpcode() == ISD::EH_LABEL) {
1661 // If their node ID got reset to -1 then they've already been selected.
1662 // Treat them like a MachineOpcode.
1663 if (User->getNodeId() == -1)
1667 // If we have a TokenFactor, we handle it specially.
1668 if (User->getOpcode() != ISD::TokenFactor) {
1669 // If the node isn't a token factor and isn't part of our pattern, then it
1670 // must be a random chained node in between two nodes we're selecting.
1671 // This happens when we have something like:
1676 // Because we structurally match the load/store as a read/modify/write,
1677 // but the call is chained between them. We cannot fold in this case
1678 // because it would induce a cycle in the graph.
1679 if (!std::count(ChainedNodesInPattern.begin(),
1680 ChainedNodesInPattern.end(), User))
1681 return CR_InducesCycle;
1683 // Otherwise we found a node that is part of our pattern. For example in:
1687 // This would happen when we're scanning down from the load and see the
1688 // store as a user. Record that there is a use of ChainedNode that is
1689 // part of the pattern and keep scanning uses.
1690 Result = CR_LeadsToInteriorNode;
1691 InteriorChainedNodes.push_back(User);
1695 // If we found a TokenFactor, there are two cases to consider: first if the
1696 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1697 // uses of the TF are in our pattern) we just want to ignore it. Second,
1698 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1704 // | \ DAG's like cheese
1707 // [TokenFactor] [Op]
1714 // In this case, the TokenFactor becomes part of our match and we rewrite it
1715 // as a new TokenFactor.
1717 // To distinguish these two cases, do a recursive walk down the uses.
1718 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1720 // If the uses of the TokenFactor are just already-selected nodes, ignore
1721 // it, it is "below" our pattern.
1723 case CR_InducesCycle:
1724 // If the uses of the TokenFactor lead to nodes that are not part of our
1725 // pattern that are not selected, folding would turn this into a cycle,
1727 return CR_InducesCycle;
1728 case CR_LeadsToInteriorNode:
1729 break; // Otherwise, keep processing.
1732 // Okay, we know we're in the interesting interior case. The TokenFactor
1733 // is now going to be considered part of the pattern so that we rewrite its
1734 // uses (it may have uses that are not part of the pattern) with the
1735 // ultimate chain result of the generated code. We will also add its chain
1736 // inputs as inputs to the ultimate TokenFactor we create.
1737 Result = CR_LeadsToInteriorNode;
1738 ChainedNodesInPattern.push_back(User);
1739 InteriorChainedNodes.push_back(User);
1746 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1747 /// operation for when the pattern matched at least one node with a chains. The
1748 /// input vector contains a list of all of the chained nodes that we match. We
1749 /// must determine if this is a valid thing to cover (i.e. matching it won't
1750 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1751 /// be used as the input node chain for the generated nodes.
1753 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1754 SelectionDAG *CurDAG) {
1755 // Walk all of the chained nodes we've matched, recursively scanning down the
1756 // users of the chain result. This adds any TokenFactor nodes that are caught
1757 // in between chained nodes to the chained and interior nodes list.
1758 SmallVector<SDNode*, 3> InteriorChainedNodes;
1759 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1760 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1761 InteriorChainedNodes) == CR_InducesCycle)
1762 return SDValue(); // Would induce a cycle.
1765 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1766 // that we are interested in. Form our input TokenFactor node.
1767 SmallVector<SDValue, 3> InputChains;
1768 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1769 // Add the input chain of this node to the InputChains list (which will be
1770 // the operands of the generated TokenFactor) if it's not an interior node.
1771 SDNode *N = ChainNodesMatched[i];
1772 if (N->getOpcode() != ISD::TokenFactor) {
1773 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1776 // Otherwise, add the input chain.
1777 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1778 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1779 InputChains.push_back(InChain);
1783 // If we have a token factor, we want to add all inputs of the token factor
1784 // that are not part of the pattern we're matching.
1785 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1786 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1787 N->getOperand(op).getNode()))
1788 InputChains.push_back(N->getOperand(op));
1793 if (InputChains.size() == 1)
1794 return InputChains[0];
1795 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1796 MVT::Other, &InputChains[0], InputChains.size());
1799 /// MorphNode - Handle morphing a node in place for the selector.
1800 SDNode *SelectionDAGISel::
1801 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1802 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1803 // It is possible we're using MorphNodeTo to replace a node with no
1804 // normal results with one that has a normal result (or we could be
1805 // adding a chain) and the input could have flags and chains as well.
1806 // In this case we need to shift the operands down.
1807 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1808 // than the old isel though.
1809 int OldFlagResultNo = -1, OldChainResultNo = -1;
1811 unsigned NTMNumResults = Node->getNumValues();
1812 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) {
1813 OldFlagResultNo = NTMNumResults-1;
1814 if (NTMNumResults != 1 &&
1815 Node->getValueType(NTMNumResults-2) == MVT::Other)
1816 OldChainResultNo = NTMNumResults-2;
1817 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1818 OldChainResultNo = NTMNumResults-1;
1820 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1821 // that this deletes operands of the old node that become dead.
1822 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1824 // MorphNodeTo can operate in two ways: if an existing node with the
1825 // specified operands exists, it can just return it. Otherwise, it
1826 // updates the node in place to have the requested operands.
1828 // If we updated the node in place, reset the node ID. To the isel,
1829 // this should be just like a newly allocated machine node.
1833 unsigned ResNumResults = Res->getNumValues();
1834 // Move the flag if needed.
1835 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 &&
1836 (unsigned)OldFlagResultNo != ResNumResults-1)
1837 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo),
1838 SDValue(Res, ResNumResults-1));
1840 if ((EmitNodeInfo & OPFL_FlagOutput) != 0)
1843 // Move the chain reference if needed.
1844 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1845 (unsigned)OldChainResultNo != ResNumResults-1)
1846 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1847 SDValue(Res, ResNumResults-1));
1849 // Otherwise, no replacement happened because the node already exists. Replace
1850 // Uses of the old node with the new one.
1852 CurDAG->ReplaceAllUsesWith(Node, Res);
1857 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1858 ALWAYS_INLINE static bool
1859 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1860 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) {
1861 // Accept if it is exactly the same as a previously recorded node.
1862 unsigned RecNo = MatcherTable[MatcherIndex++];
1863 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1864 return N == RecordedNodes[RecNo];
1867 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1868 ALWAYS_INLINE static bool
1869 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1870 SelectionDAGISel &SDISel) {
1871 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1874 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1875 ALWAYS_INLINE static bool
1876 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1877 SelectionDAGISel &SDISel, SDNode *N) {
1878 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1881 ALWAYS_INLINE static bool
1882 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1884 uint16_t Opc = MatcherTable[MatcherIndex++];
1885 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1886 return N->getOpcode() == Opc;
1889 ALWAYS_INLINE static bool
1890 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1891 SDValue N, const TargetLowering &TLI) {
1892 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1893 if (N.getValueType() == VT) return true;
1895 // Handle the case when VT is iPTR.
1896 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1899 ALWAYS_INLINE static bool
1900 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1901 SDValue N, const TargetLowering &TLI,
1903 if (ChildNo >= N.getNumOperands())
1904 return false; // Match fails if out of range child #.
1905 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1909 ALWAYS_INLINE static bool
1910 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1912 return cast<CondCodeSDNode>(N)->get() ==
1913 (ISD::CondCode)MatcherTable[MatcherIndex++];
1916 ALWAYS_INLINE static bool
1917 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1918 SDValue N, const TargetLowering &TLI) {
1919 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1920 if (cast<VTSDNode>(N)->getVT() == VT)
1923 // Handle the case when VT is iPTR.
1924 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1927 ALWAYS_INLINE static bool
1928 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1930 int64_t Val = MatcherTable[MatcherIndex++];
1932 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1934 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1935 return C != 0 && C->getSExtValue() == Val;
1938 ALWAYS_INLINE static bool
1939 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1940 SDValue N, SelectionDAGISel &SDISel) {
1941 int64_t Val = MatcherTable[MatcherIndex++];
1943 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1945 if (N->getOpcode() != ISD::AND) return false;
1947 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1948 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1951 ALWAYS_INLINE static bool
1952 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1953 SDValue N, SelectionDAGISel &SDISel) {
1954 int64_t Val = MatcherTable[MatcherIndex++];
1956 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1958 if (N->getOpcode() != ISD::OR) return false;
1960 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1961 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1964 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1965 /// scope, evaluate the current node. If the current predicate is known to
1966 /// fail, set Result=true and return anything. If the current predicate is
1967 /// known to pass, set Result=false and return the MatcherIndex to continue
1968 /// with. If the current predicate is unknown, set Result=false and return the
1969 /// MatcherIndex to continue with.
1970 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1971 unsigned Index, SDValue N,
1972 bool &Result, SelectionDAGISel &SDISel,
1973 SmallVectorImpl<SDValue> &RecordedNodes){
1974 switch (Table[Index++]) {
1977 return Index-1; // Could not evaluate this predicate.
1978 case SelectionDAGISel::OPC_CheckSame:
1979 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1981 case SelectionDAGISel::OPC_CheckPatternPredicate:
1982 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1984 case SelectionDAGISel::OPC_CheckPredicate:
1985 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1987 case SelectionDAGISel::OPC_CheckOpcode:
1988 Result = !::CheckOpcode(Table, Index, N.getNode());
1990 case SelectionDAGISel::OPC_CheckType:
1991 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1993 case SelectionDAGISel::OPC_CheckChild0Type:
1994 case SelectionDAGISel::OPC_CheckChild1Type:
1995 case SelectionDAGISel::OPC_CheckChild2Type:
1996 case SelectionDAGISel::OPC_CheckChild3Type:
1997 case SelectionDAGISel::OPC_CheckChild4Type:
1998 case SelectionDAGISel::OPC_CheckChild5Type:
1999 case SelectionDAGISel::OPC_CheckChild6Type:
2000 case SelectionDAGISel::OPC_CheckChild7Type:
2001 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
2002 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
2004 case SelectionDAGISel::OPC_CheckCondCode:
2005 Result = !::CheckCondCode(Table, Index, N);
2007 case SelectionDAGISel::OPC_CheckValueType:
2008 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2010 case SelectionDAGISel::OPC_CheckInteger:
2011 Result = !::CheckInteger(Table, Index, N);
2013 case SelectionDAGISel::OPC_CheckAndImm:
2014 Result = !::CheckAndImm(Table, Index, N, SDISel);
2016 case SelectionDAGISel::OPC_CheckOrImm:
2017 Result = !::CheckOrImm(Table, Index, N, SDISel);
2024 /// FailIndex - If this match fails, this is the index to continue with.
2027 /// NodeStack - The node stack when the scope was formed.
2028 SmallVector<SDValue, 4> NodeStack;
2030 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2031 unsigned NumRecordedNodes;
2033 /// NumMatchedMemRefs - The number of matched memref entries.
2034 unsigned NumMatchedMemRefs;
2036 /// InputChain/InputFlag - The current chain/flag
2037 SDValue InputChain, InputFlag;
2039 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2040 bool HasChainNodesMatched, HasFlagResultNodesMatched;
2043 SDNode *SelectionDAGISel::
2044 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2045 unsigned TableSize) {
2046 // FIXME: Should these even be selected? Handle these cases in the caller?
2047 switch (NodeToMatch->getOpcode()) {
2050 case ISD::EntryToken: // These nodes remain the same.
2051 case ISD::BasicBlock:
2053 //case ISD::VALUETYPE:
2054 //case ISD::CONDCODE:
2055 case ISD::HANDLENODE:
2056 case ISD::TargetConstant:
2057 case ISD::TargetConstantFP:
2058 case ISD::TargetConstantPool:
2059 case ISD::TargetFrameIndex:
2060 case ISD::TargetExternalSymbol:
2061 case ISD::TargetBlockAddress:
2062 case ISD::TargetJumpTable:
2063 case ISD::TargetGlobalTLSAddress:
2064 case ISD::TargetGlobalAddress:
2065 case ISD::TokenFactor:
2066 case ISD::CopyFromReg:
2067 case ISD::CopyToReg:
2069 NodeToMatch->setNodeId(-1); // Mark selected.
2071 case ISD::AssertSext:
2072 case ISD::AssertZext:
2073 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2074 NodeToMatch->getOperand(0));
2076 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2077 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2080 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2082 // Set up the node stack with NodeToMatch as the only node on the stack.
2083 SmallVector<SDValue, 8> NodeStack;
2084 SDValue N = SDValue(NodeToMatch, 0);
2085 NodeStack.push_back(N);
2087 // MatchScopes - Scopes used when matching, if a match failure happens, this
2088 // indicates where to continue checking.
2089 SmallVector<MatchScope, 8> MatchScopes;
2091 // RecordedNodes - This is the set of nodes that have been recorded by the
2093 SmallVector<SDValue, 8> RecordedNodes;
2095 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2097 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2099 // These are the current input chain and flag for use when generating nodes.
2100 // Various Emit operations change these. For example, emitting a copytoreg
2101 // uses and updates these.
2102 SDValue InputChain, InputFlag;
2104 // ChainNodesMatched - If a pattern matches nodes that have input/output
2105 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2106 // which ones they are. The result is captured into this list so that we can
2107 // update the chain results when the pattern is complete.
2108 SmallVector<SDNode*, 3> ChainNodesMatched;
2109 SmallVector<SDNode*, 3> FlagResultNodesMatched;
2111 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2112 NodeToMatch->dump(CurDAG);
2115 // Determine where to start the interpreter. Normally we start at opcode #0,
2116 // but if the state machine starts with an OPC_SwitchOpcode, then we
2117 // accelerate the first lookup (which is guaranteed to be hot) with the
2118 // OpcodeOffset table.
2119 unsigned MatcherIndex = 0;
2121 if (!OpcodeOffset.empty()) {
2122 // Already computed the OpcodeOffset table, just index into it.
2123 if (N.getOpcode() < OpcodeOffset.size())
2124 MatcherIndex = OpcodeOffset[N.getOpcode()];
2125 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2127 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2128 // Otherwise, the table isn't computed, but the state machine does start
2129 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2130 // is the first time we're selecting an instruction.
2133 // Get the size of this case.
2134 unsigned CaseSize = MatcherTable[Idx++];
2136 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2137 if (CaseSize == 0) break;
2139 // Get the opcode, add the index to the table.
2140 uint16_t Opc = MatcherTable[Idx++];
2141 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2142 if (Opc >= OpcodeOffset.size())
2143 OpcodeOffset.resize((Opc+1)*2);
2144 OpcodeOffset[Opc] = Idx;
2148 // Okay, do the lookup for the first opcode.
2149 if (N.getOpcode() < OpcodeOffset.size())
2150 MatcherIndex = OpcodeOffset[N.getOpcode()];
2154 assert(MatcherIndex < TableSize && "Invalid index");
2156 unsigned CurrentOpcodeIndex = MatcherIndex;
2158 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2161 // Okay, the semantics of this operation are that we should push a scope
2162 // then evaluate the first child. However, pushing a scope only to have
2163 // the first check fail (which then pops it) is inefficient. If we can
2164 // determine immediately that the first check (or first several) will
2165 // immediately fail, don't even bother pushing a scope for them.
2169 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2170 if (NumToSkip & 128)
2171 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2172 // Found the end of the scope with no match.
2173 if (NumToSkip == 0) {
2178 FailIndex = MatcherIndex+NumToSkip;
2180 unsigned MatcherIndexOfPredicate = MatcherIndex;
2181 (void)MatcherIndexOfPredicate; // silence warning.
2183 // If we can't evaluate this predicate without pushing a scope (e.g. if
2184 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2185 // push the scope and evaluate the full predicate chain.
2187 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2188 Result, *this, RecordedNodes);
2192 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2193 << "index " << MatcherIndexOfPredicate
2194 << ", continuing at " << FailIndex << "\n");
2195 ++NumDAGIselRetries;
2197 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2198 // move to the next case.
2199 MatcherIndex = FailIndex;
2202 // If the whole scope failed to match, bail.
2203 if (FailIndex == 0) break;
2205 // Push a MatchScope which indicates where to go if the first child fails
2207 MatchScope NewEntry;
2208 NewEntry.FailIndex = FailIndex;
2209 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2210 NewEntry.NumRecordedNodes = RecordedNodes.size();
2211 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2212 NewEntry.InputChain = InputChain;
2213 NewEntry.InputFlag = InputFlag;
2214 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2215 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty();
2216 MatchScopes.push_back(NewEntry);
2219 case OPC_RecordNode:
2220 // Remember this node, it may end up being an operand in the pattern.
2221 RecordedNodes.push_back(N);
2224 case OPC_RecordChild0: case OPC_RecordChild1:
2225 case OPC_RecordChild2: case OPC_RecordChild3:
2226 case OPC_RecordChild4: case OPC_RecordChild5:
2227 case OPC_RecordChild6: case OPC_RecordChild7: {
2228 unsigned ChildNo = Opcode-OPC_RecordChild0;
2229 if (ChildNo >= N.getNumOperands())
2230 break; // Match fails if out of range child #.
2232 RecordedNodes.push_back(N->getOperand(ChildNo));
2235 case OPC_RecordMemRef:
2236 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2239 case OPC_CaptureFlagInput:
2240 // If the current node has an input flag, capture it in InputFlag.
2241 if (N->getNumOperands() != 0 &&
2242 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag)
2243 InputFlag = N->getOperand(N->getNumOperands()-1);
2246 case OPC_MoveChild: {
2247 unsigned ChildNo = MatcherTable[MatcherIndex++];
2248 if (ChildNo >= N.getNumOperands())
2249 break; // Match fails if out of range child #.
2250 N = N.getOperand(ChildNo);
2251 NodeStack.push_back(N);
2255 case OPC_MoveParent:
2256 // Pop the current node off the NodeStack.
2257 NodeStack.pop_back();
2258 assert(!NodeStack.empty() && "Node stack imbalance!");
2259 N = NodeStack.back();
2263 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2265 case OPC_CheckPatternPredicate:
2266 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2268 case OPC_CheckPredicate:
2269 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2273 case OPC_CheckComplexPat: {
2274 unsigned CPNum = MatcherTable[MatcherIndex++];
2275 unsigned RecNo = MatcherTable[MatcherIndex++];
2276 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2277 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum,
2282 case OPC_CheckOpcode:
2283 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2287 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2290 case OPC_SwitchOpcode: {
2291 unsigned CurNodeOpcode = N.getOpcode();
2292 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2295 // Get the size of this case.
2296 CaseSize = MatcherTable[MatcherIndex++];
2298 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2299 if (CaseSize == 0) break;
2301 uint16_t Opc = MatcherTable[MatcherIndex++];
2302 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2304 // If the opcode matches, then we will execute this case.
2305 if (CurNodeOpcode == Opc)
2308 // Otherwise, skip over this case.
2309 MatcherIndex += CaseSize;
2312 // If no cases matched, bail out.
2313 if (CaseSize == 0) break;
2315 // Otherwise, execute the case we found.
2316 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2317 << " to " << MatcherIndex << "\n");
2321 case OPC_SwitchType: {
2322 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy;
2323 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2326 // Get the size of this case.
2327 CaseSize = MatcherTable[MatcherIndex++];
2329 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2330 if (CaseSize == 0) break;
2332 MVT::SimpleValueType CaseVT =
2333 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2334 if (CaseVT == MVT::iPTR)
2335 CaseVT = TLI.getPointerTy().SimpleTy;
2337 // If the VT matches, then we will execute this case.
2338 if (CurNodeVT == CaseVT)
2341 // Otherwise, skip over this case.
2342 MatcherIndex += CaseSize;
2345 // If no cases matched, bail out.
2346 if (CaseSize == 0) break;
2348 // Otherwise, execute the case we found.
2349 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2350 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2353 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2354 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2355 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2356 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2357 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2358 Opcode-OPC_CheckChild0Type))
2361 case OPC_CheckCondCode:
2362 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2364 case OPC_CheckValueType:
2365 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2367 case OPC_CheckInteger:
2368 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2370 case OPC_CheckAndImm:
2371 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2373 case OPC_CheckOrImm:
2374 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2377 case OPC_CheckFoldableChainNode: {
2378 assert(NodeStack.size() != 1 && "No parent node");
2379 // Verify that all intermediate nodes between the root and this one have
2381 bool HasMultipleUses = false;
2382 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2383 if (!NodeStack[i].hasOneUse()) {
2384 HasMultipleUses = true;
2387 if (HasMultipleUses) break;
2389 // Check to see that the target thinks this is profitable to fold and that
2390 // we can fold it without inducing cycles in the graph.
2391 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2393 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2394 NodeToMatch, true/*We validate our own chains*/))
2399 case OPC_EmitInteger: {
2400 MVT::SimpleValueType VT =
2401 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2402 int64_t Val = MatcherTable[MatcherIndex++];
2404 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2405 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT));
2408 case OPC_EmitRegister: {
2409 MVT::SimpleValueType VT =
2410 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2411 unsigned RegNo = MatcherTable[MatcherIndex++];
2412 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT));
2416 case OPC_EmitConvertToTarget: {
2417 // Convert from IMM/FPIMM to target version.
2418 unsigned RecNo = MatcherTable[MatcherIndex++];
2419 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2420 SDValue Imm = RecordedNodes[RecNo];
2422 if (Imm->getOpcode() == ISD::Constant) {
2423 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2424 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2425 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2426 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2427 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2430 RecordedNodes.push_back(Imm);
2434 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2435 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2436 // These are space-optimized forms of OPC_EmitMergeInputChains.
2437 assert(InputChain.getNode() == 0 &&
2438 "EmitMergeInputChains should be the first chain producing node");
2439 assert(ChainNodesMatched.empty() &&
2440 "Should only have one EmitMergeInputChains per match");
2442 // Read all of the chained nodes.
2443 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2444 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2445 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2447 // FIXME: What if other value results of the node have uses not matched
2449 if (ChainNodesMatched.back() != NodeToMatch &&
2450 !RecordedNodes[RecNo].hasOneUse()) {
2451 ChainNodesMatched.clear();
2455 // Merge the input chains if they are not intra-pattern references.
2456 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2458 if (InputChain.getNode() == 0)
2459 break; // Failed to merge.
2463 case OPC_EmitMergeInputChains: {
2464 assert(InputChain.getNode() == 0 &&
2465 "EmitMergeInputChains should be the first chain producing node");
2466 // This node gets a list of nodes we matched in the input that have
2467 // chains. We want to token factor all of the input chains to these nodes
2468 // together. However, if any of the input chains is actually one of the
2469 // nodes matched in this pattern, then we have an intra-match reference.
2470 // Ignore these because the newly token factored chain should not refer to
2472 unsigned NumChains = MatcherTable[MatcherIndex++];
2473 assert(NumChains != 0 && "Can't TF zero chains");
2475 assert(ChainNodesMatched.empty() &&
2476 "Should only have one EmitMergeInputChains per match");
2478 // Read all of the chained nodes.
2479 for (unsigned i = 0; i != NumChains; ++i) {
2480 unsigned RecNo = MatcherTable[MatcherIndex++];
2481 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2482 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2484 // FIXME: What if other value results of the node have uses not matched
2486 if (ChainNodesMatched.back() != NodeToMatch &&
2487 !RecordedNodes[RecNo].hasOneUse()) {
2488 ChainNodesMatched.clear();
2493 // If the inner loop broke out, the match fails.
2494 if (ChainNodesMatched.empty())
2497 // Merge the input chains if they are not intra-pattern references.
2498 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2500 if (InputChain.getNode() == 0)
2501 break; // Failed to merge.
2506 case OPC_EmitCopyToReg: {
2507 unsigned RecNo = MatcherTable[MatcherIndex++];
2508 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2509 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2511 if (InputChain.getNode() == 0)
2512 InputChain = CurDAG->getEntryNode();
2514 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2515 DestPhysReg, RecordedNodes[RecNo],
2518 InputFlag = InputChain.getValue(1);
2522 case OPC_EmitNodeXForm: {
2523 unsigned XFormNo = MatcherTable[MatcherIndex++];
2524 unsigned RecNo = MatcherTable[MatcherIndex++];
2525 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2526 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo));
2531 case OPC_MorphNodeTo: {
2532 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2533 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2534 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2535 // Get the result VT list.
2536 unsigned NumVTs = MatcherTable[MatcherIndex++];
2537 SmallVector<EVT, 4> VTs;
2538 for (unsigned i = 0; i != NumVTs; ++i) {
2539 MVT::SimpleValueType VT =
2540 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2541 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2545 if (EmitNodeInfo & OPFL_Chain)
2546 VTs.push_back(MVT::Other);
2547 if (EmitNodeInfo & OPFL_FlagOutput)
2548 VTs.push_back(MVT::Flag);
2550 // This is hot code, so optimize the two most common cases of 1 and 2
2553 if (VTs.size() == 1)
2554 VTList = CurDAG->getVTList(VTs[0]);
2555 else if (VTs.size() == 2)
2556 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2558 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2560 // Get the operand list.
2561 unsigned NumOps = MatcherTable[MatcherIndex++];
2562 SmallVector<SDValue, 8> Ops;
2563 for (unsigned i = 0; i != NumOps; ++i) {
2564 unsigned RecNo = MatcherTable[MatcherIndex++];
2566 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2568 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2569 Ops.push_back(RecordedNodes[RecNo]);
2572 // If there are variadic operands to add, handle them now.
2573 if (EmitNodeInfo & OPFL_VariadicInfo) {
2574 // Determine the start index to copy from.
2575 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2576 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2577 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2578 "Invalid variadic node");
2579 // Copy all of the variadic operands, not including a potential flag
2581 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2583 SDValue V = NodeToMatch->getOperand(i);
2584 if (V.getValueType() == MVT::Flag) break;
2589 // If this has chain/flag inputs, add them.
2590 if (EmitNodeInfo & OPFL_Chain)
2591 Ops.push_back(InputChain);
2592 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0)
2593 Ops.push_back(InputFlag);
2597 if (Opcode != OPC_MorphNodeTo) {
2598 // If this is a normal EmitNode command, just create the new node and
2599 // add the results to the RecordedNodes list.
2600 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2601 VTList, Ops.data(), Ops.size());
2603 // Add all the non-flag/non-chain results to the RecordedNodes list.
2604 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2605 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
2606 RecordedNodes.push_back(SDValue(Res, i));
2610 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2614 // If the node had chain/flag results, update our notion of the current
2616 if (EmitNodeInfo & OPFL_FlagOutput) {
2617 InputFlag = SDValue(Res, VTs.size()-1);
2618 if (EmitNodeInfo & OPFL_Chain)
2619 InputChain = SDValue(Res, VTs.size()-2);
2620 } else if (EmitNodeInfo & OPFL_Chain)
2621 InputChain = SDValue(Res, VTs.size()-1);
2623 // If the OPFL_MemRefs flag is set on this node, slap all of the
2624 // accumulated memrefs onto it.
2626 // FIXME: This is vastly incorrect for patterns with multiple outputs
2627 // instructions that access memory and for ComplexPatterns that match
2629 if (EmitNodeInfo & OPFL_MemRefs) {
2630 MachineSDNode::mmo_iterator MemRefs =
2631 MF->allocateMemRefsArray(MatchedMemRefs.size());
2632 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2633 cast<MachineSDNode>(Res)
2634 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2638 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2639 << " node: "; Res->dump(CurDAG); errs() << "\n");
2641 // If this was a MorphNodeTo then we're completely done!
2642 if (Opcode == OPC_MorphNodeTo) {
2643 // Update chain and flag uses.
2644 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2645 InputFlag, FlagResultNodesMatched, true);
2652 case OPC_MarkFlagResults: {
2653 unsigned NumNodes = MatcherTable[MatcherIndex++];
2655 // Read and remember all the flag-result nodes.
2656 for (unsigned i = 0; i != NumNodes; ++i) {
2657 unsigned RecNo = MatcherTable[MatcherIndex++];
2659 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2661 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2662 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2667 case OPC_CompleteMatch: {
2668 // The match has been completed, and any new nodes (if any) have been
2669 // created. Patch up references to the matched dag to use the newly
2671 unsigned NumResults = MatcherTable[MatcherIndex++];
2673 for (unsigned i = 0; i != NumResults; ++i) {
2674 unsigned ResSlot = MatcherTable[MatcherIndex++];
2676 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2678 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2679 SDValue Res = RecordedNodes[ResSlot];
2681 assert(i < NodeToMatch->getNumValues() &&
2682 NodeToMatch->getValueType(i) != MVT::Other &&
2683 NodeToMatch->getValueType(i) != MVT::Flag &&
2684 "Invalid number of results to complete!");
2685 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2686 NodeToMatch->getValueType(i) == MVT::iPTR ||
2687 Res.getValueType() == MVT::iPTR ||
2688 NodeToMatch->getValueType(i).getSizeInBits() ==
2689 Res.getValueType().getSizeInBits()) &&
2690 "invalid replacement");
2691 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2694 // If the root node defines a flag, add it to the flag nodes to update
2696 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag)
2697 FlagResultNodesMatched.push_back(NodeToMatch);
2699 // Update chain and flag uses.
2700 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2701 InputFlag, FlagResultNodesMatched, false);
2703 assert(NodeToMatch->use_empty() &&
2704 "Didn't replace all uses of the node?");
2706 // FIXME: We just return here, which interacts correctly with SelectRoot
2707 // above. We should fix this to not return an SDNode* anymore.
2712 // If the code reached this point, then the match failed. See if there is
2713 // another child to try in the current 'Scope', otherwise pop it until we
2714 // find a case to check.
2715 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2716 ++NumDAGIselRetries;
2718 if (MatchScopes.empty()) {
2719 CannotYetSelect(NodeToMatch);
2723 // Restore the interpreter state back to the point where the scope was
2725 MatchScope &LastScope = MatchScopes.back();
2726 RecordedNodes.resize(LastScope.NumRecordedNodes);
2728 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2729 N = NodeStack.back();
2731 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2732 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2733 MatcherIndex = LastScope.FailIndex;
2735 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2737 InputChain = LastScope.InputChain;
2738 InputFlag = LastScope.InputFlag;
2739 if (!LastScope.HasChainNodesMatched)
2740 ChainNodesMatched.clear();
2741 if (!LastScope.HasFlagResultNodesMatched)
2742 FlagResultNodesMatched.clear();
2744 // Check to see what the offset is at the new MatcherIndex. If it is zero
2745 // we have reached the end of this scope, otherwise we have another child
2746 // in the current scope to try.
2747 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2748 if (NumToSkip & 128)
2749 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2751 // If we have another child in this scope to match, update FailIndex and
2753 if (NumToSkip != 0) {
2754 LastScope.FailIndex = MatcherIndex+NumToSkip;
2758 // End of this scope, pop it and try the next child in the containing
2760 MatchScopes.pop_back();
2767 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2769 raw_string_ostream Msg(msg);
2770 Msg << "Cannot yet select: ";
2772 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2773 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2774 N->getOpcode() != ISD::INTRINSIC_VOID) {
2775 N->printrFull(Msg, CurDAG);
2777 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2779 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2780 if (iid < Intrinsic::num_intrinsics)
2781 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2782 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2783 Msg << "target intrinsic %" << TII->getName(iid);
2785 Msg << "unknown intrinsic #" << iid;
2787 llvm_report_error(Msg.str());
2790 char SelectionDAGISel::ID = 0;