1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/LLVMContext.h"
28 #include "llvm/CodeGen/FastISel.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/GCMetadata.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
36 #include "llvm/CodeGen/SchedulerRegistry.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetIntrinsicInfo.h"
40 #include "llvm/Target/TargetInstrInfo.h"
41 #include "llvm/Target/TargetLowering.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetOptions.h"
44 #include "llvm/Support/Compiler.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/Timer.h"
48 #include "llvm/Support/raw_ostream.h"
49 #include "llvm/ADT/Statistic.h"
53 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
54 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
57 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
58 cl::desc("Enable verbose messages in the \"fast\" "
59 "instruction selector"));
61 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
62 cl::desc("Enable abort calls when \"fast\" instruction fails"));
66 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
67 cl::desc("Pop up a window to show dags before the first "
70 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
71 cl::desc("Pop up a window to show dags before legalize types"));
73 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
74 cl::desc("Pop up a window to show dags before legalize"));
76 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
77 cl::desc("Pop up a window to show dags before the second "
80 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
81 cl::desc("Pop up a window to show dags before the post legalize types"
82 " dag combine pass"));
84 ViewISelDAGs("view-isel-dags", cl::Hidden,
85 cl::desc("Pop up a window to show isel dags as they are selected"));
87 ViewSchedDAGs("view-sched-dags", cl::Hidden,
88 cl::desc("Pop up a window to show sched dags as they are processed"));
90 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
91 cl::desc("Pop up a window to show SUnit dags after they are processed"));
93 static const bool ViewDAGCombine1 = false,
94 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
95 ViewDAGCombine2 = false,
96 ViewDAGCombineLT = false,
97 ViewISelDAGs = false, ViewSchedDAGs = false,
98 ViewSUnitDAGs = false;
101 //===---------------------------------------------------------------------===//
103 /// RegisterScheduler class - Track the registration of instruction schedulers.
105 //===---------------------------------------------------------------------===//
106 MachinePassRegistry RegisterScheduler::Registry;
108 //===---------------------------------------------------------------------===//
110 /// ISHeuristic command line option for instruction schedulers.
112 //===---------------------------------------------------------------------===//
113 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
114 RegisterPassParser<RegisterScheduler> >
115 ISHeuristic("pre-RA-sched",
116 cl::init(&createDefaultScheduler),
117 cl::desc("Instruction schedulers available (before register"
120 static RegisterScheduler
121 defaultListDAGScheduler("default", "Best scheduler for the target",
122 createDefaultScheduler);
125 //===--------------------------------------------------------------------===//
126 /// createDefaultScheduler - This creates an instruction scheduler appropriate
128 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
129 CodeGenOpt::Level OptLevel) {
130 const TargetLowering &TLI = IS->getTargetLowering();
132 if (OptLevel == CodeGenOpt::None)
133 return createFastDAGScheduler(IS, OptLevel);
134 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
135 return createTDListDAGScheduler(IS, OptLevel);
136 assert(TLI.getSchedulingPreference() ==
137 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
138 return createBURRListDAGScheduler(IS, OptLevel);
142 // EmitInstrWithCustomInserter - This method should be implemented by targets
143 // that mark instructions with the 'usesCustomInserter' flag. These
144 // instructions are special in various ways, which require special support to
145 // insert. The specified MachineInstr is created but not inserted into any
146 // basic blocks, and this method is called to expand it into a sequence of
147 // instructions, potentially also creating new basic blocks and control flow.
148 // When new basic blocks are inserted and the edges from MBB to its successors
149 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
152 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
153 MachineBasicBlock *MBB) const {
155 dbgs() << "If a target marks an instruction with "
156 "'usesCustomInserter', it must implement "
157 "TargetLowering::EmitInstrWithCustomInserter!";
163 //===----------------------------------------------------------------------===//
164 // SelectionDAGISel code
165 //===----------------------------------------------------------------------===//
167 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, CodeGenOpt::Level OL) :
168 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
169 FuncInfo(new FunctionLoweringInfo(TLI)),
170 CurDAG(new SelectionDAG(tm, *FuncInfo)),
171 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
177 SelectionDAGISel::~SelectionDAGISel() {
183 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
184 AU.addRequired<AliasAnalysis>();
185 AU.addPreserved<AliasAnalysis>();
186 AU.addRequired<GCModuleInfo>();
187 AU.addPreserved<GCModuleInfo>();
188 MachineFunctionPass::getAnalysisUsage(AU);
191 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
192 // Do some sanity-checking on the command-line options.
193 assert((!EnableFastISelVerbose || EnableFastISel) &&
194 "-fast-isel-verbose requires -fast-isel");
195 assert((!EnableFastISelAbort || EnableFastISel) &&
196 "-fast-isel-abort requires -fast-isel");
198 const Function &Fn = *mf.getFunction();
199 const TargetInstrInfo &TII = *TM.getInstrInfo();
200 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
203 RegInfo = &MF->getRegInfo();
204 AA = &getAnalysis<AliasAnalysis>();
205 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
207 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
210 FuncInfo->set(Fn, *MF, EnableFastISel);
213 SelectAllBasicBlocks(Fn);
215 // If the first basic block in the function has live ins that need to be
216 // copied into vregs, emit the copies into the top of the block before
217 // emitting the code for the block.
218 MachineBasicBlock *EntryMBB = MF->begin();
219 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
221 // Insert DBG_VALUE instructions for function arguments to the entry block.
222 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
223 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
224 unsigned Reg = MI->getOperand(0).getReg();
225 if (TargetRegisterInfo::isPhysicalRegister(Reg))
226 EntryMBB->insert(EntryMBB->begin(), MI);
228 MachineInstr *Def = RegInfo->getVRegDef(Reg);
229 MachineBasicBlock::iterator InsertPos = Def;
230 EntryMBB->insert(llvm::next(InsertPos), MI);
234 // Release function-specific state. SDB and CurDAG are already cleared
242 SelectionDAGISel::SelectBasicBlock(MachineBasicBlock *BB,
243 const BasicBlock *LLVMBB,
244 BasicBlock::const_iterator Begin,
245 BasicBlock::const_iterator End,
247 // Lower all of the non-terminator instructions. If a call is emitted
248 // as a tail call, cease emitting nodes for this block. Terminators
249 // are handled below.
250 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
253 // Make sure the root of the DAG is up-to-date.
254 CurDAG->setRoot(SDB->getControlRoot());
255 HadTailCall = SDB->HasTailCall;
258 // Final step, emit the lowered DAG as machine code.
259 return CodeGenAndEmitDAG(BB);
263 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
264 /// nodes from the worklist.
265 class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener {
266 SmallVector<SDNode*, 128> &Worklist;
267 SmallPtrSet<SDNode*, 128> &InWorklist;
269 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl,
270 SmallPtrSet<SDNode*, 128> &inwl)
271 : Worklist(wl), InWorklist(inwl) {}
273 void RemoveFromWorklist(SDNode *N) {
274 if (!InWorklist.erase(N)) return;
276 SmallVector<SDNode*, 128>::iterator I =
277 std::find(Worklist.begin(), Worklist.end(), N);
278 assert(I != Worklist.end() && "Not in worklist");
280 *I = Worklist.back();
284 virtual void NodeDeleted(SDNode *N, SDNode *E) {
285 RemoveFromWorklist(N);
288 virtual void NodeUpdated(SDNode *N) {
294 /// TrivialTruncElim - Eliminate some trivial nops that can result from
295 /// ShrinkDemandedOps: (trunc (ext n)) -> n.
296 static bool TrivialTruncElim(SDValue Op,
297 TargetLowering::TargetLoweringOpt &TLO) {
298 SDValue N0 = Op.getOperand(0);
299 EVT VT = Op.getValueType();
300 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
301 N0.getOpcode() == ISD::SIGN_EXTEND ||
302 N0.getOpcode() == ISD::ANY_EXTEND) &&
303 N0.getOperand(0).getValueType() == VT) {
304 return TLO.CombineTo(Op, N0.getOperand(0));
309 /// ShrinkDemandedOps - A late transformation pass that shrink expressions
310 /// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts
311 /// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
312 void SelectionDAGISel::ShrinkDemandedOps() {
313 SmallVector<SDNode*, 128> Worklist;
314 SmallPtrSet<SDNode*, 128> InWorklist;
316 // Add all the dag nodes to the worklist.
317 Worklist.reserve(CurDAG->allnodes_size());
318 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
319 E = CurDAG->allnodes_end(); I != E; ++I) {
320 Worklist.push_back(I);
321 InWorklist.insert(I);
324 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true, true, true);
325 while (!Worklist.empty()) {
326 SDNode *N = Worklist.pop_back_val();
329 if (N->use_empty() && N != CurDAG->getRoot().getNode()) {
330 // Deleting this node may make its operands dead, add them to the worklist
331 // if they aren't already there.
332 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
333 if (InWorklist.insert(N->getOperand(i).getNode()))
334 Worklist.push_back(N->getOperand(i).getNode());
336 CurDAG->DeleteNode(N);
340 // Run ShrinkDemandedOp on scalar binary operations.
341 if (N->getNumValues() != 1 ||
342 !N->getValueType(0).isSimple() || !N->getValueType(0).isInteger())
345 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
346 APInt Demanded = APInt::getAllOnesValue(BitWidth);
347 APInt KnownZero, KnownOne;
348 if (!TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded,
349 KnownZero, KnownOne, TLO) &&
350 (N->getOpcode() != ISD::TRUNCATE ||
351 !TrivialTruncElim(SDValue(N, 0), TLO)))
355 assert(!InWorklist.count(N) && "Already in worklist");
356 Worklist.push_back(N);
357 InWorklist.insert(N);
359 // Replace the old value with the new one.
360 DEBUG(errs() << "\nShrinkDemandedOps replacing ";
361 TLO.Old.getNode()->dump(CurDAG);
362 errs() << "\nWith: ";
363 TLO.New.getNode()->dump(CurDAG);
366 if (InWorklist.insert(TLO.New.getNode()))
367 Worklist.push_back(TLO.New.getNode());
369 SDOPsWorkListRemover DeadNodes(Worklist, InWorklist);
370 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
372 if (!TLO.Old.getNode()->use_empty()) continue;
374 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands();
376 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode();
377 if (OpNode->hasOneUse()) {
378 // Add OpNode to the end of the list to revisit.
379 DeadNodes.RemoveFromWorklist(OpNode);
380 Worklist.push_back(OpNode);
381 InWorklist.insert(OpNode);
385 DeadNodes.RemoveFromWorklist(TLO.Old.getNode());
386 CurDAG->DeleteNode(TLO.Old.getNode());
390 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
391 SmallPtrSet<SDNode*, 128> VisitedNodes;
392 SmallVector<SDNode*, 128> Worklist;
394 Worklist.push_back(CurDAG->getRoot().getNode());
401 SDNode *N = Worklist.pop_back_val();
403 // If we've already seen this node, ignore it.
404 if (!VisitedNodes.insert(N))
407 // Otherwise, add all chain operands to the worklist.
408 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
409 if (N->getOperand(i).getValueType() == MVT::Other)
410 Worklist.push_back(N->getOperand(i).getNode());
412 // If this is a CopyToReg with a vreg dest, process it.
413 if (N->getOpcode() != ISD::CopyToReg)
416 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
417 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
420 // Ignore non-scalar or non-integer values.
421 SDValue Src = N->getOperand(2);
422 EVT SrcVT = Src.getValueType();
423 if (!SrcVT.isInteger() || SrcVT.isVector())
426 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
427 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
428 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
430 // Only install this information if it tells us something.
431 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
432 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
433 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
434 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
435 FunctionLoweringInfo::LiveOutInfo &LOI =
436 FuncInfo->LiveOutRegInfo[DestReg];
437 LOI.NumSignBits = NumSignBits;
438 LOI.KnownOne = KnownOne;
439 LOI.KnownZero = KnownZero;
441 } while (!Worklist.empty());
444 MachineBasicBlock *SelectionDAGISel::CodeGenAndEmitDAG(MachineBasicBlock *BB) {
445 std::string GroupName;
446 if (TimePassesIsEnabled)
447 GroupName = "Instruction Selection and Scheduling";
448 std::string BlockName;
449 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
450 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
452 BlockName = MF->getFunction()->getNameStr() + ":" +
453 BB->getBasicBlock()->getNameStr();
455 DEBUG(dbgs() << "Initial selection DAG:\n");
456 DEBUG(CurDAG->dump());
458 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
460 // Run the DAG combiner in pre-legalize mode.
461 if (TimePassesIsEnabled) {
462 NamedRegionTimer T("DAG Combining 1", GroupName);
463 CurDAG->Combine(Unrestricted, *AA, OptLevel);
465 CurDAG->Combine(Unrestricted, *AA, OptLevel);
468 DEBUG(dbgs() << "Optimized lowered selection DAG:\n");
469 DEBUG(CurDAG->dump());
471 // Second step, hack on the DAG until it only uses operations and types that
472 // the target supports.
473 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
477 if (TimePassesIsEnabled) {
478 NamedRegionTimer T("Type Legalization", GroupName);
479 Changed = CurDAG->LegalizeTypes();
481 Changed = CurDAG->LegalizeTypes();
484 DEBUG(dbgs() << "Type-legalized selection DAG:\n");
485 DEBUG(CurDAG->dump());
488 if (ViewDAGCombineLT)
489 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
491 // Run the DAG combiner in post-type-legalize mode.
492 if (TimePassesIsEnabled) {
493 NamedRegionTimer T("DAG Combining after legalize types", GroupName);
494 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
496 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
499 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n");
500 DEBUG(CurDAG->dump());
503 if (TimePassesIsEnabled) {
504 NamedRegionTimer T("Vector Legalization", GroupName);
505 Changed = CurDAG->LegalizeVectors();
507 Changed = CurDAG->LegalizeVectors();
511 if (TimePassesIsEnabled) {
512 NamedRegionTimer T("Type Legalization 2", GroupName);
513 CurDAG->LegalizeTypes();
515 CurDAG->LegalizeTypes();
518 if (ViewDAGCombineLT)
519 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
521 // Run the DAG combiner in post-type-legalize mode.
522 if (TimePassesIsEnabled) {
523 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName);
524 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
526 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
529 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n");
530 DEBUG(CurDAG->dump());
533 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
535 if (TimePassesIsEnabled) {
536 NamedRegionTimer T("DAG Legalization", GroupName);
537 CurDAG->Legalize(OptLevel);
539 CurDAG->Legalize(OptLevel);
542 DEBUG(dbgs() << "Legalized selection DAG:\n");
543 DEBUG(CurDAG->dump());
545 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
547 // Run the DAG combiner in post-legalize mode.
548 if (TimePassesIsEnabled) {
549 NamedRegionTimer T("DAG Combining 2", GroupName);
550 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
552 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
555 DEBUG(dbgs() << "Optimized legalized selection DAG:\n");
556 DEBUG(CurDAG->dump());
558 if (OptLevel != CodeGenOpt::None) {
560 ComputeLiveOutVRegInfo();
563 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
565 // Third, instruction select all of the operations to machine code, adding the
566 // code to the MachineBasicBlock.
567 if (TimePassesIsEnabled) {
568 NamedRegionTimer T("Instruction Selection", GroupName);
569 DoInstructionSelection();
571 DoInstructionSelection();
574 DEBUG(dbgs() << "Selected selection DAG:\n");
575 DEBUG(CurDAG->dump());
577 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
579 // Schedule machine code.
580 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
581 if (TimePassesIsEnabled) {
582 NamedRegionTimer T("Instruction Scheduling", GroupName);
583 Scheduler->Run(CurDAG, BB, BB->end());
585 Scheduler->Run(CurDAG, BB, BB->end());
588 if (ViewSUnitDAGs) Scheduler->viewGraph();
590 // Emit machine code to BB. This can change 'BB' to the last block being
592 if (TimePassesIsEnabled) {
593 NamedRegionTimer T("Instruction Creation", GroupName);
594 BB = Scheduler->EmitSchedule();
596 BB = Scheduler->EmitSchedule();
599 // Free the scheduler state.
600 if (TimePassesIsEnabled) {
601 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
607 // Free the SelectionDAG state, now that we're finished with it.
613 void SelectionDAGISel::DoInstructionSelection() {
614 DEBUG(errs() << "===== Instruction selection begins:\n");
618 // Select target instructions for the DAG.
620 // Number all nodes with a topological order and set DAGSize.
621 DAGSize = CurDAG->AssignTopologicalOrder();
623 // Create a dummy node (which is not added to allnodes), that adds
624 // a reference to the root node, preventing it from being deleted,
625 // and tracking any changes of the root.
626 HandleSDNode Dummy(CurDAG->getRoot());
627 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
630 // The AllNodes list is now topological-sorted. Visit the
631 // nodes by starting at the end of the list (the root of the
632 // graph) and preceding back toward the beginning (the entry
634 while (ISelPosition != CurDAG->allnodes_begin()) {
635 SDNode *Node = --ISelPosition;
636 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
637 // but there are currently some corner cases that it misses. Also, this
638 // makes it theoretically possible to disable the DAGCombiner.
639 if (Node->use_empty())
642 SDNode *ResNode = Select(Node);
644 // FIXME: This is pretty gross. 'Select' should be changed to not return
645 // anything at all and this code should be nuked with a tactical strike.
647 // If node should not be replaced, continue with the next one.
648 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
652 ReplaceUses(Node, ResNode);
654 // If after the replacement this node is not used any more,
655 // remove this dead node.
656 if (Node->use_empty()) { // Don't delete EntryToken, etc.
657 ISelUpdater ISU(ISelPosition);
658 CurDAG->RemoveDeadNode(Node, &ISU);
662 CurDAG->setRoot(Dummy.getValue());
664 DEBUG(errs() << "===== Instruction selection ends:\n");
666 PostprocessISelDAG();
669 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
670 /// do other setup for EH landing-pad blocks.
671 void SelectionDAGISel::PrepareEHLandingPad(MachineBasicBlock *BB) {
672 // Add a label to mark the beginning of the landing pad. Deletion of the
673 // landing pad can thus be detected via the MachineModuleInfo.
674 MCSymbol *Label = MF->getMMI().addLandingPad(BB);
676 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
677 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label);
679 // Mark exception register as live in.
680 unsigned Reg = TLI.getExceptionAddressRegister();
681 if (Reg) BB->addLiveIn(Reg);
683 // Mark exception selector register as live in.
684 Reg = TLI.getExceptionSelectorRegister();
685 if (Reg) BB->addLiveIn(Reg);
687 // FIXME: Hack around an exception handling flaw (PR1508): the personality
688 // function and list of typeids logically belong to the invoke (or, if you
689 // like, the basic block containing the invoke), and need to be associated
690 // with it in the dwarf exception handling tables. Currently however the
691 // information is provided by an intrinsic (eh.selector) that can be moved
692 // to unexpected places by the optimizers: if the unwind edge is critical,
693 // then breaking it can result in the intrinsics being in the successor of
694 // the landing pad, not the landing pad itself. This results
695 // in exceptions not being caught because no typeids are associated with
696 // the invoke. This may not be the only way things can go wrong, but it
697 // is the only way we try to work around for the moment.
698 const BasicBlock *LLVMBB = BB->getBasicBlock();
699 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
701 if (Br && Br->isUnconditional()) { // Critical edge?
702 BasicBlock::const_iterator I, E;
703 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
704 if (isa<EHSelectorInst>(I))
708 // No catch info found - try to extract some from the successor.
709 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
713 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
714 // Initialize the Fast-ISel state, if needed.
715 FastISel *FastIS = 0;
717 FastIS = TLI.createFastISel(*MF, FuncInfo->ValueMap, FuncInfo->MBBMap,
718 FuncInfo->StaticAllocaMap,
719 FuncInfo->PHINodesToUpdate
721 , FuncInfo->CatchInfoLost
725 // Iterate over all basic blocks in the function.
726 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
727 const BasicBlock *LLVMBB = &*I;
728 MachineBasicBlock *BB = FuncInfo->MBBMap[LLVMBB];
730 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
731 BasicBlock::const_iterator const End = LLVMBB->end();
732 BasicBlock::const_iterator BI = Begin;
734 // Lower any arguments needed in this block if this is the entry block.
735 if (LLVMBB == &Fn.getEntryBlock())
736 LowerArguments(LLVMBB);
738 // Setup an EH landing-pad block.
739 if (BB->isLandingPad())
740 PrepareEHLandingPad(BB);
742 // Before doing SelectionDAG ISel, see if FastISel has been requested.
744 // Emit code for any incoming arguments. This must happen before
745 // beginning FastISel on the entry block.
746 if (LLVMBB == &Fn.getEntryBlock()) {
747 CurDAG->setRoot(SDB->getControlRoot());
749 BB = CodeGenAndEmitDAG(BB);
751 FastIS->startNewBlock(BB);
752 // Do FastISel on as many instructions as possible.
753 for (; BI != End; ++BI) {
754 // Try to select the instruction with FastISel.
755 if (FastIS->SelectInstruction(BI))
758 // Then handle certain instructions as single-LLVM-Instruction blocks.
759 if (isa<CallInst>(BI)) {
760 ++NumFastIselFailures;
761 if (EnableFastISelVerbose || EnableFastISelAbort) {
762 dbgs() << "FastISel missed call: ";
766 if (!BI->getType()->isVoidTy() && !BI->use_empty()) {
767 unsigned &R = FuncInfo->ValueMap[BI];
769 R = FuncInfo->CreateRegForValue(BI);
772 bool HadTailCall = false;
773 BB = SelectBasicBlock(BB, LLVMBB, BI, llvm::next(BI), HadTailCall);
775 // If the call was emitted as a tail call, we're done with the block.
781 // If the instruction was codegen'd with multiple blocks,
782 // inform the FastISel object where to resume inserting.
783 FastIS->setCurrentBlock(BB);
787 // Otherwise, give up on FastISel for the rest of the block.
788 // For now, be a little lenient about non-branch terminators.
789 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
790 ++NumFastIselFailures;
791 if (EnableFastISelVerbose || EnableFastISelAbort) {
792 dbgs() << "FastISel miss: ";
795 if (EnableFastISelAbort)
796 // The "fast" selector couldn't handle something and bailed.
797 // For the purpose of debugging, just abort.
798 llvm_unreachable("FastISel didn't select the entire block");
804 // Run SelectionDAG instruction selection on the remainder of the block
805 // not handled by FastISel. If FastISel is not run, this is the entire
809 BB = SelectBasicBlock(BB, LLVMBB, BI, End, HadTailCall);
812 FinishBasicBlock(BB);
813 FuncInfo->PHINodesToUpdate.clear();
820 SelectionDAGISel::FinishBasicBlock(MachineBasicBlock *BB) {
822 DEBUG(dbgs() << "Total amount of phi nodes to update: "
823 << FuncInfo->PHINodesToUpdate.size() << "\n");
824 DEBUG(for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
825 dbgs() << "Node " << i << " : ("
826 << FuncInfo->PHINodesToUpdate[i].first
827 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
829 // Next, now that we know what the last MBB the LLVM BB expanded is, update
830 // PHI nodes in successors.
831 if (SDB->SwitchCases.empty() &&
832 SDB->JTCases.empty() &&
833 SDB->BitTestCases.empty()) {
834 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
835 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
836 assert(PHI->isPHI() &&
837 "This is not a machine PHI node that we are updating!");
838 if (!BB->isSuccessor(PHI->getParent()))
841 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
842 PHI->addOperand(MachineOperand::CreateMBB(BB));
847 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
848 // Lower header first, if it wasn't already lowered
849 if (!SDB->BitTestCases[i].Emitted) {
850 // Set the current basic block to the mbb we wish to insert the code into
851 BB = SDB->BitTestCases[i].Parent;
853 SDB->visitBitTestHeader(SDB->BitTestCases[i], BB);
854 CurDAG->setRoot(SDB->getRoot());
856 BB = CodeGenAndEmitDAG(BB);
859 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
860 // Set the current basic block to the mbb we wish to insert the code into
861 BB = SDB->BitTestCases[i].Cases[j].ThisBB;
864 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
865 SDB->BitTestCases[i].Reg,
866 SDB->BitTestCases[i].Cases[j],
869 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
870 SDB->BitTestCases[i].Reg,
871 SDB->BitTestCases[i].Cases[j],
875 CurDAG->setRoot(SDB->getRoot());
877 BB = CodeGenAndEmitDAG(BB);
881 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
883 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
884 MachineBasicBlock *PHIBB = PHI->getParent();
885 assert(PHI->isPHI() &&
886 "This is not a machine PHI node that we are updating!");
887 // This is "default" BB. We have two jumps to it. From "header" BB and
888 // from last "case" BB.
889 if (PHIBB == SDB->BitTestCases[i].Default) {
890 PHI->addOperand(MachineOperand::
891 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
893 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
894 PHI->addOperand(MachineOperand::
895 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
897 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
900 // One of "cases" BB.
901 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
903 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
904 if (cBB->isSuccessor(PHIBB)) {
905 PHI->addOperand(MachineOperand::
906 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
908 PHI->addOperand(MachineOperand::CreateMBB(cBB));
913 SDB->BitTestCases.clear();
915 // If the JumpTable record is filled in, then we need to emit a jump table.
916 // Updating the PHI nodes is tricky in this case, since we need to determine
917 // whether the PHI is a successor of the range check MBB or the jump table MBB
918 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
919 // Lower header first, if it wasn't already lowered
920 if (!SDB->JTCases[i].first.Emitted) {
921 // Set the current basic block to the mbb we wish to insert the code into
922 BB = SDB->JTCases[i].first.HeaderBB;
924 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
926 CurDAG->setRoot(SDB->getRoot());
928 BB = CodeGenAndEmitDAG(BB);
931 // Set the current basic block to the mbb we wish to insert the code into
932 BB = SDB->JTCases[i].second.MBB;
934 SDB->visitJumpTable(SDB->JTCases[i].second);
935 CurDAG->setRoot(SDB->getRoot());
937 BB = CodeGenAndEmitDAG(BB);
940 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
942 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
943 MachineBasicBlock *PHIBB = PHI->getParent();
944 assert(PHI->isPHI() &&
945 "This is not a machine PHI node that we are updating!");
946 // "default" BB. We can go there only from header BB.
947 if (PHIBB == SDB->JTCases[i].second.Default) {
949 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
952 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
954 // JT BB. Just iterate over successors here
955 if (BB->isSuccessor(PHIBB)) {
957 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
959 PHI->addOperand(MachineOperand::CreateMBB(BB));
963 SDB->JTCases.clear();
965 // If the switch block involved a branch to one of the actual successors, we
966 // need to update PHI nodes in that block.
967 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
968 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
969 assert(PHI->isPHI() &&
970 "This is not a machine PHI node that we are updating!");
971 if (BB->isSuccessor(PHI->getParent())) {
973 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
974 PHI->addOperand(MachineOperand::CreateMBB(BB));
978 // If we generated any switch lowering information, build and codegen any
979 // additional DAGs necessary.
980 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
981 // Set the current basic block to the mbb we wish to insert the code into
982 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB;
984 // Determine the unique successors.
985 SmallVector<MachineBasicBlock *, 2> Succs;
986 Succs.push_back(SDB->SwitchCases[i].TrueBB);
987 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
988 Succs.push_back(SDB->SwitchCases[i].FalseBB);
990 // Emit the code. Note that this could result in ThisBB being split, so
991 // we need to check for updates.
992 SDB->visitSwitchCase(SDB->SwitchCases[i], BB);
993 CurDAG->setRoot(SDB->getRoot());
995 ThisBB = CodeGenAndEmitDAG(BB);
997 // Handle any PHI nodes in successors of this chunk, as if we were coming
998 // from the original BB before switch expansion. Note that PHI nodes can
999 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1000 // handle them the right number of times.
1001 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1003 // BB may have been removed from the CFG if a branch was constant folded.
1004 if (ThisBB->isSuccessor(BB)) {
1005 for (MachineBasicBlock::iterator Phi = BB->begin();
1006 Phi != BB->end() && Phi->isPHI();
1008 // This value for this PHI node is recorded in PHINodesToUpdate.
1009 for (unsigned pn = 0; ; ++pn) {
1010 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1011 "Didn't find PHI entry!");
1012 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) {
1013 Phi->addOperand(MachineOperand::
1014 CreateReg(FuncInfo->PHINodesToUpdate[pn].second,
1016 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1024 SDB->SwitchCases.clear();
1028 /// Create the scheduler. If a specific scheduler was specified
1029 /// via the SchedulerRegistry, use it, otherwise select the
1030 /// one preferred by the target.
1032 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1033 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1037 RegisterScheduler::setDefault(Ctor);
1040 return Ctor(this, OptLevel);
1043 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1044 return new ScheduleHazardRecognizer();
1047 //===----------------------------------------------------------------------===//
1048 // Helper functions used by the generated instruction selector.
1049 //===----------------------------------------------------------------------===//
1050 // Calls to these methods are generated by tblgen.
1052 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1053 /// the dag combiner simplified the 255, we still want to match. RHS is the
1054 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1055 /// specified in the .td file (e.g. 255).
1056 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1057 int64_t DesiredMaskS) const {
1058 const APInt &ActualMask = RHS->getAPIntValue();
1059 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1061 // If the actual mask exactly matches, success!
1062 if (ActualMask == DesiredMask)
1065 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1066 if (ActualMask.intersects(~DesiredMask))
1069 // Otherwise, the DAG Combiner may have proven that the value coming in is
1070 // either already zero or is not demanded. Check for known zero input bits.
1071 APInt NeededMask = DesiredMask & ~ActualMask;
1072 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1075 // TODO: check to see if missing bits are just not demanded.
1077 // Otherwise, this pattern doesn't match.
1081 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1082 /// the dag combiner simplified the 255, we still want to match. RHS is the
1083 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1084 /// specified in the .td file (e.g. 255).
1085 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1086 int64_t DesiredMaskS) const {
1087 const APInt &ActualMask = RHS->getAPIntValue();
1088 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1090 // If the actual mask exactly matches, success!
1091 if (ActualMask == DesiredMask)
1094 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1095 if (ActualMask.intersects(~DesiredMask))
1098 // Otherwise, the DAG Combiner may have proven that the value coming in is
1099 // either already zero or is not demanded. Check for known zero input bits.
1100 APInt NeededMask = DesiredMask & ~ActualMask;
1102 APInt KnownZero, KnownOne;
1103 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1105 // If all the missing bits in the or are already known to be set, match!
1106 if ((NeededMask & KnownOne) == NeededMask)
1109 // TODO: check to see if missing bits are just not demanded.
1111 // Otherwise, this pattern doesn't match.
1116 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1117 /// by tblgen. Others should not call it.
1118 void SelectionDAGISel::
1119 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1120 std::vector<SDValue> InOps;
1121 std::swap(InOps, Ops);
1123 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1124 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1125 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1127 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1128 if (InOps[e-1].getValueType() == MVT::Flag)
1129 --e; // Don't process a flag operand if it is here.
1132 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1133 if (!InlineAsm::isMemKind(Flags)) {
1134 // Just skip over this operand, copying the operands verbatim.
1135 Ops.insert(Ops.end(), InOps.begin()+i,
1136 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1137 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1139 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1140 "Memory operand with multiple values?");
1141 // Otherwise, this is a memory operand. Ask the target to select it.
1142 std::vector<SDValue> SelOps;
1143 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1144 report_fatal_error("Could not match memory address. Inline asm"
1147 // Add this to the output node.
1149 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1150 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1151 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1156 // Add the flag input back if present.
1157 if (e != InOps.size())
1158 Ops.push_back(InOps.back());
1161 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1164 static SDNode *findFlagUse(SDNode *N) {
1165 unsigned FlagResNo = N->getNumValues()-1;
1166 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1167 SDUse &Use = I.getUse();
1168 if (Use.getResNo() == FlagResNo)
1169 return Use.getUser();
1174 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1175 /// This function recursively traverses up the operand chain, ignoring
1177 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1178 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1179 bool IgnoreChains) {
1180 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1181 // greater than all of its (recursive) operands. If we scan to a point where
1182 // 'use' is smaller than the node we're scanning for, then we know we will
1185 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1186 // happen because we scan down to newly selected nodes in the case of flag
1188 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1191 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1192 // won't fail if we scan it again.
1193 if (!Visited.insert(Use))
1196 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1197 // Ignore chain uses, they are validated by HandleMergeInputChains.
1198 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1201 SDNode *N = Use->getOperand(i).getNode();
1203 if (Use == ImmedUse || Use == Root)
1204 continue; // We are not looking for immediate use.
1209 // Traverse up the operand chain.
1210 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1216 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1217 /// operand node N of U during instruction selection that starts at Root.
1218 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1219 SDNode *Root) const {
1220 if (OptLevel == CodeGenOpt::None) return false;
1221 return N.hasOneUse();
1224 /// IsLegalToFold - Returns true if the specific operand node N of
1225 /// U can be folded during instruction selection that starts at Root.
1226 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1227 CodeGenOpt::Level OptLevel,
1228 bool IgnoreChains) {
1229 if (OptLevel == CodeGenOpt::None) return false;
1231 // If Root use can somehow reach N through a path that that doesn't contain
1232 // U then folding N would create a cycle. e.g. In the following
1233 // diagram, Root can reach N through X. If N is folded into into Root, then
1234 // X is both a predecessor and a successor of U.
1245 // * indicates nodes to be folded together.
1247 // If Root produces a flag, then it gets (even more) interesting. Since it
1248 // will be "glued" together with its flag use in the scheduler, we need to
1249 // check if it might reach N.
1268 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1269 // (call it Fold), then X is a predecessor of FU and a successor of
1270 // Fold. But since Fold and FU are flagged together, this will create
1271 // a cycle in the scheduling graph.
1273 // If the node has flags, walk down the graph to the "lowest" node in the
1275 EVT VT = Root->getValueType(Root->getNumValues()-1);
1276 while (VT == MVT::Flag) {
1277 SDNode *FU = findFlagUse(Root);
1281 VT = Root->getValueType(Root->getNumValues()-1);
1283 // If our query node has a flag result with a use, we've walked up it. If
1284 // the user (which has already been selected) has a chain or indirectly uses
1285 // the chain, our WalkChainUsers predicate will not consider it. Because of
1286 // this, we cannot ignore chains in this predicate.
1287 IgnoreChains = false;
1291 SmallPtrSet<SDNode*, 16> Visited;
1292 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1295 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1296 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1297 SelectInlineAsmMemoryOperands(Ops);
1299 std::vector<EVT> VTs;
1300 VTs.push_back(MVT::Other);
1301 VTs.push_back(MVT::Flag);
1302 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1303 VTs, &Ops[0], Ops.size());
1305 return New.getNode();
1308 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1309 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1312 /// GetVBR - decode a vbr encoding whose top bit is set.
1313 ALWAYS_INLINE static uint64_t
1314 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1315 assert(Val >= 128 && "Not a VBR");
1316 Val &= 127; // Remove first vbr bit.
1321 NextBits = MatcherTable[Idx++];
1322 Val |= (NextBits&127) << Shift;
1324 } while (NextBits & 128);
1330 /// UpdateChainsAndFlags - When a match is complete, this method updates uses of
1331 /// interior flag and chain results to use the new flag and chain results.
1332 void SelectionDAGISel::
1333 UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
1334 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1336 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched,
1337 bool isMorphNodeTo) {
1338 SmallVector<SDNode*, 4> NowDeadNodes;
1340 ISelUpdater ISU(ISelPosition);
1342 // Now that all the normal results are replaced, we replace the chain and
1343 // flag results if present.
1344 if (!ChainNodesMatched.empty()) {
1345 assert(InputChain.getNode() != 0 &&
1346 "Matched input chains but didn't produce a chain");
1347 // Loop over all of the nodes we matched that produced a chain result.
1348 // Replace all the chain results with the final chain we ended up with.
1349 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1350 SDNode *ChainNode = ChainNodesMatched[i];
1352 // If this node was already deleted, don't look at it.
1353 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1356 // Don't replace the results of the root node if we're doing a
1358 if (ChainNode == NodeToMatch && isMorphNodeTo)
1361 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1362 if (ChainVal.getValueType() == MVT::Flag)
1363 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1364 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1365 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1367 // If the node became dead and we haven't already seen it, delete it.
1368 if (ChainNode->use_empty() &&
1369 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1370 NowDeadNodes.push_back(ChainNode);
1374 // If the result produces a flag, update any flag results in the matched
1375 // pattern with the flag result.
1376 if (InputFlag.getNode() != 0) {
1377 // Handle any interior nodes explicitly marked.
1378 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) {
1379 SDNode *FRN = FlagResultNodesMatched[i];
1381 // If this node was already deleted, don't look at it.
1382 if (FRN->getOpcode() == ISD::DELETED_NODE)
1385 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag &&
1386 "Doesn't have a flag result");
1387 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1390 // If the node became dead and we haven't already seen it, delete it.
1391 if (FRN->use_empty() &&
1392 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1393 NowDeadNodes.push_back(FRN);
1397 if (!NowDeadNodes.empty())
1398 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1400 DEBUG(errs() << "ISEL: Match complete!\n");
1406 CR_LeadsToInteriorNode
1409 /// WalkChainUsers - Walk down the users of the specified chained node that is
1410 /// part of the pattern we're matching, looking at all of the users we find.
1411 /// This determines whether something is an interior node, whether we have a
1412 /// non-pattern node in between two pattern nodes (which prevent folding because
1413 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1414 /// between pattern nodes (in which case the TF becomes part of the pattern).
1416 /// The walk we do here is guaranteed to be small because we quickly get down to
1417 /// already selected nodes "below" us.
1419 WalkChainUsers(SDNode *ChainedNode,
1420 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1421 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1422 ChainResult Result = CR_Simple;
1424 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1425 E = ChainedNode->use_end(); UI != E; ++UI) {
1426 // Make sure the use is of the chain, not some other value we produce.
1427 if (UI.getUse().getValueType() != MVT::Other) continue;
1431 // If we see an already-selected machine node, then we've gone beyond the
1432 // pattern that we're selecting down into the already selected chunk of the
1434 if (User->isMachineOpcode() ||
1435 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1438 if (User->getOpcode() == ISD::CopyToReg ||
1439 User->getOpcode() == ISD::CopyFromReg ||
1440 User->getOpcode() == ISD::INLINEASM ||
1441 User->getOpcode() == ISD::EH_LABEL) {
1442 // If their node ID got reset to -1 then they've already been selected.
1443 // Treat them like a MachineOpcode.
1444 if (User->getNodeId() == -1)
1448 // If we have a TokenFactor, we handle it specially.
1449 if (User->getOpcode() != ISD::TokenFactor) {
1450 // If the node isn't a token factor and isn't part of our pattern, then it
1451 // must be a random chained node in between two nodes we're selecting.
1452 // This happens when we have something like:
1457 // Because we structurally match the load/store as a read/modify/write,
1458 // but the call is chained between them. We cannot fold in this case
1459 // because it would induce a cycle in the graph.
1460 if (!std::count(ChainedNodesInPattern.begin(),
1461 ChainedNodesInPattern.end(), User))
1462 return CR_InducesCycle;
1464 // Otherwise we found a node that is part of our pattern. For example in:
1468 // This would happen when we're scanning down from the load and see the
1469 // store as a user. Record that there is a use of ChainedNode that is
1470 // part of the pattern and keep scanning uses.
1471 Result = CR_LeadsToInteriorNode;
1472 InteriorChainedNodes.push_back(User);
1476 // If we found a TokenFactor, there are two cases to consider: first if the
1477 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1478 // uses of the TF are in our pattern) we just want to ignore it. Second,
1479 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1485 // | \ DAG's like cheese
1488 // [TokenFactor] [Op]
1495 // In this case, the TokenFactor becomes part of our match and we rewrite it
1496 // as a new TokenFactor.
1498 // To distinguish these two cases, do a recursive walk down the uses.
1499 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1501 // If the uses of the TokenFactor are just already-selected nodes, ignore
1502 // it, it is "below" our pattern.
1504 case CR_InducesCycle:
1505 // If the uses of the TokenFactor lead to nodes that are not part of our
1506 // pattern that are not selected, folding would turn this into a cycle,
1508 return CR_InducesCycle;
1509 case CR_LeadsToInteriorNode:
1510 break; // Otherwise, keep processing.
1513 // Okay, we know we're in the interesting interior case. The TokenFactor
1514 // is now going to be considered part of the pattern so that we rewrite its
1515 // uses (it may have uses that are not part of the pattern) with the
1516 // ultimate chain result of the generated code. We will also add its chain
1517 // inputs as inputs to the ultimate TokenFactor we create.
1518 Result = CR_LeadsToInteriorNode;
1519 ChainedNodesInPattern.push_back(User);
1520 InteriorChainedNodes.push_back(User);
1527 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1528 /// operation for when the pattern matched at least one node with a chains. The
1529 /// input vector contains a list of all of the chained nodes that we match. We
1530 /// must determine if this is a valid thing to cover (i.e. matching it won't
1531 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1532 /// be used as the input node chain for the generated nodes.
1534 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1535 SelectionDAG *CurDAG) {
1536 // Walk all of the chained nodes we've matched, recursively scanning down the
1537 // users of the chain result. This adds any TokenFactor nodes that are caught
1538 // in between chained nodes to the chained and interior nodes list.
1539 SmallVector<SDNode*, 3> InteriorChainedNodes;
1540 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1541 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1542 InteriorChainedNodes) == CR_InducesCycle)
1543 return SDValue(); // Would induce a cycle.
1546 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1547 // that we are interested in. Form our input TokenFactor node.
1548 SmallVector<SDValue, 3> InputChains;
1549 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1550 // Add the input chain of this node to the InputChains list (which will be
1551 // the operands of the generated TokenFactor) if it's not an interior node.
1552 SDNode *N = ChainNodesMatched[i];
1553 if (N->getOpcode() != ISD::TokenFactor) {
1554 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1557 // Otherwise, add the input chain.
1558 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1559 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1560 InputChains.push_back(InChain);
1564 // If we have a token factor, we want to add all inputs of the token factor
1565 // that are not part of the pattern we're matching.
1566 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1567 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1568 N->getOperand(op).getNode()))
1569 InputChains.push_back(N->getOperand(op));
1574 if (InputChains.size() == 1)
1575 return InputChains[0];
1576 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1577 MVT::Other, &InputChains[0], InputChains.size());
1580 /// MorphNode - Handle morphing a node in place for the selector.
1581 SDNode *SelectionDAGISel::
1582 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1583 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1584 // It is possible we're using MorphNodeTo to replace a node with no
1585 // normal results with one that has a normal result (or we could be
1586 // adding a chain) and the input could have flags and chains as well.
1587 // In this case we need to shift the operands down.
1588 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1589 // than the old isel though.
1590 int OldFlagResultNo = -1, OldChainResultNo = -1;
1592 unsigned NTMNumResults = Node->getNumValues();
1593 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) {
1594 OldFlagResultNo = NTMNumResults-1;
1595 if (NTMNumResults != 1 &&
1596 Node->getValueType(NTMNumResults-2) == MVT::Other)
1597 OldChainResultNo = NTMNumResults-2;
1598 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1599 OldChainResultNo = NTMNumResults-1;
1601 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1602 // that this deletes operands of the old node that become dead.
1603 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1605 // MorphNodeTo can operate in two ways: if an existing node with the
1606 // specified operands exists, it can just return it. Otherwise, it
1607 // updates the node in place to have the requested operands.
1609 // If we updated the node in place, reset the node ID. To the isel,
1610 // this should be just like a newly allocated machine node.
1614 unsigned ResNumResults = Res->getNumValues();
1615 // Move the flag if needed.
1616 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 &&
1617 (unsigned)OldFlagResultNo != ResNumResults-1)
1618 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo),
1619 SDValue(Res, ResNumResults-1));
1621 if ((EmitNodeInfo & OPFL_FlagOutput) != 0)
1624 // Move the chain reference if needed.
1625 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1626 (unsigned)OldChainResultNo != ResNumResults-1)
1627 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1628 SDValue(Res, ResNumResults-1));
1630 // Otherwise, no replacement happened because the node already exists. Replace
1631 // Uses of the old node with the new one.
1633 CurDAG->ReplaceAllUsesWith(Node, Res);
1638 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1639 ALWAYS_INLINE static bool
1640 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1641 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) {
1642 // Accept if it is exactly the same as a previously recorded node.
1643 unsigned RecNo = MatcherTable[MatcherIndex++];
1644 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1645 return N == RecordedNodes[RecNo];
1648 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1649 ALWAYS_INLINE static bool
1650 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1651 SelectionDAGISel &SDISel) {
1652 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1655 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1656 ALWAYS_INLINE static bool
1657 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1658 SelectionDAGISel &SDISel, SDNode *N) {
1659 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1662 ALWAYS_INLINE static bool
1663 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1665 uint16_t Opc = MatcherTable[MatcherIndex++];
1666 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1667 return N->getOpcode() == Opc;
1670 ALWAYS_INLINE static bool
1671 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1672 SDValue N, const TargetLowering &TLI) {
1673 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1674 if (N.getValueType() == VT) return true;
1676 // Handle the case when VT is iPTR.
1677 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1680 ALWAYS_INLINE static bool
1681 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1682 SDValue N, const TargetLowering &TLI,
1684 if (ChildNo >= N.getNumOperands())
1685 return false; // Match fails if out of range child #.
1686 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1690 ALWAYS_INLINE static bool
1691 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1693 return cast<CondCodeSDNode>(N)->get() ==
1694 (ISD::CondCode)MatcherTable[MatcherIndex++];
1697 ALWAYS_INLINE static bool
1698 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1699 SDValue N, const TargetLowering &TLI) {
1700 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1701 if (cast<VTSDNode>(N)->getVT() == VT)
1704 // Handle the case when VT is iPTR.
1705 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1708 ALWAYS_INLINE static bool
1709 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1711 int64_t Val = MatcherTable[MatcherIndex++];
1713 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1715 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1716 return C != 0 && C->getSExtValue() == Val;
1719 ALWAYS_INLINE static bool
1720 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1721 SDValue N, SelectionDAGISel &SDISel) {
1722 int64_t Val = MatcherTable[MatcherIndex++];
1724 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1726 if (N->getOpcode() != ISD::AND) return false;
1728 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1729 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1732 ALWAYS_INLINE static bool
1733 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1734 SDValue N, SelectionDAGISel &SDISel) {
1735 int64_t Val = MatcherTable[MatcherIndex++];
1737 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1739 if (N->getOpcode() != ISD::OR) return false;
1741 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1742 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1745 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1746 /// scope, evaluate the current node. If the current predicate is known to
1747 /// fail, set Result=true and return anything. If the current predicate is
1748 /// known to pass, set Result=false and return the MatcherIndex to continue
1749 /// with. If the current predicate is unknown, set Result=false and return the
1750 /// MatcherIndex to continue with.
1751 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1752 unsigned Index, SDValue N,
1753 bool &Result, SelectionDAGISel &SDISel,
1754 SmallVectorImpl<SDValue> &RecordedNodes){
1755 switch (Table[Index++]) {
1758 return Index-1; // Could not evaluate this predicate.
1759 case SelectionDAGISel::OPC_CheckSame:
1760 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1762 case SelectionDAGISel::OPC_CheckPatternPredicate:
1763 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1765 case SelectionDAGISel::OPC_CheckPredicate:
1766 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1768 case SelectionDAGISel::OPC_CheckOpcode:
1769 Result = !::CheckOpcode(Table, Index, N.getNode());
1771 case SelectionDAGISel::OPC_CheckType:
1772 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1774 case SelectionDAGISel::OPC_CheckChild0Type:
1775 case SelectionDAGISel::OPC_CheckChild1Type:
1776 case SelectionDAGISel::OPC_CheckChild2Type:
1777 case SelectionDAGISel::OPC_CheckChild3Type:
1778 case SelectionDAGISel::OPC_CheckChild4Type:
1779 case SelectionDAGISel::OPC_CheckChild5Type:
1780 case SelectionDAGISel::OPC_CheckChild6Type:
1781 case SelectionDAGISel::OPC_CheckChild7Type:
1782 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1783 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1785 case SelectionDAGISel::OPC_CheckCondCode:
1786 Result = !::CheckCondCode(Table, Index, N);
1788 case SelectionDAGISel::OPC_CheckValueType:
1789 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
1791 case SelectionDAGISel::OPC_CheckInteger:
1792 Result = !::CheckInteger(Table, Index, N);
1794 case SelectionDAGISel::OPC_CheckAndImm:
1795 Result = !::CheckAndImm(Table, Index, N, SDISel);
1797 case SelectionDAGISel::OPC_CheckOrImm:
1798 Result = !::CheckOrImm(Table, Index, N, SDISel);
1806 /// FailIndex - If this match fails, this is the index to continue with.
1809 /// NodeStack - The node stack when the scope was formed.
1810 SmallVector<SDValue, 4> NodeStack;
1812 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
1813 unsigned NumRecordedNodes;
1815 /// NumMatchedMemRefs - The number of matched memref entries.
1816 unsigned NumMatchedMemRefs;
1818 /// InputChain/InputFlag - The current chain/flag
1819 SDValue InputChain, InputFlag;
1821 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
1822 bool HasChainNodesMatched, HasFlagResultNodesMatched;
1827 SDNode *SelectionDAGISel::
1828 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
1829 unsigned TableSize) {
1830 // FIXME: Should these even be selected? Handle these cases in the caller?
1831 switch (NodeToMatch->getOpcode()) {
1834 case ISD::EntryToken: // These nodes remain the same.
1835 case ISD::BasicBlock:
1837 //case ISD::VALUETYPE:
1838 //case ISD::CONDCODE:
1839 case ISD::HANDLENODE:
1840 case ISD::MDNODE_SDNODE:
1841 case ISD::TargetConstant:
1842 case ISD::TargetConstantFP:
1843 case ISD::TargetConstantPool:
1844 case ISD::TargetFrameIndex:
1845 case ISD::TargetExternalSymbol:
1846 case ISD::TargetBlockAddress:
1847 case ISD::TargetJumpTable:
1848 case ISD::TargetGlobalTLSAddress:
1849 case ISD::TargetGlobalAddress:
1850 case ISD::TokenFactor:
1851 case ISD::CopyFromReg:
1852 case ISD::CopyToReg:
1854 NodeToMatch->setNodeId(-1); // Mark selected.
1856 case ISD::AssertSext:
1857 case ISD::AssertZext:
1858 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
1859 NodeToMatch->getOperand(0));
1861 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
1862 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
1865 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
1867 // Set up the node stack with NodeToMatch as the only node on the stack.
1868 SmallVector<SDValue, 8> NodeStack;
1869 SDValue N = SDValue(NodeToMatch, 0);
1870 NodeStack.push_back(N);
1872 // MatchScopes - Scopes used when matching, if a match failure happens, this
1873 // indicates where to continue checking.
1874 SmallVector<MatchScope, 8> MatchScopes;
1876 // RecordedNodes - This is the set of nodes that have been recorded by the
1878 SmallVector<SDValue, 8> RecordedNodes;
1880 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
1882 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
1884 // These are the current input chain and flag for use when generating nodes.
1885 // Various Emit operations change these. For example, emitting a copytoreg
1886 // uses and updates these.
1887 SDValue InputChain, InputFlag;
1889 // ChainNodesMatched - If a pattern matches nodes that have input/output
1890 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
1891 // which ones they are. The result is captured into this list so that we can
1892 // update the chain results when the pattern is complete.
1893 SmallVector<SDNode*, 3> ChainNodesMatched;
1894 SmallVector<SDNode*, 3> FlagResultNodesMatched;
1896 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
1897 NodeToMatch->dump(CurDAG);
1900 // Determine where to start the interpreter. Normally we start at opcode #0,
1901 // but if the state machine starts with an OPC_SwitchOpcode, then we
1902 // accelerate the first lookup (which is guaranteed to be hot) with the
1903 // OpcodeOffset table.
1904 unsigned MatcherIndex = 0;
1906 if (!OpcodeOffset.empty()) {
1907 // Already computed the OpcodeOffset table, just index into it.
1908 if (N.getOpcode() < OpcodeOffset.size())
1909 MatcherIndex = OpcodeOffset[N.getOpcode()];
1910 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
1912 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
1913 // Otherwise, the table isn't computed, but the state machine does start
1914 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
1915 // is the first time we're selecting an instruction.
1918 // Get the size of this case.
1919 unsigned CaseSize = MatcherTable[Idx++];
1921 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
1922 if (CaseSize == 0) break;
1924 // Get the opcode, add the index to the table.
1925 uint16_t Opc = MatcherTable[Idx++];
1926 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
1927 if (Opc >= OpcodeOffset.size())
1928 OpcodeOffset.resize((Opc+1)*2);
1929 OpcodeOffset[Opc] = Idx;
1933 // Okay, do the lookup for the first opcode.
1934 if (N.getOpcode() < OpcodeOffset.size())
1935 MatcherIndex = OpcodeOffset[N.getOpcode()];
1939 assert(MatcherIndex < TableSize && "Invalid index");
1941 unsigned CurrentOpcodeIndex = MatcherIndex;
1943 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
1946 // Okay, the semantics of this operation are that we should push a scope
1947 // then evaluate the first child. However, pushing a scope only to have
1948 // the first check fail (which then pops it) is inefficient. If we can
1949 // determine immediately that the first check (or first several) will
1950 // immediately fail, don't even bother pushing a scope for them.
1954 unsigned NumToSkip = MatcherTable[MatcherIndex++];
1955 if (NumToSkip & 128)
1956 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
1957 // Found the end of the scope with no match.
1958 if (NumToSkip == 0) {
1963 FailIndex = MatcherIndex+NumToSkip;
1965 unsigned MatcherIndexOfPredicate = MatcherIndex;
1966 (void)MatcherIndexOfPredicate; // silence warning.
1968 // If we can't evaluate this predicate without pushing a scope (e.g. if
1969 // it is a 'MoveParent') or if the predicate succeeds on this node, we
1970 // push the scope and evaluate the full predicate chain.
1972 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
1973 Result, *this, RecordedNodes);
1977 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
1978 << "index " << MatcherIndexOfPredicate
1979 << ", continuing at " << FailIndex << "\n");
1980 ++NumDAGIselRetries;
1982 // Otherwise, we know that this case of the Scope is guaranteed to fail,
1983 // move to the next case.
1984 MatcherIndex = FailIndex;
1987 // If the whole scope failed to match, bail.
1988 if (FailIndex == 0) break;
1990 // Push a MatchScope which indicates where to go if the first child fails
1992 MatchScope NewEntry;
1993 NewEntry.FailIndex = FailIndex;
1994 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
1995 NewEntry.NumRecordedNodes = RecordedNodes.size();
1996 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
1997 NewEntry.InputChain = InputChain;
1998 NewEntry.InputFlag = InputFlag;
1999 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2000 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty();
2001 MatchScopes.push_back(NewEntry);
2004 case OPC_RecordNode:
2005 // Remember this node, it may end up being an operand in the pattern.
2006 RecordedNodes.push_back(N);
2009 case OPC_RecordChild0: case OPC_RecordChild1:
2010 case OPC_RecordChild2: case OPC_RecordChild3:
2011 case OPC_RecordChild4: case OPC_RecordChild5:
2012 case OPC_RecordChild6: case OPC_RecordChild7: {
2013 unsigned ChildNo = Opcode-OPC_RecordChild0;
2014 if (ChildNo >= N.getNumOperands())
2015 break; // Match fails if out of range child #.
2017 RecordedNodes.push_back(N->getOperand(ChildNo));
2020 case OPC_RecordMemRef:
2021 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2024 case OPC_CaptureFlagInput:
2025 // If the current node has an input flag, capture it in InputFlag.
2026 if (N->getNumOperands() != 0 &&
2027 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag)
2028 InputFlag = N->getOperand(N->getNumOperands()-1);
2031 case OPC_MoveChild: {
2032 unsigned ChildNo = MatcherTable[MatcherIndex++];
2033 if (ChildNo >= N.getNumOperands())
2034 break; // Match fails if out of range child #.
2035 N = N.getOperand(ChildNo);
2036 NodeStack.push_back(N);
2040 case OPC_MoveParent:
2041 // Pop the current node off the NodeStack.
2042 NodeStack.pop_back();
2043 assert(!NodeStack.empty() && "Node stack imbalance!");
2044 N = NodeStack.back();
2048 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2050 case OPC_CheckPatternPredicate:
2051 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2053 case OPC_CheckPredicate:
2054 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2058 case OPC_CheckComplexPat: {
2059 unsigned CPNum = MatcherTable[MatcherIndex++];
2060 unsigned RecNo = MatcherTable[MatcherIndex++];
2061 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2062 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum,
2067 case OPC_CheckOpcode:
2068 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2072 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2075 case OPC_SwitchOpcode: {
2076 unsigned CurNodeOpcode = N.getOpcode();
2077 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2080 // Get the size of this case.
2081 CaseSize = MatcherTable[MatcherIndex++];
2083 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2084 if (CaseSize == 0) break;
2086 uint16_t Opc = MatcherTable[MatcherIndex++];
2087 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2089 // If the opcode matches, then we will execute this case.
2090 if (CurNodeOpcode == Opc)
2093 // Otherwise, skip over this case.
2094 MatcherIndex += CaseSize;
2097 // If no cases matched, bail out.
2098 if (CaseSize == 0) break;
2100 // Otherwise, execute the case we found.
2101 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2102 << " to " << MatcherIndex << "\n");
2106 case OPC_SwitchType: {
2107 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy;
2108 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2111 // Get the size of this case.
2112 CaseSize = MatcherTable[MatcherIndex++];
2114 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2115 if (CaseSize == 0) break;
2117 MVT::SimpleValueType CaseVT =
2118 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2119 if (CaseVT == MVT::iPTR)
2120 CaseVT = TLI.getPointerTy().SimpleTy;
2122 // If the VT matches, then we will execute this case.
2123 if (CurNodeVT == CaseVT)
2126 // Otherwise, skip over this case.
2127 MatcherIndex += CaseSize;
2130 // If no cases matched, bail out.
2131 if (CaseSize == 0) break;
2133 // Otherwise, execute the case we found.
2134 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2135 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2138 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2139 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2140 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2141 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2142 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2143 Opcode-OPC_CheckChild0Type))
2146 case OPC_CheckCondCode:
2147 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2149 case OPC_CheckValueType:
2150 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2152 case OPC_CheckInteger:
2153 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2155 case OPC_CheckAndImm:
2156 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2158 case OPC_CheckOrImm:
2159 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2162 case OPC_CheckFoldableChainNode: {
2163 assert(NodeStack.size() != 1 && "No parent node");
2164 // Verify that all intermediate nodes between the root and this one have
2166 bool HasMultipleUses = false;
2167 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2168 if (!NodeStack[i].hasOneUse()) {
2169 HasMultipleUses = true;
2172 if (HasMultipleUses) break;
2174 // Check to see that the target thinks this is profitable to fold and that
2175 // we can fold it without inducing cycles in the graph.
2176 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2178 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2179 NodeToMatch, OptLevel,
2180 true/*We validate our own chains*/))
2185 case OPC_EmitInteger: {
2186 MVT::SimpleValueType VT =
2187 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2188 int64_t Val = MatcherTable[MatcherIndex++];
2190 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2191 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT));
2194 case OPC_EmitRegister: {
2195 MVT::SimpleValueType VT =
2196 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2197 unsigned RegNo = MatcherTable[MatcherIndex++];
2198 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT));
2202 case OPC_EmitConvertToTarget: {
2203 // Convert from IMM/FPIMM to target version.
2204 unsigned RecNo = MatcherTable[MatcherIndex++];
2205 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2206 SDValue Imm = RecordedNodes[RecNo];
2208 if (Imm->getOpcode() == ISD::Constant) {
2209 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2210 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2211 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2212 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2213 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2216 RecordedNodes.push_back(Imm);
2220 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2221 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2222 // These are space-optimized forms of OPC_EmitMergeInputChains.
2223 assert(InputChain.getNode() == 0 &&
2224 "EmitMergeInputChains should be the first chain producing node");
2225 assert(ChainNodesMatched.empty() &&
2226 "Should only have one EmitMergeInputChains per match");
2228 // Read all of the chained nodes.
2229 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2230 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2231 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2233 // FIXME: What if other value results of the node have uses not matched
2235 if (ChainNodesMatched.back() != NodeToMatch &&
2236 !RecordedNodes[RecNo].hasOneUse()) {
2237 ChainNodesMatched.clear();
2241 // Merge the input chains if they are not intra-pattern references.
2242 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2244 if (InputChain.getNode() == 0)
2245 break; // Failed to merge.
2249 case OPC_EmitMergeInputChains: {
2250 assert(InputChain.getNode() == 0 &&
2251 "EmitMergeInputChains should be the first chain producing node");
2252 // This node gets a list of nodes we matched in the input that have
2253 // chains. We want to token factor all of the input chains to these nodes
2254 // together. However, if any of the input chains is actually one of the
2255 // nodes matched in this pattern, then we have an intra-match reference.
2256 // Ignore these because the newly token factored chain should not refer to
2258 unsigned NumChains = MatcherTable[MatcherIndex++];
2259 assert(NumChains != 0 && "Can't TF zero chains");
2261 assert(ChainNodesMatched.empty() &&
2262 "Should only have one EmitMergeInputChains per match");
2264 // Read all of the chained nodes.
2265 for (unsigned i = 0; i != NumChains; ++i) {
2266 unsigned RecNo = MatcherTable[MatcherIndex++];
2267 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2268 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2270 // FIXME: What if other value results of the node have uses not matched
2272 if (ChainNodesMatched.back() != NodeToMatch &&
2273 !RecordedNodes[RecNo].hasOneUse()) {
2274 ChainNodesMatched.clear();
2279 // If the inner loop broke out, the match fails.
2280 if (ChainNodesMatched.empty())
2283 // Merge the input chains if they are not intra-pattern references.
2284 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2286 if (InputChain.getNode() == 0)
2287 break; // Failed to merge.
2292 case OPC_EmitCopyToReg: {
2293 unsigned RecNo = MatcherTable[MatcherIndex++];
2294 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2295 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2297 if (InputChain.getNode() == 0)
2298 InputChain = CurDAG->getEntryNode();
2300 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2301 DestPhysReg, RecordedNodes[RecNo],
2304 InputFlag = InputChain.getValue(1);
2308 case OPC_EmitNodeXForm: {
2309 unsigned XFormNo = MatcherTable[MatcherIndex++];
2310 unsigned RecNo = MatcherTable[MatcherIndex++];
2311 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2312 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo));
2317 case OPC_MorphNodeTo: {
2318 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2319 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2320 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2321 // Get the result VT list.
2322 unsigned NumVTs = MatcherTable[MatcherIndex++];
2323 SmallVector<EVT, 4> VTs;
2324 for (unsigned i = 0; i != NumVTs; ++i) {
2325 MVT::SimpleValueType VT =
2326 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2327 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2331 if (EmitNodeInfo & OPFL_Chain)
2332 VTs.push_back(MVT::Other);
2333 if (EmitNodeInfo & OPFL_FlagOutput)
2334 VTs.push_back(MVT::Flag);
2336 // This is hot code, so optimize the two most common cases of 1 and 2
2339 if (VTs.size() == 1)
2340 VTList = CurDAG->getVTList(VTs[0]);
2341 else if (VTs.size() == 2)
2342 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2344 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2346 // Get the operand list.
2347 unsigned NumOps = MatcherTable[MatcherIndex++];
2348 SmallVector<SDValue, 8> Ops;
2349 for (unsigned i = 0; i != NumOps; ++i) {
2350 unsigned RecNo = MatcherTable[MatcherIndex++];
2352 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2354 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2355 Ops.push_back(RecordedNodes[RecNo]);
2358 // If there are variadic operands to add, handle them now.
2359 if (EmitNodeInfo & OPFL_VariadicInfo) {
2360 // Determine the start index to copy from.
2361 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2362 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2363 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2364 "Invalid variadic node");
2365 // Copy all of the variadic operands, not including a potential flag
2367 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2369 SDValue V = NodeToMatch->getOperand(i);
2370 if (V.getValueType() == MVT::Flag) break;
2375 // If this has chain/flag inputs, add them.
2376 if (EmitNodeInfo & OPFL_Chain)
2377 Ops.push_back(InputChain);
2378 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0)
2379 Ops.push_back(InputFlag);
2383 if (Opcode != OPC_MorphNodeTo) {
2384 // If this is a normal EmitNode command, just create the new node and
2385 // add the results to the RecordedNodes list.
2386 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2387 VTList, Ops.data(), Ops.size());
2389 // Add all the non-flag/non-chain results to the RecordedNodes list.
2390 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2391 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
2392 RecordedNodes.push_back(SDValue(Res, i));
2396 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2400 // If the node had chain/flag results, update our notion of the current
2402 if (EmitNodeInfo & OPFL_FlagOutput) {
2403 InputFlag = SDValue(Res, VTs.size()-1);
2404 if (EmitNodeInfo & OPFL_Chain)
2405 InputChain = SDValue(Res, VTs.size()-2);
2406 } else if (EmitNodeInfo & OPFL_Chain)
2407 InputChain = SDValue(Res, VTs.size()-1);
2409 // If the OPFL_MemRefs flag is set on this node, slap all of the
2410 // accumulated memrefs onto it.
2412 // FIXME: This is vastly incorrect for patterns with multiple outputs
2413 // instructions that access memory and for ComplexPatterns that match
2415 if (EmitNodeInfo & OPFL_MemRefs) {
2416 MachineSDNode::mmo_iterator MemRefs =
2417 MF->allocateMemRefsArray(MatchedMemRefs.size());
2418 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2419 cast<MachineSDNode>(Res)
2420 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2424 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2425 << " node: "; Res->dump(CurDAG); errs() << "\n");
2427 // If this was a MorphNodeTo then we're completely done!
2428 if (Opcode == OPC_MorphNodeTo) {
2429 // Update chain and flag uses.
2430 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2431 InputFlag, FlagResultNodesMatched, true);
2438 case OPC_MarkFlagResults: {
2439 unsigned NumNodes = MatcherTable[MatcherIndex++];
2441 // Read and remember all the flag-result nodes.
2442 for (unsigned i = 0; i != NumNodes; ++i) {
2443 unsigned RecNo = MatcherTable[MatcherIndex++];
2445 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2447 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2448 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2453 case OPC_CompleteMatch: {
2454 // The match has been completed, and any new nodes (if any) have been
2455 // created. Patch up references to the matched dag to use the newly
2457 unsigned NumResults = MatcherTable[MatcherIndex++];
2459 for (unsigned i = 0; i != NumResults; ++i) {
2460 unsigned ResSlot = MatcherTable[MatcherIndex++];
2462 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2464 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2465 SDValue Res = RecordedNodes[ResSlot];
2467 assert(i < NodeToMatch->getNumValues() &&
2468 NodeToMatch->getValueType(i) != MVT::Other &&
2469 NodeToMatch->getValueType(i) != MVT::Flag &&
2470 "Invalid number of results to complete!");
2471 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2472 NodeToMatch->getValueType(i) == MVT::iPTR ||
2473 Res.getValueType() == MVT::iPTR ||
2474 NodeToMatch->getValueType(i).getSizeInBits() ==
2475 Res.getValueType().getSizeInBits()) &&
2476 "invalid replacement");
2477 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2480 // If the root node defines a flag, add it to the flag nodes to update
2482 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag)
2483 FlagResultNodesMatched.push_back(NodeToMatch);
2485 // Update chain and flag uses.
2486 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2487 InputFlag, FlagResultNodesMatched, false);
2489 assert(NodeToMatch->use_empty() &&
2490 "Didn't replace all uses of the node?");
2492 // FIXME: We just return here, which interacts correctly with SelectRoot
2493 // above. We should fix this to not return an SDNode* anymore.
2498 // If the code reached this point, then the match failed. See if there is
2499 // another child to try in the current 'Scope', otherwise pop it until we
2500 // find a case to check.
2501 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2502 ++NumDAGIselRetries;
2504 if (MatchScopes.empty()) {
2505 CannotYetSelect(NodeToMatch);
2509 // Restore the interpreter state back to the point where the scope was
2511 MatchScope &LastScope = MatchScopes.back();
2512 RecordedNodes.resize(LastScope.NumRecordedNodes);
2514 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2515 N = NodeStack.back();
2517 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2518 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2519 MatcherIndex = LastScope.FailIndex;
2521 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2523 InputChain = LastScope.InputChain;
2524 InputFlag = LastScope.InputFlag;
2525 if (!LastScope.HasChainNodesMatched)
2526 ChainNodesMatched.clear();
2527 if (!LastScope.HasFlagResultNodesMatched)
2528 FlagResultNodesMatched.clear();
2530 // Check to see what the offset is at the new MatcherIndex. If it is zero
2531 // we have reached the end of this scope, otherwise we have another child
2532 // in the current scope to try.
2533 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2534 if (NumToSkip & 128)
2535 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2537 // If we have another child in this scope to match, update FailIndex and
2539 if (NumToSkip != 0) {
2540 LastScope.FailIndex = MatcherIndex+NumToSkip;
2544 // End of this scope, pop it and try the next child in the containing
2546 MatchScopes.pop_back();
2553 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2555 raw_string_ostream Msg(msg);
2556 Msg << "Cannot yet select: ";
2558 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2559 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2560 N->getOpcode() != ISD::INTRINSIC_VOID) {
2561 N->printrFull(Msg, CurDAG);
2563 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2565 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2566 if (iid < Intrinsic::num_intrinsics)
2567 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2568 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2569 Msg << "target intrinsic %" << TII->getName(iid);
2571 Msg << "unknown intrinsic #" << iid;
2573 report_fatal_error(Msg.str());
2576 char SelectionDAGISel::ID = 0;