1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/LLVMContext.h"
28 #include "llvm/CodeGen/FastISel.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/GCMetadata.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
36 #include "llvm/CodeGen/SchedulerRegistry.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetIntrinsicInfo.h"
40 #include "llvm/Target/TargetInstrInfo.h"
41 #include "llvm/Target/TargetLowering.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetOptions.h"
44 #include "llvm/Support/Compiler.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/Timer.h"
48 #include "llvm/Support/raw_ostream.h"
49 #include "llvm/ADT/Statistic.h"
53 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
54 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
57 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
58 cl::desc("Enable verbose messages in the \"fast\" "
59 "instruction selector"));
61 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
62 cl::desc("Enable abort calls when \"fast\" instruction fails"));
66 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
67 cl::desc("Pop up a window to show dags before the first "
70 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
71 cl::desc("Pop up a window to show dags before legalize types"));
73 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
74 cl::desc("Pop up a window to show dags before legalize"));
76 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
77 cl::desc("Pop up a window to show dags before the second "
80 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
81 cl::desc("Pop up a window to show dags before the post legalize types"
82 " dag combine pass"));
84 ViewISelDAGs("view-isel-dags", cl::Hidden,
85 cl::desc("Pop up a window to show isel dags as they are selected"));
87 ViewSchedDAGs("view-sched-dags", cl::Hidden,
88 cl::desc("Pop up a window to show sched dags as they are processed"));
90 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
91 cl::desc("Pop up a window to show SUnit dags after they are processed"));
93 static const bool ViewDAGCombine1 = false,
94 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
95 ViewDAGCombine2 = false,
96 ViewDAGCombineLT = false,
97 ViewISelDAGs = false, ViewSchedDAGs = false,
98 ViewSUnitDAGs = false;
101 //===---------------------------------------------------------------------===//
103 /// RegisterScheduler class - Track the registration of instruction schedulers.
105 //===---------------------------------------------------------------------===//
106 MachinePassRegistry RegisterScheduler::Registry;
108 //===---------------------------------------------------------------------===//
110 /// ISHeuristic command line option for instruction schedulers.
112 //===---------------------------------------------------------------------===//
113 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
114 RegisterPassParser<RegisterScheduler> >
115 ISHeuristic("pre-RA-sched",
116 cl::init(&createDefaultScheduler),
117 cl::desc("Instruction schedulers available (before register"
120 static RegisterScheduler
121 defaultListDAGScheduler("default", "Best scheduler for the target",
122 createDefaultScheduler);
125 //===--------------------------------------------------------------------===//
126 /// createDefaultScheduler - This creates an instruction scheduler appropriate
128 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
129 CodeGenOpt::Level OptLevel) {
130 const TargetLowering &TLI = IS->getTargetLowering();
132 if (OptLevel == CodeGenOpt::None)
133 return createFastDAGScheduler(IS, OptLevel);
134 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
135 return createTDListDAGScheduler(IS, OptLevel);
136 assert(TLI.getSchedulingPreference() ==
137 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
138 return createBURRListDAGScheduler(IS, OptLevel);
142 // EmitInstrWithCustomInserter - This method should be implemented by targets
143 // that mark instructions with the 'usesCustomInserter' flag. These
144 // instructions are special in various ways, which require special support to
145 // insert. The specified MachineInstr is created but not inserted into any
146 // basic blocks, and this method is called to expand it into a sequence of
147 // instructions, potentially also creating new basic blocks and control flow.
148 // When new basic blocks are inserted and the edges from MBB to its successors
149 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
151 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
152 MachineBasicBlock *MBB,
153 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
155 dbgs() << "If a target marks an instruction with "
156 "'usesCustomInserter', it must implement "
157 "TargetLowering::EmitInstrWithCustomInserter!";
163 //===----------------------------------------------------------------------===//
164 // SelectionDAGISel code
165 //===----------------------------------------------------------------------===//
167 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) :
168 MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
169 FuncInfo(new FunctionLoweringInfo(TLI)),
170 CurDAG(new SelectionDAG(TLI, *FuncInfo)),
171 SDB(new SelectionDAGBuilder(*CurDAG, TLI, *FuncInfo, OL)),
177 SelectionDAGISel::~SelectionDAGISel() {
183 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
184 AU.addRequired<AliasAnalysis>();
185 AU.addPreserved<AliasAnalysis>();
186 AU.addRequired<GCModuleInfo>();
187 AU.addPreserved<GCModuleInfo>();
188 MachineFunctionPass::getAnalysisUsage(AU);
191 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
192 // Do some sanity-checking on the command-line options.
193 assert((!EnableFastISelVerbose || EnableFastISel) &&
194 "-fast-isel-verbose requires -fast-isel");
195 assert((!EnableFastISelAbort || EnableFastISel) &&
196 "-fast-isel-abort requires -fast-isel");
198 Function &Fn = *mf.getFunction();
199 const TargetInstrInfo &TII = *TM.getInstrInfo();
200 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
203 RegInfo = &MF->getRegInfo();
204 AA = &getAnalysis<AliasAnalysis>();
205 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
207 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
210 FuncInfo->set(Fn, *MF, EnableFastISel);
213 SelectAllBasicBlocks(Fn, *MF, TII);
215 // Release function-specific state. SDB and CurDAG are already cleared
219 // If the first basic block in the function has live ins that need to be
220 // copied into vregs, emit the copies into the top of the block before
221 // emitting the code for the block.
222 RegInfo->EmitLiveInCopies(MF->begin(), TRI, TII);
227 /// SetDebugLoc - Update MF's and SDB's DebugLocs if debug information is
228 /// attached with this instruction.
229 static void SetDebugLoc(Instruction *I, SelectionDAGBuilder *SDB,
230 FastISel *FastIS, MachineFunction *MF) {
231 DebugLoc DL = I->getDebugLoc();
232 if (DL.isUnknown()) return;
234 SDB->setCurDebugLoc(DL);
237 FastIS->setCurDebugLoc(DL);
239 // If the function doesn't have a default debug location yet, set
240 // it. This is kind of a hack.
241 if (MF->getDefaultDebugLoc().isUnknown())
242 MF->setDefaultDebugLoc(DL);
245 /// ResetDebugLoc - Set MF's and SDB's DebugLocs to Unknown.
246 static void ResetDebugLoc(SelectionDAGBuilder *SDB, FastISel *FastIS) {
247 SDB->setCurDebugLoc(DebugLoc());
249 FastIS->setCurDebugLoc(DebugLoc());
252 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
253 BasicBlock::iterator Begin,
254 BasicBlock::iterator End,
256 SDB->setCurrentBasicBlock(BB);
258 // Lower all of the non-terminator instructions. If a call is emitted
259 // as a tail call, cease emitting nodes for this block.
260 for (BasicBlock::iterator I = Begin; I != End && !SDB->HasTailCall; ++I) {
261 SetDebugLoc(I, SDB, 0, MF);
263 if (!isa<TerminatorInst>(I)) {
266 // Set the current debug location back to "unknown" so that it doesn't
267 // spuriously apply to subsequent instructions.
268 ResetDebugLoc(SDB, 0);
272 if (!SDB->HasTailCall) {
273 // Ensure that all instructions which are used outside of their defining
274 // blocks are available as virtual registers. Invoke is handled elsewhere.
275 for (BasicBlock::iterator I = Begin; I != End; ++I)
276 if (!isa<PHINode>(I) && !isa<InvokeInst>(I))
277 SDB->CopyToExportRegsIfNeeded(I);
279 // Handle PHI nodes in successor blocks.
280 if (End == LLVMBB->end()) {
281 HandlePHINodesInSuccessorBlocks(LLVMBB);
283 // Lower the terminator after the copies are emitted.
284 SetDebugLoc(LLVMBB->getTerminator(), SDB, 0, MF);
285 SDB->visit(*LLVMBB->getTerminator());
286 ResetDebugLoc(SDB, 0);
290 // Make sure the root of the DAG is up-to-date.
291 CurDAG->setRoot(SDB->getControlRoot());
293 // Final step, emit the lowered DAG as machine code.
295 HadTailCall = SDB->HasTailCall;
300 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
301 /// nodes from the worklist.
302 class SDOPsWorkListRemover : public SelectionDAG::DAGUpdateListener {
303 SmallVector<SDNode*, 128> &Worklist;
304 SmallPtrSet<SDNode*, 128> &InWorklist;
306 SDOPsWorkListRemover(SmallVector<SDNode*, 128> &wl,
307 SmallPtrSet<SDNode*, 128> &inwl)
308 : Worklist(wl), InWorklist(inwl) {}
310 void RemoveFromWorklist(SDNode *N) {
311 if (!InWorklist.erase(N)) return;
313 SmallVector<SDNode*, 128>::iterator I =
314 std::find(Worklist.begin(), Worklist.end(), N);
315 assert(I != Worklist.end() && "Not in worklist");
317 *I = Worklist.back();
321 virtual void NodeDeleted(SDNode *N, SDNode *E) {
322 RemoveFromWorklist(N);
325 virtual void NodeUpdated(SDNode *N) {
331 /// TrivialTruncElim - Eliminate some trivial nops that can result from
332 /// ShrinkDemandedOps: (trunc (ext n)) -> n.
333 static bool TrivialTruncElim(SDValue Op,
334 TargetLowering::TargetLoweringOpt &TLO) {
335 SDValue N0 = Op.getOperand(0);
336 EVT VT = Op.getValueType();
337 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
338 N0.getOpcode() == ISD::SIGN_EXTEND ||
339 N0.getOpcode() == ISD::ANY_EXTEND) &&
340 N0.getOperand(0).getValueType() == VT) {
341 return TLO.CombineTo(Op, N0.getOperand(0));
346 /// ShrinkDemandedOps - A late transformation pass that shrink expressions
347 /// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts
348 /// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
349 void SelectionDAGISel::ShrinkDemandedOps() {
350 SmallVector<SDNode*, 128> Worklist;
351 SmallPtrSet<SDNode*, 128> InWorklist;
353 // Add all the dag nodes to the worklist.
354 Worklist.reserve(CurDAG->allnodes_size());
355 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
356 E = CurDAG->allnodes_end(); I != E; ++I) {
357 Worklist.push_back(I);
358 InWorklist.insert(I);
361 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true);
362 while (!Worklist.empty()) {
363 SDNode *N = Worklist.pop_back_val();
366 if (N->use_empty() && N != CurDAG->getRoot().getNode()) {
367 // Deleting this node may make its operands dead, add them to the worklist
368 // if they aren't already there.
369 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
370 if (InWorklist.insert(N->getOperand(i).getNode()))
371 Worklist.push_back(N->getOperand(i).getNode());
373 CurDAG->DeleteNode(N);
377 // Run ShrinkDemandedOp on scalar binary operations.
378 if (N->getNumValues() != 1 ||
379 !N->getValueType(0).isSimple() || !N->getValueType(0).isInteger())
382 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
383 APInt Demanded = APInt::getAllOnesValue(BitWidth);
384 APInt KnownZero, KnownOne;
385 if (!TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded,
386 KnownZero, KnownOne, TLO) &&
387 (N->getOpcode() != ISD::TRUNCATE ||
388 !TrivialTruncElim(SDValue(N, 0), TLO)))
392 assert(!InWorklist.count(N) && "Already in worklist");
393 Worklist.push_back(N);
394 InWorklist.insert(N);
396 // Replace the old value with the new one.
397 DEBUG(errs() << "\nShrinkDemandedOps replacing ";
398 TLO.Old.getNode()->dump(CurDAG);
399 errs() << "\nWith: ";
400 TLO.New.getNode()->dump(CurDAG);
403 if (InWorklist.insert(TLO.New.getNode()))
404 Worklist.push_back(TLO.New.getNode());
406 SDOPsWorkListRemover DeadNodes(Worklist, InWorklist);
407 CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
409 if (!TLO.Old.getNode()->use_empty()) continue;
411 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands();
413 SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode();
414 if (OpNode->hasOneUse()) {
415 // Add OpNode to the end of the list to revisit.
416 DeadNodes.RemoveFromWorklist(OpNode);
417 Worklist.push_back(OpNode);
418 InWorklist.insert(OpNode);
422 DeadNodes.RemoveFromWorklist(TLO.Old.getNode());
423 CurDAG->DeleteNode(TLO.Old.getNode());
427 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
428 SmallPtrSet<SDNode*, 128> VisitedNodes;
429 SmallVector<SDNode*, 128> Worklist;
431 Worklist.push_back(CurDAG->getRoot().getNode());
438 SDNode *N = Worklist.pop_back_val();
440 // If we've already seen this node, ignore it.
441 if (!VisitedNodes.insert(N))
444 // Otherwise, add all chain operands to the worklist.
445 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
446 if (N->getOperand(i).getValueType() == MVT::Other)
447 Worklist.push_back(N->getOperand(i).getNode());
449 // If this is a CopyToReg with a vreg dest, process it.
450 if (N->getOpcode() != ISD::CopyToReg)
453 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
454 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
457 // Ignore non-scalar or non-integer values.
458 SDValue Src = N->getOperand(2);
459 EVT SrcVT = Src.getValueType();
460 if (!SrcVT.isInteger() || SrcVT.isVector())
463 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
464 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
465 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
467 // Only install this information if it tells us something.
468 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
469 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
470 if (DestReg >= FuncInfo->LiveOutRegInfo.size())
471 FuncInfo->LiveOutRegInfo.resize(DestReg+1);
472 FunctionLoweringInfo::LiveOutInfo &LOI =
473 FuncInfo->LiveOutRegInfo[DestReg];
474 LOI.NumSignBits = NumSignBits;
475 LOI.KnownOne = KnownOne;
476 LOI.KnownZero = KnownZero;
478 } while (!Worklist.empty());
481 void SelectionDAGISel::CodeGenAndEmitDAG() {
482 std::string GroupName;
483 if (TimePassesIsEnabled)
484 GroupName = "Instruction Selection and Scheduling";
485 std::string BlockName;
486 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
487 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
489 BlockName = MF->getFunction()->getNameStr() + ":" +
490 BB->getBasicBlock()->getNameStr();
492 DEBUG(dbgs() << "Initial selection DAG:\n");
493 DEBUG(CurDAG->dump());
495 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
497 // Run the DAG combiner in pre-legalize mode.
498 if (TimePassesIsEnabled) {
499 NamedRegionTimer T("DAG Combining 1", GroupName);
500 CurDAG->Combine(Unrestricted, *AA, OptLevel);
502 CurDAG->Combine(Unrestricted, *AA, OptLevel);
505 DEBUG(dbgs() << "Optimized lowered selection DAG:\n");
506 DEBUG(CurDAG->dump());
508 // Second step, hack on the DAG until it only uses operations and types that
509 // the target supports.
510 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
514 if (TimePassesIsEnabled) {
515 NamedRegionTimer T("Type Legalization", GroupName);
516 Changed = CurDAG->LegalizeTypes();
518 Changed = CurDAG->LegalizeTypes();
521 DEBUG(dbgs() << "Type-legalized selection DAG:\n");
522 DEBUG(CurDAG->dump());
525 if (ViewDAGCombineLT)
526 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
528 // Run the DAG combiner in post-type-legalize mode.
529 if (TimePassesIsEnabled) {
530 NamedRegionTimer T("DAG Combining after legalize types", GroupName);
531 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
533 CurDAG->Combine(NoIllegalTypes, *AA, OptLevel);
536 DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n");
537 DEBUG(CurDAG->dump());
540 if (TimePassesIsEnabled) {
541 NamedRegionTimer T("Vector Legalization", GroupName);
542 Changed = CurDAG->LegalizeVectors();
544 Changed = CurDAG->LegalizeVectors();
548 if (TimePassesIsEnabled) {
549 NamedRegionTimer T("Type Legalization 2", GroupName);
550 CurDAG->LegalizeTypes();
552 CurDAG->LegalizeTypes();
555 if (ViewDAGCombineLT)
556 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
558 // Run the DAG combiner in post-type-legalize mode.
559 if (TimePassesIsEnabled) {
560 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName);
561 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
563 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
566 DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n");
567 DEBUG(CurDAG->dump());
570 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
572 if (TimePassesIsEnabled) {
573 NamedRegionTimer T("DAG Legalization", GroupName);
574 CurDAG->Legalize(OptLevel);
576 CurDAG->Legalize(OptLevel);
579 DEBUG(dbgs() << "Legalized selection DAG:\n");
580 DEBUG(CurDAG->dump());
582 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
584 // Run the DAG combiner in post-legalize mode.
585 if (TimePassesIsEnabled) {
586 NamedRegionTimer T("DAG Combining 2", GroupName);
587 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
589 CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
592 DEBUG(dbgs() << "Optimized legalized selection DAG:\n");
593 DEBUG(CurDAG->dump());
595 if (OptLevel != CodeGenOpt::None) {
597 ComputeLiveOutVRegInfo();
600 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
602 // Third, instruction select all of the operations to machine code, adding the
603 // code to the MachineBasicBlock.
604 if (TimePassesIsEnabled) {
605 NamedRegionTimer T("Instruction Selection", GroupName);
606 DoInstructionSelection();
608 DoInstructionSelection();
611 DEBUG(dbgs() << "Selected selection DAG:\n");
612 DEBUG(CurDAG->dump());
614 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
616 // Schedule machine code.
617 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
618 if (TimePassesIsEnabled) {
619 NamedRegionTimer T("Instruction Scheduling", GroupName);
620 Scheduler->Run(CurDAG, BB, BB->end());
622 Scheduler->Run(CurDAG, BB, BB->end());
625 if (ViewSUnitDAGs) Scheduler->viewGraph();
627 // Emit machine code to BB. This can change 'BB' to the last block being
629 if (TimePassesIsEnabled) {
630 NamedRegionTimer T("Instruction Creation", GroupName);
631 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
633 BB = Scheduler->EmitSchedule(&SDB->EdgeMapping);
636 // Free the scheduler state.
637 if (TimePassesIsEnabled) {
638 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
644 DEBUG(dbgs() << "Selected machine code:\n");
648 void SelectionDAGISel::DoInstructionSelection() {
649 DEBUG(errs() << "===== Instruction selection begins:\n");
653 // Select target instructions for the DAG.
655 // Number all nodes with a topological order and set DAGSize.
656 DAGSize = CurDAG->AssignTopologicalOrder();
658 // Create a dummy node (which is not added to allnodes), that adds
659 // a reference to the root node, preventing it from being deleted,
660 // and tracking any changes of the root.
661 HandleSDNode Dummy(CurDAG->getRoot());
662 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
665 // The AllNodes list is now topological-sorted. Visit the
666 // nodes by starting at the end of the list (the root of the
667 // graph) and preceding back toward the beginning (the entry
669 while (ISelPosition != CurDAG->allnodes_begin()) {
670 SDNode *Node = --ISelPosition;
671 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
672 // but there are currently some corner cases that it misses. Also, this
673 // makes it theoretically possible to disable the DAGCombiner.
674 if (Node->use_empty())
677 SDNode *ResNode = Select(Node);
679 // FIXME: This is pretty gross. 'Select' should be changed to not return
680 // anything at all and this code should be nuked with a tactical strike.
682 // If node should not be replaced, continue with the next one.
683 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
687 ReplaceUses(Node, ResNode);
689 // If after the replacement this node is not used any more,
690 // remove this dead node.
691 if (Node->use_empty()) { // Don't delete EntryToken, etc.
692 ISelUpdater ISU(ISelPosition);
693 CurDAG->RemoveDeadNode(Node, &ISU);
697 CurDAG->setRoot(Dummy.getValue());
699 DEBUG(errs() << "===== Instruction selection ends:\n");
701 PostprocessISelDAG();
705 void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
707 const TargetInstrInfo &TII) {
708 // Initialize the Fast-ISel state, if needed.
709 FastISel *FastIS = 0;
711 FastIS = TLI.createFastISel(MF, FuncInfo->ValueMap, FuncInfo->MBBMap,
712 FuncInfo->StaticAllocaMap
714 , FuncInfo->CatchInfoLost
718 // Iterate over all basic blocks in the function.
719 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
720 BasicBlock *LLVMBB = &*I;
721 BB = FuncInfo->MBBMap[LLVMBB];
723 BasicBlock::iterator const Begin = LLVMBB->begin();
724 BasicBlock::iterator const End = LLVMBB->end();
725 BasicBlock::iterator BI = Begin;
727 // Lower any arguments needed in this block if this is the entry block.
728 bool SuppressFastISel = false;
729 if (LLVMBB == &Fn.getEntryBlock()) {
730 LowerArguments(LLVMBB);
732 // If any of the arguments has the byval attribute, forgo
733 // fast-isel in the entry block.
736 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end();
738 if (Fn.paramHasAttr(j, Attribute::ByVal)) {
739 if (EnableFastISelVerbose || EnableFastISelAbort)
740 dbgs() << "FastISel skips entry block due to byval argument\n";
741 SuppressFastISel = true;
747 if (BB->isLandingPad()) {
748 // Add a label to mark the beginning of the landing pad. Deletion of the
749 // landing pad can thus be detected via the MachineModuleInfo.
750 MCSymbol *Label = MF.getMMI().addLandingPad(BB);
752 const TargetInstrDesc &II = TII.get(TargetOpcode::EH_LABEL);
753 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label);
755 // Mark exception register as live in.
756 unsigned Reg = TLI.getExceptionAddressRegister();
757 if (Reg) BB->addLiveIn(Reg);
759 // Mark exception selector register as live in.
760 Reg = TLI.getExceptionSelectorRegister();
761 if (Reg) BB->addLiveIn(Reg);
763 // FIXME: Hack around an exception handling flaw (PR1508): the personality
764 // function and list of typeids logically belong to the invoke (or, if you
765 // like, the basic block containing the invoke), and need to be associated
766 // with it in the dwarf exception handling tables. Currently however the
767 // information is provided by an intrinsic (eh.selector) that can be moved
768 // to unexpected places by the optimizers: if the unwind edge is critical,
769 // then breaking it can result in the intrinsics being in the successor of
770 // the landing pad, not the landing pad itself. This results
771 // in exceptions not being caught because no typeids are associated with
772 // the invoke. This may not be the only way things can go wrong, but it
773 // is the only way we try to work around for the moment.
774 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
776 if (Br && Br->isUnconditional()) { // Critical edge?
777 BasicBlock::iterator I, E;
778 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
779 if (isa<EHSelectorInst>(I))
783 // No catch info found - try to extract some from the successor.
784 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF.getMMI(), *FuncInfo);
788 // Before doing SelectionDAG ISel, see if FastISel has been requested.
789 if (FastIS && !SuppressFastISel) {
790 // Emit code for any incoming arguments. This must happen before
791 // beginning FastISel on the entry block.
792 if (LLVMBB == &Fn.getEntryBlock()) {
793 CurDAG->setRoot(SDB->getControlRoot());
797 FastIS->startNewBlock(BB);
798 // Do FastISel on as many instructions as possible.
799 for (; BI != End; ++BI) {
800 // Just before the terminator instruction, insert instructions to
801 // feed PHI nodes in successor blocks.
802 if (isa<TerminatorInst>(BI))
803 if (!HandlePHINodesInSuccessorBlocksFast(LLVMBB, FastIS)) {
804 ++NumFastIselFailures;
805 ResetDebugLoc(SDB, FastIS);
806 if (EnableFastISelVerbose || EnableFastISelAbort) {
807 dbgs() << "FastISel miss: ";
810 assert(!EnableFastISelAbort &&
811 "FastISel didn't handle a PHI in a successor");
815 SetDebugLoc(BI, SDB, FastIS, &MF);
817 // Try to select the instruction with FastISel.
818 if (FastIS->SelectInstruction(BI)) {
819 ResetDebugLoc(SDB, FastIS);
823 // Clear out the debug location so that it doesn't carry over to
824 // unrelated instructions.
825 ResetDebugLoc(SDB, FastIS);
827 // Then handle certain instructions as single-LLVM-Instruction blocks.
828 if (isa<CallInst>(BI)) {
829 ++NumFastIselFailures;
830 if (EnableFastISelVerbose || EnableFastISelAbort) {
831 dbgs() << "FastISel missed call: ";
835 if (!BI->getType()->isVoidTy()) {
836 unsigned &R = FuncInfo->ValueMap[BI];
838 R = FuncInfo->CreateRegForValue(BI);
841 bool HadTailCall = false;
842 SelectBasicBlock(LLVMBB, BI, llvm::next(BI), HadTailCall);
844 // If the call was emitted as a tail call, we're done with the block.
850 // If the instruction was codegen'd with multiple blocks,
851 // inform the FastISel object where to resume inserting.
852 FastIS->setCurrentBlock(BB);
856 // Otherwise, give up on FastISel for the rest of the block.
857 // For now, be a little lenient about non-branch terminators.
858 if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
859 ++NumFastIselFailures;
860 if (EnableFastISelVerbose || EnableFastISelAbort) {
861 dbgs() << "FastISel miss: ";
864 if (EnableFastISelAbort)
865 // The "fast" selector couldn't handle something and bailed.
866 // For the purpose of debugging, just abort.
867 llvm_unreachable("FastISel didn't select the entire block");
873 // Run SelectionDAG instruction selection on the remainder of the block
874 // not handled by FastISel. If FastISel is not run, this is the entire
878 SelectBasicBlock(LLVMBB, BI, End, HadTailCall);
888 SelectionDAGISel::FinishBasicBlock() {
890 DEBUG(dbgs() << "Target-post-processed machine code:\n");
893 DEBUG(dbgs() << "Total amount of phi nodes to update: "
894 << SDB->PHINodesToUpdate.size() << "\n");
895 DEBUG(for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i)
896 dbgs() << "Node " << i << " : ("
897 << SDB->PHINodesToUpdate[i].first
898 << ", " << SDB->PHINodesToUpdate[i].second << ")\n");
900 // Next, now that we know what the last MBB the LLVM BB expanded is, update
901 // PHI nodes in successors.
902 if (SDB->SwitchCases.empty() &&
903 SDB->JTCases.empty() &&
904 SDB->BitTestCases.empty()) {
905 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
906 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
907 assert(PHI->isPHI() &&
908 "This is not a machine PHI node that we are updating!");
909 if (!BB->isSuccessor(PHI->getParent()))
911 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
913 PHI->addOperand(MachineOperand::CreateMBB(BB));
915 SDB->PHINodesToUpdate.clear();
919 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
920 // Lower header first, if it wasn't already lowered
921 if (!SDB->BitTestCases[i].Emitted) {
922 // Set the current basic block to the mbb we wish to insert the code into
923 BB = SDB->BitTestCases[i].Parent;
924 SDB->setCurrentBasicBlock(BB);
926 SDB->visitBitTestHeader(SDB->BitTestCases[i]);
927 CurDAG->setRoot(SDB->getRoot());
932 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
933 // Set the current basic block to the mbb we wish to insert the code into
934 BB = SDB->BitTestCases[i].Cases[j].ThisBB;
935 SDB->setCurrentBasicBlock(BB);
938 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
939 SDB->BitTestCases[i].Reg,
940 SDB->BitTestCases[i].Cases[j]);
942 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
943 SDB->BitTestCases[i].Reg,
944 SDB->BitTestCases[i].Cases[j]);
947 CurDAG->setRoot(SDB->getRoot());
953 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
954 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
955 MachineBasicBlock *PHIBB = PHI->getParent();
956 assert(PHI->isPHI() &&
957 "This is not a machine PHI node that we are updating!");
958 // This is "default" BB. We have two jumps to it. From "header" BB and
959 // from last "case" BB.
960 if (PHIBB == SDB->BitTestCases[i].Default) {
961 PHI->addOperand(MachineOperand::
962 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
963 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
964 PHI->addOperand(MachineOperand::
965 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
966 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
969 // One of "cases" BB.
970 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
972 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
973 if (cBB->isSuccessor(PHIBB)) {
974 PHI->addOperand(MachineOperand::
975 CreateReg(SDB->PHINodesToUpdate[pi].second, false));
976 PHI->addOperand(MachineOperand::CreateMBB(cBB));
981 SDB->BitTestCases.clear();
983 // If the JumpTable record is filled in, then we need to emit a jump table.
984 // Updating the PHI nodes is tricky in this case, since we need to determine
985 // whether the PHI is a successor of the range check MBB or the jump table MBB
986 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
987 // Lower header first, if it wasn't already lowered
988 if (!SDB->JTCases[i].first.Emitted) {
989 // Set the current basic block to the mbb we wish to insert the code into
990 BB = SDB->JTCases[i].first.HeaderBB;
991 SDB->setCurrentBasicBlock(BB);
993 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first);
994 CurDAG->setRoot(SDB->getRoot());
999 // Set the current basic block to the mbb we wish to insert the code into
1000 BB = SDB->JTCases[i].second.MBB;
1001 SDB->setCurrentBasicBlock(BB);
1003 SDB->visitJumpTable(SDB->JTCases[i].second);
1004 CurDAG->setRoot(SDB->getRoot());
1005 CodeGenAndEmitDAG();
1009 for (unsigned pi = 0, pe = SDB->PHINodesToUpdate.size(); pi != pe; ++pi) {
1010 MachineInstr *PHI = SDB->PHINodesToUpdate[pi].first;
1011 MachineBasicBlock *PHIBB = PHI->getParent();
1012 assert(PHI->isPHI() &&
1013 "This is not a machine PHI node that we are updating!");
1014 // "default" BB. We can go there only from header BB.
1015 if (PHIBB == SDB->JTCases[i].second.Default) {
1017 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1019 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1021 // JT BB. Just iterate over successors here
1022 if (BB->isSuccessor(PHIBB)) {
1024 (MachineOperand::CreateReg(SDB->PHINodesToUpdate[pi].second, false));
1025 PHI->addOperand(MachineOperand::CreateMBB(BB));
1029 SDB->JTCases.clear();
1031 // If the switch block involved a branch to one of the actual successors, we
1032 // need to update PHI nodes in that block.
1033 for (unsigned i = 0, e = SDB->PHINodesToUpdate.size(); i != e; ++i) {
1034 MachineInstr *PHI = SDB->PHINodesToUpdate[i].first;
1035 assert(PHI->isPHI() &&
1036 "This is not a machine PHI node that we are updating!");
1037 if (BB->isSuccessor(PHI->getParent())) {
1038 PHI->addOperand(MachineOperand::CreateReg(SDB->PHINodesToUpdate[i].second,
1040 PHI->addOperand(MachineOperand::CreateMBB(BB));
1044 // If we generated any switch lowering information, build and codegen any
1045 // additional DAGs necessary.
1046 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1047 // Set the current basic block to the mbb we wish to insert the code into
1048 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB;
1049 SDB->setCurrentBasicBlock(BB);
1052 SDB->visitSwitchCase(SDB->SwitchCases[i]);
1053 CurDAG->setRoot(SDB->getRoot());
1054 CodeGenAndEmitDAG();
1056 // Handle any PHI nodes in successors of this chunk, as if we were coming
1057 // from the original BB before switch expansion. Note that PHI nodes can
1058 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1059 // handle them the right number of times.
1060 while ((BB = SDB->SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
1061 // If new BB's are created during scheduling, the edges may have been
1062 // updated. That is, the edge from ThisBB to BB may have been split and
1063 // BB's predecessor is now another block.
1064 DenseMap<MachineBasicBlock*, MachineBasicBlock*>::iterator EI =
1065 SDB->EdgeMapping.find(BB);
1066 if (EI != SDB->EdgeMapping.end())
1067 ThisBB = EI->second;
1069 // BB may have been removed from the CFG if a branch was constant folded.
1070 if (ThisBB->isSuccessor(BB)) {
1071 for (MachineBasicBlock::iterator Phi = BB->begin();
1072 Phi != BB->end() && Phi->isPHI();
1074 // This value for this PHI node is recorded in PHINodesToUpdate.
1075 for (unsigned pn = 0; ; ++pn) {
1076 assert(pn != SDB->PHINodesToUpdate.size() &&
1077 "Didn't find PHI entry!");
1078 if (SDB->PHINodesToUpdate[pn].first == Phi) {
1079 Phi->addOperand(MachineOperand::
1080 CreateReg(SDB->PHINodesToUpdate[pn].second,
1082 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1089 // Don't process RHS if same block as LHS.
1090 if (BB == SDB->SwitchCases[i].FalseBB)
1091 SDB->SwitchCases[i].FalseBB = 0;
1093 // If we haven't handled the RHS, do so now. Otherwise, we're done.
1094 SDB->SwitchCases[i].TrueBB = SDB->SwitchCases[i].FalseBB;
1095 SDB->SwitchCases[i].FalseBB = 0;
1097 assert(SDB->SwitchCases[i].TrueBB == 0 && SDB->SwitchCases[i].FalseBB == 0);
1100 SDB->SwitchCases.clear();
1102 SDB->PHINodesToUpdate.clear();
1106 /// Create the scheduler. If a specific scheduler was specified
1107 /// via the SchedulerRegistry, use it, otherwise select the
1108 /// one preferred by the target.
1110 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1111 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1115 RegisterScheduler::setDefault(Ctor);
1118 return Ctor(this, OptLevel);
1121 ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
1122 return new ScheduleHazardRecognizer();
1125 //===----------------------------------------------------------------------===//
1126 // Helper functions used by the generated instruction selector.
1127 //===----------------------------------------------------------------------===//
1128 // Calls to these methods are generated by tblgen.
1130 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1131 /// the dag combiner simplified the 255, we still want to match. RHS is the
1132 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1133 /// specified in the .td file (e.g. 255).
1134 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1135 int64_t DesiredMaskS) const {
1136 const APInt &ActualMask = RHS->getAPIntValue();
1137 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1139 // If the actual mask exactly matches, success!
1140 if (ActualMask == DesiredMask)
1143 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1144 if (ActualMask.intersects(~DesiredMask))
1147 // Otherwise, the DAG Combiner may have proven that the value coming in is
1148 // either already zero or is not demanded. Check for known zero input bits.
1149 APInt NeededMask = DesiredMask & ~ActualMask;
1150 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1153 // TODO: check to see if missing bits are just not demanded.
1155 // Otherwise, this pattern doesn't match.
1159 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1160 /// the dag combiner simplified the 255, we still want to match. RHS is the
1161 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1162 /// specified in the .td file (e.g. 255).
1163 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1164 int64_t DesiredMaskS) const {
1165 const APInt &ActualMask = RHS->getAPIntValue();
1166 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1168 // If the actual mask exactly matches, success!
1169 if (ActualMask == DesiredMask)
1172 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1173 if (ActualMask.intersects(~DesiredMask))
1176 // Otherwise, the DAG Combiner may have proven that the value coming in is
1177 // either already zero or is not demanded. Check for known zero input bits.
1178 APInt NeededMask = DesiredMask & ~ActualMask;
1180 APInt KnownZero, KnownOne;
1181 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1183 // If all the missing bits in the or are already known to be set, match!
1184 if ((NeededMask & KnownOne) == NeededMask)
1187 // TODO: check to see if missing bits are just not demanded.
1189 // Otherwise, this pattern doesn't match.
1194 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1195 /// by tblgen. Others should not call it.
1196 void SelectionDAGISel::
1197 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1198 std::vector<SDValue> InOps;
1199 std::swap(InOps, Ops);
1201 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1202 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1203 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1205 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1206 if (InOps[e-1].getValueType() == MVT::Flag)
1207 --e; // Don't process a flag operand if it is here.
1210 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1211 if (!InlineAsm::isMemKind(Flags)) {
1212 // Just skip over this operand, copying the operands verbatim.
1213 Ops.insert(Ops.end(), InOps.begin()+i,
1214 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1215 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1217 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1218 "Memory operand with multiple values?");
1219 // Otherwise, this is a memory operand. Ask the target to select it.
1220 std::vector<SDValue> SelOps;
1221 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1222 report_fatal_error("Could not match memory address. Inline asm"
1225 // Add this to the output node.
1227 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1228 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1229 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1234 // Add the flag input back if present.
1235 if (e != InOps.size())
1236 Ops.push_back(InOps.back());
1239 /// findFlagUse - Return use of EVT::Flag value produced by the specified
1242 static SDNode *findFlagUse(SDNode *N) {
1243 unsigned FlagResNo = N->getNumValues()-1;
1244 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1245 SDUse &Use = I.getUse();
1246 if (Use.getResNo() == FlagResNo)
1247 return Use.getUser();
1252 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1253 /// This function recursively traverses up the operand chain, ignoring
1255 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1256 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1257 bool IgnoreChains) {
1258 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1259 // greater than all of its (recursive) operands. If we scan to a point where
1260 // 'use' is smaller than the node we're scanning for, then we know we will
1263 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1264 // happen because we scan down to newly selected nodes in the case of flag
1266 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1269 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1270 // won't fail if we scan it again.
1271 if (!Visited.insert(Use))
1274 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1275 // Ignore chain uses, they are validated by HandleMergeInputChains.
1276 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1279 SDNode *N = Use->getOperand(i).getNode();
1281 if (Use == ImmedUse || Use == Root)
1282 continue; // We are not looking for immediate use.
1287 // Traverse up the operand chain.
1288 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1294 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1295 /// operand node N of U during instruction selection that starts at Root.
1296 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1297 SDNode *Root) const {
1298 if (OptLevel == CodeGenOpt::None) return false;
1299 return N.hasOneUse();
1302 /// IsLegalToFold - Returns true if the specific operand node N of
1303 /// U can be folded during instruction selection that starts at Root.
1304 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1305 bool IgnoreChains) const {
1306 if (OptLevel == CodeGenOpt::None) return false;
1308 // If Root use can somehow reach N through a path that that doesn't contain
1309 // U then folding N would create a cycle. e.g. In the following
1310 // diagram, Root can reach N through X. If N is folded into into Root, then
1311 // X is both a predecessor and a successor of U.
1322 // * indicates nodes to be folded together.
1324 // If Root produces a flag, then it gets (even more) interesting. Since it
1325 // will be "glued" together with its flag use in the scheduler, we need to
1326 // check if it might reach N.
1345 // If FU (flag use) indirectly reaches N (the load), and Root folds N
1346 // (call it Fold), then X is a predecessor of FU and a successor of
1347 // Fold. But since Fold and FU are flagged together, this will create
1348 // a cycle in the scheduling graph.
1350 // If the node has flags, walk down the graph to the "lowest" node in the
1352 EVT VT = Root->getValueType(Root->getNumValues()-1);
1353 while (VT == MVT::Flag) {
1354 SDNode *FU = findFlagUse(Root);
1358 VT = Root->getValueType(Root->getNumValues()-1);
1360 // If our query node has a flag result with a use, we've walked up it. If
1361 // the user (which has already been selected) has a chain or indirectly uses
1362 // the chain, our WalkChainUsers predicate will not consider it. Because of
1363 // this, we cannot ignore chains in this predicate.
1364 IgnoreChains = false;
1368 SmallPtrSet<SDNode*, 16> Visited;
1369 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1372 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1373 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1374 SelectInlineAsmMemoryOperands(Ops);
1376 std::vector<EVT> VTs;
1377 VTs.push_back(MVT::Other);
1378 VTs.push_back(MVT::Flag);
1379 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1380 VTs, &Ops[0], Ops.size());
1382 return New.getNode();
1385 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1386 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1389 /// GetVBR - decode a vbr encoding whose top bit is set.
1390 ALWAYS_INLINE static uint64_t
1391 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1392 assert(Val >= 128 && "Not a VBR");
1393 Val &= 127; // Remove first vbr bit.
1398 NextBits = MatcherTable[Idx++];
1399 Val |= (NextBits&127) << Shift;
1401 } while (NextBits & 128);
1407 /// UpdateChainsAndFlags - When a match is complete, this method updates uses of
1408 /// interior flag and chain results to use the new flag and chain results.
1409 void SelectionDAGISel::
1410 UpdateChainsAndFlags(SDNode *NodeToMatch, SDValue InputChain,
1411 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1413 const SmallVectorImpl<SDNode*> &FlagResultNodesMatched,
1414 bool isMorphNodeTo) {
1415 SmallVector<SDNode*, 4> NowDeadNodes;
1417 ISelUpdater ISU(ISelPosition);
1419 // Now that all the normal results are replaced, we replace the chain and
1420 // flag results if present.
1421 if (!ChainNodesMatched.empty()) {
1422 assert(InputChain.getNode() != 0 &&
1423 "Matched input chains but didn't produce a chain");
1424 // Loop over all of the nodes we matched that produced a chain result.
1425 // Replace all the chain results with the final chain we ended up with.
1426 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1427 SDNode *ChainNode = ChainNodesMatched[i];
1429 // If this node was already deleted, don't look at it.
1430 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1433 // Don't replace the results of the root node if we're doing a
1435 if (ChainNode == NodeToMatch && isMorphNodeTo)
1438 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1439 if (ChainVal.getValueType() == MVT::Flag)
1440 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1441 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1442 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1444 // If the node became dead and we haven't already seen it, delete it.
1445 if (ChainNode->use_empty() &&
1446 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1447 NowDeadNodes.push_back(ChainNode);
1451 // If the result produces a flag, update any flag results in the matched
1452 // pattern with the flag result.
1453 if (InputFlag.getNode() != 0) {
1454 // Handle any interior nodes explicitly marked.
1455 for (unsigned i = 0, e = FlagResultNodesMatched.size(); i != e; ++i) {
1456 SDNode *FRN = FlagResultNodesMatched[i];
1458 // If this node was already deleted, don't look at it.
1459 if (FRN->getOpcode() == ISD::DELETED_NODE)
1462 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Flag &&
1463 "Doesn't have a flag result");
1464 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1467 // If the node became dead and we haven't already seen it, delete it.
1468 if (FRN->use_empty() &&
1469 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1470 NowDeadNodes.push_back(FRN);
1474 if (!NowDeadNodes.empty())
1475 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1477 DEBUG(errs() << "ISEL: Match complete!\n");
1483 CR_LeadsToInteriorNode
1486 /// WalkChainUsers - Walk down the users of the specified chained node that is
1487 /// part of the pattern we're matching, looking at all of the users we find.
1488 /// This determines whether something is an interior node, whether we have a
1489 /// non-pattern node in between two pattern nodes (which prevent folding because
1490 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1491 /// between pattern nodes (in which case the TF becomes part of the pattern).
1493 /// The walk we do here is guaranteed to be small because we quickly get down to
1494 /// already selected nodes "below" us.
1496 WalkChainUsers(SDNode *ChainedNode,
1497 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1498 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1499 ChainResult Result = CR_Simple;
1501 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1502 E = ChainedNode->use_end(); UI != E; ++UI) {
1503 // Make sure the use is of the chain, not some other value we produce.
1504 if (UI.getUse().getValueType() != MVT::Other) continue;
1508 // If we see an already-selected machine node, then we've gone beyond the
1509 // pattern that we're selecting down into the already selected chunk of the
1511 if (User->isMachineOpcode() ||
1512 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1515 if (User->getOpcode() == ISD::CopyToReg ||
1516 User->getOpcode() == ISD::CopyFromReg ||
1517 User->getOpcode() == ISD::INLINEASM ||
1518 User->getOpcode() == ISD::EH_LABEL) {
1519 // If their node ID got reset to -1 then they've already been selected.
1520 // Treat them like a MachineOpcode.
1521 if (User->getNodeId() == -1)
1525 // If we have a TokenFactor, we handle it specially.
1526 if (User->getOpcode() != ISD::TokenFactor) {
1527 // If the node isn't a token factor and isn't part of our pattern, then it
1528 // must be a random chained node in between two nodes we're selecting.
1529 // This happens when we have something like:
1534 // Because we structurally match the load/store as a read/modify/write,
1535 // but the call is chained between them. We cannot fold in this case
1536 // because it would induce a cycle in the graph.
1537 if (!std::count(ChainedNodesInPattern.begin(),
1538 ChainedNodesInPattern.end(), User))
1539 return CR_InducesCycle;
1541 // Otherwise we found a node that is part of our pattern. For example in:
1545 // This would happen when we're scanning down from the load and see the
1546 // store as a user. Record that there is a use of ChainedNode that is
1547 // part of the pattern and keep scanning uses.
1548 Result = CR_LeadsToInteriorNode;
1549 InteriorChainedNodes.push_back(User);
1553 // If we found a TokenFactor, there are two cases to consider: first if the
1554 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1555 // uses of the TF are in our pattern) we just want to ignore it. Second,
1556 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1562 // | \ DAG's like cheese
1565 // [TokenFactor] [Op]
1572 // In this case, the TokenFactor becomes part of our match and we rewrite it
1573 // as a new TokenFactor.
1575 // To distinguish these two cases, do a recursive walk down the uses.
1576 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1578 // If the uses of the TokenFactor are just already-selected nodes, ignore
1579 // it, it is "below" our pattern.
1581 case CR_InducesCycle:
1582 // If the uses of the TokenFactor lead to nodes that are not part of our
1583 // pattern that are not selected, folding would turn this into a cycle,
1585 return CR_InducesCycle;
1586 case CR_LeadsToInteriorNode:
1587 break; // Otherwise, keep processing.
1590 // Okay, we know we're in the interesting interior case. The TokenFactor
1591 // is now going to be considered part of the pattern so that we rewrite its
1592 // uses (it may have uses that are not part of the pattern) with the
1593 // ultimate chain result of the generated code. We will also add its chain
1594 // inputs as inputs to the ultimate TokenFactor we create.
1595 Result = CR_LeadsToInteriorNode;
1596 ChainedNodesInPattern.push_back(User);
1597 InteriorChainedNodes.push_back(User);
1604 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1605 /// operation for when the pattern matched at least one node with a chains. The
1606 /// input vector contains a list of all of the chained nodes that we match. We
1607 /// must determine if this is a valid thing to cover (i.e. matching it won't
1608 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1609 /// be used as the input node chain for the generated nodes.
1611 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1612 SelectionDAG *CurDAG) {
1613 // Walk all of the chained nodes we've matched, recursively scanning down the
1614 // users of the chain result. This adds any TokenFactor nodes that are caught
1615 // in between chained nodes to the chained and interior nodes list.
1616 SmallVector<SDNode*, 3> InteriorChainedNodes;
1617 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1618 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1619 InteriorChainedNodes) == CR_InducesCycle)
1620 return SDValue(); // Would induce a cycle.
1623 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1624 // that we are interested in. Form our input TokenFactor node.
1625 SmallVector<SDValue, 3> InputChains;
1626 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1627 // Add the input chain of this node to the InputChains list (which will be
1628 // the operands of the generated TokenFactor) if it's not an interior node.
1629 SDNode *N = ChainNodesMatched[i];
1630 if (N->getOpcode() != ISD::TokenFactor) {
1631 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1634 // Otherwise, add the input chain.
1635 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1636 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1637 InputChains.push_back(InChain);
1641 // If we have a token factor, we want to add all inputs of the token factor
1642 // that are not part of the pattern we're matching.
1643 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1644 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1645 N->getOperand(op).getNode()))
1646 InputChains.push_back(N->getOperand(op));
1651 if (InputChains.size() == 1)
1652 return InputChains[0];
1653 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1654 MVT::Other, &InputChains[0], InputChains.size());
1657 /// MorphNode - Handle morphing a node in place for the selector.
1658 SDNode *SelectionDAGISel::
1659 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1660 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1661 // It is possible we're using MorphNodeTo to replace a node with no
1662 // normal results with one that has a normal result (or we could be
1663 // adding a chain) and the input could have flags and chains as well.
1664 // In this case we need to shift the operands down.
1665 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1666 // than the old isel though.
1667 int OldFlagResultNo = -1, OldChainResultNo = -1;
1669 unsigned NTMNumResults = Node->getNumValues();
1670 if (Node->getValueType(NTMNumResults-1) == MVT::Flag) {
1671 OldFlagResultNo = NTMNumResults-1;
1672 if (NTMNumResults != 1 &&
1673 Node->getValueType(NTMNumResults-2) == MVT::Other)
1674 OldChainResultNo = NTMNumResults-2;
1675 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1676 OldChainResultNo = NTMNumResults-1;
1678 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1679 // that this deletes operands of the old node that become dead.
1680 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1682 // MorphNodeTo can operate in two ways: if an existing node with the
1683 // specified operands exists, it can just return it. Otherwise, it
1684 // updates the node in place to have the requested operands.
1686 // If we updated the node in place, reset the node ID. To the isel,
1687 // this should be just like a newly allocated machine node.
1691 unsigned ResNumResults = Res->getNumValues();
1692 // Move the flag if needed.
1693 if ((EmitNodeInfo & OPFL_FlagOutput) && OldFlagResultNo != -1 &&
1694 (unsigned)OldFlagResultNo != ResNumResults-1)
1695 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldFlagResultNo),
1696 SDValue(Res, ResNumResults-1));
1698 if ((EmitNodeInfo & OPFL_FlagOutput) != 0)
1701 // Move the chain reference if needed.
1702 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1703 (unsigned)OldChainResultNo != ResNumResults-1)
1704 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1705 SDValue(Res, ResNumResults-1));
1707 // Otherwise, no replacement happened because the node already exists. Replace
1708 // Uses of the old node with the new one.
1710 CurDAG->ReplaceAllUsesWith(Node, Res);
1715 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1716 ALWAYS_INLINE static bool
1717 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1718 SDValue N, const SmallVectorImpl<SDValue> &RecordedNodes) {
1719 // Accept if it is exactly the same as a previously recorded node.
1720 unsigned RecNo = MatcherTable[MatcherIndex++];
1721 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1722 return N == RecordedNodes[RecNo];
1725 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1726 ALWAYS_INLINE static bool
1727 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1728 SelectionDAGISel &SDISel) {
1729 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1732 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1733 ALWAYS_INLINE static bool
1734 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1735 SelectionDAGISel &SDISel, SDNode *N) {
1736 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1739 ALWAYS_INLINE static bool
1740 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1742 uint16_t Opc = MatcherTable[MatcherIndex++];
1743 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1744 return N->getOpcode() == Opc;
1747 ALWAYS_INLINE static bool
1748 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1749 SDValue N, const TargetLowering &TLI) {
1750 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1751 if (N.getValueType() == VT) return true;
1753 // Handle the case when VT is iPTR.
1754 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1757 ALWAYS_INLINE static bool
1758 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1759 SDValue N, const TargetLowering &TLI,
1761 if (ChildNo >= N.getNumOperands())
1762 return false; // Match fails if out of range child #.
1763 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1767 ALWAYS_INLINE static bool
1768 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1770 return cast<CondCodeSDNode>(N)->get() ==
1771 (ISD::CondCode)MatcherTable[MatcherIndex++];
1774 ALWAYS_INLINE static bool
1775 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1776 SDValue N, const TargetLowering &TLI) {
1777 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1778 if (cast<VTSDNode>(N)->getVT() == VT)
1781 // Handle the case when VT is iPTR.
1782 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1785 ALWAYS_INLINE static bool
1786 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1788 int64_t Val = MatcherTable[MatcherIndex++];
1790 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1792 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1793 return C != 0 && C->getSExtValue() == Val;
1796 ALWAYS_INLINE static bool
1797 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1798 SDValue N, SelectionDAGISel &SDISel) {
1799 int64_t Val = MatcherTable[MatcherIndex++];
1801 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1803 if (N->getOpcode() != ISD::AND) return false;
1805 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1806 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1809 ALWAYS_INLINE static bool
1810 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1811 SDValue N, SelectionDAGISel &SDISel) {
1812 int64_t Val = MatcherTable[MatcherIndex++];
1814 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1816 if (N->getOpcode() != ISD::OR) return false;
1818 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1819 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1822 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1823 /// scope, evaluate the current node. If the current predicate is known to
1824 /// fail, set Result=true and return anything. If the current predicate is
1825 /// known to pass, set Result=false and return the MatcherIndex to continue
1826 /// with. If the current predicate is unknown, set Result=false and return the
1827 /// MatcherIndex to continue with.
1828 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1829 unsigned Index, SDValue N,
1830 bool &Result, SelectionDAGISel &SDISel,
1831 SmallVectorImpl<SDValue> &RecordedNodes){
1832 switch (Table[Index++]) {
1835 return Index-1; // Could not evaluate this predicate.
1836 case SelectionDAGISel::OPC_CheckSame:
1837 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1839 case SelectionDAGISel::OPC_CheckPatternPredicate:
1840 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1842 case SelectionDAGISel::OPC_CheckPredicate:
1843 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1845 case SelectionDAGISel::OPC_CheckOpcode:
1846 Result = !::CheckOpcode(Table, Index, N.getNode());
1848 case SelectionDAGISel::OPC_CheckType:
1849 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1851 case SelectionDAGISel::OPC_CheckChild0Type:
1852 case SelectionDAGISel::OPC_CheckChild1Type:
1853 case SelectionDAGISel::OPC_CheckChild2Type:
1854 case SelectionDAGISel::OPC_CheckChild3Type:
1855 case SelectionDAGISel::OPC_CheckChild4Type:
1856 case SelectionDAGISel::OPC_CheckChild5Type:
1857 case SelectionDAGISel::OPC_CheckChild6Type:
1858 case SelectionDAGISel::OPC_CheckChild7Type:
1859 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1860 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1862 case SelectionDAGISel::OPC_CheckCondCode:
1863 Result = !::CheckCondCode(Table, Index, N);
1865 case SelectionDAGISel::OPC_CheckValueType:
1866 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
1868 case SelectionDAGISel::OPC_CheckInteger:
1869 Result = !::CheckInteger(Table, Index, N);
1871 case SelectionDAGISel::OPC_CheckAndImm:
1872 Result = !::CheckAndImm(Table, Index, N, SDISel);
1874 case SelectionDAGISel::OPC_CheckOrImm:
1875 Result = !::CheckOrImm(Table, Index, N, SDISel);
1882 /// FailIndex - If this match fails, this is the index to continue with.
1885 /// NodeStack - The node stack when the scope was formed.
1886 SmallVector<SDValue, 4> NodeStack;
1888 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
1889 unsigned NumRecordedNodes;
1891 /// NumMatchedMemRefs - The number of matched memref entries.
1892 unsigned NumMatchedMemRefs;
1894 /// InputChain/InputFlag - The current chain/flag
1895 SDValue InputChain, InputFlag;
1897 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
1898 bool HasChainNodesMatched, HasFlagResultNodesMatched;
1901 SDNode *SelectionDAGISel::
1902 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
1903 unsigned TableSize) {
1904 // FIXME: Should these even be selected? Handle these cases in the caller?
1905 switch (NodeToMatch->getOpcode()) {
1908 case ISD::EntryToken: // These nodes remain the same.
1909 case ISD::BasicBlock:
1911 //case ISD::VALUETYPE:
1912 //case ISD::CONDCODE:
1913 case ISD::HANDLENODE:
1914 case ISD::MDNODE_SDNODE:
1915 case ISD::TargetConstant:
1916 case ISD::TargetConstantFP:
1917 case ISD::TargetConstantPool:
1918 case ISD::TargetFrameIndex:
1919 case ISD::TargetExternalSymbol:
1920 case ISD::TargetBlockAddress:
1921 case ISD::TargetJumpTable:
1922 case ISD::TargetGlobalTLSAddress:
1923 case ISD::TargetGlobalAddress:
1924 case ISD::TokenFactor:
1925 case ISD::CopyFromReg:
1926 case ISD::CopyToReg:
1928 NodeToMatch->setNodeId(-1); // Mark selected.
1930 case ISD::AssertSext:
1931 case ISD::AssertZext:
1932 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
1933 NodeToMatch->getOperand(0));
1935 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
1936 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
1939 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
1941 // Set up the node stack with NodeToMatch as the only node on the stack.
1942 SmallVector<SDValue, 8> NodeStack;
1943 SDValue N = SDValue(NodeToMatch, 0);
1944 NodeStack.push_back(N);
1946 // MatchScopes - Scopes used when matching, if a match failure happens, this
1947 // indicates where to continue checking.
1948 SmallVector<MatchScope, 8> MatchScopes;
1950 // RecordedNodes - This is the set of nodes that have been recorded by the
1952 SmallVector<SDValue, 8> RecordedNodes;
1954 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
1956 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
1958 // These are the current input chain and flag for use when generating nodes.
1959 // Various Emit operations change these. For example, emitting a copytoreg
1960 // uses and updates these.
1961 SDValue InputChain, InputFlag;
1963 // ChainNodesMatched - If a pattern matches nodes that have input/output
1964 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
1965 // which ones they are. The result is captured into this list so that we can
1966 // update the chain results when the pattern is complete.
1967 SmallVector<SDNode*, 3> ChainNodesMatched;
1968 SmallVector<SDNode*, 3> FlagResultNodesMatched;
1970 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
1971 NodeToMatch->dump(CurDAG);
1974 // Determine where to start the interpreter. Normally we start at opcode #0,
1975 // but if the state machine starts with an OPC_SwitchOpcode, then we
1976 // accelerate the first lookup (which is guaranteed to be hot) with the
1977 // OpcodeOffset table.
1978 unsigned MatcherIndex = 0;
1980 if (!OpcodeOffset.empty()) {
1981 // Already computed the OpcodeOffset table, just index into it.
1982 if (N.getOpcode() < OpcodeOffset.size())
1983 MatcherIndex = OpcodeOffset[N.getOpcode()];
1984 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
1986 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
1987 // Otherwise, the table isn't computed, but the state machine does start
1988 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
1989 // is the first time we're selecting an instruction.
1992 // Get the size of this case.
1993 unsigned CaseSize = MatcherTable[Idx++];
1995 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
1996 if (CaseSize == 0) break;
1998 // Get the opcode, add the index to the table.
1999 uint16_t Opc = MatcherTable[Idx++];
2000 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2001 if (Opc >= OpcodeOffset.size())
2002 OpcodeOffset.resize((Opc+1)*2);
2003 OpcodeOffset[Opc] = Idx;
2007 // Okay, do the lookup for the first opcode.
2008 if (N.getOpcode() < OpcodeOffset.size())
2009 MatcherIndex = OpcodeOffset[N.getOpcode()];
2013 assert(MatcherIndex < TableSize && "Invalid index");
2015 unsigned CurrentOpcodeIndex = MatcherIndex;
2017 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2020 // Okay, the semantics of this operation are that we should push a scope
2021 // then evaluate the first child. However, pushing a scope only to have
2022 // the first check fail (which then pops it) is inefficient. If we can
2023 // determine immediately that the first check (or first several) will
2024 // immediately fail, don't even bother pushing a scope for them.
2028 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2029 if (NumToSkip & 128)
2030 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2031 // Found the end of the scope with no match.
2032 if (NumToSkip == 0) {
2037 FailIndex = MatcherIndex+NumToSkip;
2039 unsigned MatcherIndexOfPredicate = MatcherIndex;
2040 (void)MatcherIndexOfPredicate; // silence warning.
2042 // If we can't evaluate this predicate without pushing a scope (e.g. if
2043 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2044 // push the scope and evaluate the full predicate chain.
2046 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2047 Result, *this, RecordedNodes);
2051 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2052 << "index " << MatcherIndexOfPredicate
2053 << ", continuing at " << FailIndex << "\n");
2054 ++NumDAGIselRetries;
2056 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2057 // move to the next case.
2058 MatcherIndex = FailIndex;
2061 // If the whole scope failed to match, bail.
2062 if (FailIndex == 0) break;
2064 // Push a MatchScope which indicates where to go if the first child fails
2066 MatchScope NewEntry;
2067 NewEntry.FailIndex = FailIndex;
2068 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2069 NewEntry.NumRecordedNodes = RecordedNodes.size();
2070 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2071 NewEntry.InputChain = InputChain;
2072 NewEntry.InputFlag = InputFlag;
2073 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2074 NewEntry.HasFlagResultNodesMatched = !FlagResultNodesMatched.empty();
2075 MatchScopes.push_back(NewEntry);
2078 case OPC_RecordNode:
2079 // Remember this node, it may end up being an operand in the pattern.
2080 RecordedNodes.push_back(N);
2083 case OPC_RecordChild0: case OPC_RecordChild1:
2084 case OPC_RecordChild2: case OPC_RecordChild3:
2085 case OPC_RecordChild4: case OPC_RecordChild5:
2086 case OPC_RecordChild6: case OPC_RecordChild7: {
2087 unsigned ChildNo = Opcode-OPC_RecordChild0;
2088 if (ChildNo >= N.getNumOperands())
2089 break; // Match fails if out of range child #.
2091 RecordedNodes.push_back(N->getOperand(ChildNo));
2094 case OPC_RecordMemRef:
2095 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2098 case OPC_CaptureFlagInput:
2099 // If the current node has an input flag, capture it in InputFlag.
2100 if (N->getNumOperands() != 0 &&
2101 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag)
2102 InputFlag = N->getOperand(N->getNumOperands()-1);
2105 case OPC_MoveChild: {
2106 unsigned ChildNo = MatcherTable[MatcherIndex++];
2107 if (ChildNo >= N.getNumOperands())
2108 break; // Match fails if out of range child #.
2109 N = N.getOperand(ChildNo);
2110 NodeStack.push_back(N);
2114 case OPC_MoveParent:
2115 // Pop the current node off the NodeStack.
2116 NodeStack.pop_back();
2117 assert(!NodeStack.empty() && "Node stack imbalance!");
2118 N = NodeStack.back();
2122 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2124 case OPC_CheckPatternPredicate:
2125 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2127 case OPC_CheckPredicate:
2128 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2132 case OPC_CheckComplexPat: {
2133 unsigned CPNum = MatcherTable[MatcherIndex++];
2134 unsigned RecNo = MatcherTable[MatcherIndex++];
2135 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2136 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo], CPNum,
2141 case OPC_CheckOpcode:
2142 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2146 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2149 case OPC_SwitchOpcode: {
2150 unsigned CurNodeOpcode = N.getOpcode();
2151 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2154 // Get the size of this case.
2155 CaseSize = MatcherTable[MatcherIndex++];
2157 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2158 if (CaseSize == 0) break;
2160 uint16_t Opc = MatcherTable[MatcherIndex++];
2161 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2163 // If the opcode matches, then we will execute this case.
2164 if (CurNodeOpcode == Opc)
2167 // Otherwise, skip over this case.
2168 MatcherIndex += CaseSize;
2171 // If no cases matched, bail out.
2172 if (CaseSize == 0) break;
2174 // Otherwise, execute the case we found.
2175 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2176 << " to " << MatcherIndex << "\n");
2180 case OPC_SwitchType: {
2181 MVT::SimpleValueType CurNodeVT = N.getValueType().getSimpleVT().SimpleTy;
2182 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2185 // Get the size of this case.
2186 CaseSize = MatcherTable[MatcherIndex++];
2188 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2189 if (CaseSize == 0) break;
2191 MVT::SimpleValueType CaseVT =
2192 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2193 if (CaseVT == MVT::iPTR)
2194 CaseVT = TLI.getPointerTy().SimpleTy;
2196 // If the VT matches, then we will execute this case.
2197 if (CurNodeVT == CaseVT)
2200 // Otherwise, skip over this case.
2201 MatcherIndex += CaseSize;
2204 // If no cases matched, bail out.
2205 if (CaseSize == 0) break;
2207 // Otherwise, execute the case we found.
2208 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2209 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2212 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2213 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2214 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2215 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2216 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2217 Opcode-OPC_CheckChild0Type))
2220 case OPC_CheckCondCode:
2221 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2223 case OPC_CheckValueType:
2224 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2226 case OPC_CheckInteger:
2227 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2229 case OPC_CheckAndImm:
2230 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2232 case OPC_CheckOrImm:
2233 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2236 case OPC_CheckFoldableChainNode: {
2237 assert(NodeStack.size() != 1 && "No parent node");
2238 // Verify that all intermediate nodes between the root and this one have
2240 bool HasMultipleUses = false;
2241 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2242 if (!NodeStack[i].hasOneUse()) {
2243 HasMultipleUses = true;
2246 if (HasMultipleUses) break;
2248 // Check to see that the target thinks this is profitable to fold and that
2249 // we can fold it without inducing cycles in the graph.
2250 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2252 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2253 NodeToMatch, true/*We validate our own chains*/))
2258 case OPC_EmitInteger: {
2259 MVT::SimpleValueType VT =
2260 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2261 int64_t Val = MatcherTable[MatcherIndex++];
2263 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2264 RecordedNodes.push_back(CurDAG->getTargetConstant(Val, VT));
2267 case OPC_EmitRegister: {
2268 MVT::SimpleValueType VT =
2269 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2270 unsigned RegNo = MatcherTable[MatcherIndex++];
2271 RecordedNodes.push_back(CurDAG->getRegister(RegNo, VT));
2275 case OPC_EmitConvertToTarget: {
2276 // Convert from IMM/FPIMM to target version.
2277 unsigned RecNo = MatcherTable[MatcherIndex++];
2278 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2279 SDValue Imm = RecordedNodes[RecNo];
2281 if (Imm->getOpcode() == ISD::Constant) {
2282 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2283 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2284 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2285 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2286 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2289 RecordedNodes.push_back(Imm);
2293 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2294 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2295 // These are space-optimized forms of OPC_EmitMergeInputChains.
2296 assert(InputChain.getNode() == 0 &&
2297 "EmitMergeInputChains should be the first chain producing node");
2298 assert(ChainNodesMatched.empty() &&
2299 "Should only have one EmitMergeInputChains per match");
2301 // Read all of the chained nodes.
2302 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2303 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2304 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2306 // FIXME: What if other value results of the node have uses not matched
2308 if (ChainNodesMatched.back() != NodeToMatch &&
2309 !RecordedNodes[RecNo].hasOneUse()) {
2310 ChainNodesMatched.clear();
2314 // Merge the input chains if they are not intra-pattern references.
2315 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2317 if (InputChain.getNode() == 0)
2318 break; // Failed to merge.
2322 case OPC_EmitMergeInputChains: {
2323 assert(InputChain.getNode() == 0 &&
2324 "EmitMergeInputChains should be the first chain producing node");
2325 // This node gets a list of nodes we matched in the input that have
2326 // chains. We want to token factor all of the input chains to these nodes
2327 // together. However, if any of the input chains is actually one of the
2328 // nodes matched in this pattern, then we have an intra-match reference.
2329 // Ignore these because the newly token factored chain should not refer to
2331 unsigned NumChains = MatcherTable[MatcherIndex++];
2332 assert(NumChains != 0 && "Can't TF zero chains");
2334 assert(ChainNodesMatched.empty() &&
2335 "Should only have one EmitMergeInputChains per match");
2337 // Read all of the chained nodes.
2338 for (unsigned i = 0; i != NumChains; ++i) {
2339 unsigned RecNo = MatcherTable[MatcherIndex++];
2340 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2341 ChainNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2343 // FIXME: What if other value results of the node have uses not matched
2345 if (ChainNodesMatched.back() != NodeToMatch &&
2346 !RecordedNodes[RecNo].hasOneUse()) {
2347 ChainNodesMatched.clear();
2352 // If the inner loop broke out, the match fails.
2353 if (ChainNodesMatched.empty())
2356 // Merge the input chains if they are not intra-pattern references.
2357 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2359 if (InputChain.getNode() == 0)
2360 break; // Failed to merge.
2365 case OPC_EmitCopyToReg: {
2366 unsigned RecNo = MatcherTable[MatcherIndex++];
2367 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2368 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2370 if (InputChain.getNode() == 0)
2371 InputChain = CurDAG->getEntryNode();
2373 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2374 DestPhysReg, RecordedNodes[RecNo],
2377 InputFlag = InputChain.getValue(1);
2381 case OPC_EmitNodeXForm: {
2382 unsigned XFormNo = MatcherTable[MatcherIndex++];
2383 unsigned RecNo = MatcherTable[MatcherIndex++];
2384 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2385 RecordedNodes.push_back(RunSDNodeXForm(RecordedNodes[RecNo], XFormNo));
2390 case OPC_MorphNodeTo: {
2391 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2392 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2393 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2394 // Get the result VT list.
2395 unsigned NumVTs = MatcherTable[MatcherIndex++];
2396 SmallVector<EVT, 4> VTs;
2397 for (unsigned i = 0; i != NumVTs; ++i) {
2398 MVT::SimpleValueType VT =
2399 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2400 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2404 if (EmitNodeInfo & OPFL_Chain)
2405 VTs.push_back(MVT::Other);
2406 if (EmitNodeInfo & OPFL_FlagOutput)
2407 VTs.push_back(MVT::Flag);
2409 // This is hot code, so optimize the two most common cases of 1 and 2
2412 if (VTs.size() == 1)
2413 VTList = CurDAG->getVTList(VTs[0]);
2414 else if (VTs.size() == 2)
2415 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2417 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2419 // Get the operand list.
2420 unsigned NumOps = MatcherTable[MatcherIndex++];
2421 SmallVector<SDValue, 8> Ops;
2422 for (unsigned i = 0; i != NumOps; ++i) {
2423 unsigned RecNo = MatcherTable[MatcherIndex++];
2425 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2427 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2428 Ops.push_back(RecordedNodes[RecNo]);
2431 // If there are variadic operands to add, handle them now.
2432 if (EmitNodeInfo & OPFL_VariadicInfo) {
2433 // Determine the start index to copy from.
2434 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2435 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2436 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2437 "Invalid variadic node");
2438 // Copy all of the variadic operands, not including a potential flag
2440 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2442 SDValue V = NodeToMatch->getOperand(i);
2443 if (V.getValueType() == MVT::Flag) break;
2448 // If this has chain/flag inputs, add them.
2449 if (EmitNodeInfo & OPFL_Chain)
2450 Ops.push_back(InputChain);
2451 if ((EmitNodeInfo & OPFL_FlagInput) && InputFlag.getNode() != 0)
2452 Ops.push_back(InputFlag);
2456 if (Opcode != OPC_MorphNodeTo) {
2457 // If this is a normal EmitNode command, just create the new node and
2458 // add the results to the RecordedNodes list.
2459 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2460 VTList, Ops.data(), Ops.size());
2462 // Add all the non-flag/non-chain results to the RecordedNodes list.
2463 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2464 if (VTs[i] == MVT::Other || VTs[i] == MVT::Flag) break;
2465 RecordedNodes.push_back(SDValue(Res, i));
2469 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2473 // If the node had chain/flag results, update our notion of the current
2475 if (EmitNodeInfo & OPFL_FlagOutput) {
2476 InputFlag = SDValue(Res, VTs.size()-1);
2477 if (EmitNodeInfo & OPFL_Chain)
2478 InputChain = SDValue(Res, VTs.size()-2);
2479 } else if (EmitNodeInfo & OPFL_Chain)
2480 InputChain = SDValue(Res, VTs.size()-1);
2482 // If the OPFL_MemRefs flag is set on this node, slap all of the
2483 // accumulated memrefs onto it.
2485 // FIXME: This is vastly incorrect for patterns with multiple outputs
2486 // instructions that access memory and for ComplexPatterns that match
2488 if (EmitNodeInfo & OPFL_MemRefs) {
2489 MachineSDNode::mmo_iterator MemRefs =
2490 MF->allocateMemRefsArray(MatchedMemRefs.size());
2491 std::copy(MatchedMemRefs.begin(), MatchedMemRefs.end(), MemRefs);
2492 cast<MachineSDNode>(Res)
2493 ->setMemRefs(MemRefs, MemRefs + MatchedMemRefs.size());
2497 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2498 << " node: "; Res->dump(CurDAG); errs() << "\n");
2500 // If this was a MorphNodeTo then we're completely done!
2501 if (Opcode == OPC_MorphNodeTo) {
2502 // Update chain and flag uses.
2503 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2504 InputFlag, FlagResultNodesMatched, true);
2511 case OPC_MarkFlagResults: {
2512 unsigned NumNodes = MatcherTable[MatcherIndex++];
2514 // Read and remember all the flag-result nodes.
2515 for (unsigned i = 0; i != NumNodes; ++i) {
2516 unsigned RecNo = MatcherTable[MatcherIndex++];
2518 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2520 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2521 FlagResultNodesMatched.push_back(RecordedNodes[RecNo].getNode());
2526 case OPC_CompleteMatch: {
2527 // The match has been completed, and any new nodes (if any) have been
2528 // created. Patch up references to the matched dag to use the newly
2530 unsigned NumResults = MatcherTable[MatcherIndex++];
2532 for (unsigned i = 0; i != NumResults; ++i) {
2533 unsigned ResSlot = MatcherTable[MatcherIndex++];
2535 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2537 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2538 SDValue Res = RecordedNodes[ResSlot];
2540 assert(i < NodeToMatch->getNumValues() &&
2541 NodeToMatch->getValueType(i) != MVT::Other &&
2542 NodeToMatch->getValueType(i) != MVT::Flag &&
2543 "Invalid number of results to complete!");
2544 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2545 NodeToMatch->getValueType(i) == MVT::iPTR ||
2546 Res.getValueType() == MVT::iPTR ||
2547 NodeToMatch->getValueType(i).getSizeInBits() ==
2548 Res.getValueType().getSizeInBits()) &&
2549 "invalid replacement");
2550 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2553 // If the root node defines a flag, add it to the flag nodes to update
2555 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Flag)
2556 FlagResultNodesMatched.push_back(NodeToMatch);
2558 // Update chain and flag uses.
2559 UpdateChainsAndFlags(NodeToMatch, InputChain, ChainNodesMatched,
2560 InputFlag, FlagResultNodesMatched, false);
2562 assert(NodeToMatch->use_empty() &&
2563 "Didn't replace all uses of the node?");
2565 // FIXME: We just return here, which interacts correctly with SelectRoot
2566 // above. We should fix this to not return an SDNode* anymore.
2571 // If the code reached this point, then the match failed. See if there is
2572 // another child to try in the current 'Scope', otherwise pop it until we
2573 // find a case to check.
2574 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2575 ++NumDAGIselRetries;
2577 if (MatchScopes.empty()) {
2578 CannotYetSelect(NodeToMatch);
2582 // Restore the interpreter state back to the point where the scope was
2584 MatchScope &LastScope = MatchScopes.back();
2585 RecordedNodes.resize(LastScope.NumRecordedNodes);
2587 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2588 N = NodeStack.back();
2590 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2591 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2592 MatcherIndex = LastScope.FailIndex;
2594 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2596 InputChain = LastScope.InputChain;
2597 InputFlag = LastScope.InputFlag;
2598 if (!LastScope.HasChainNodesMatched)
2599 ChainNodesMatched.clear();
2600 if (!LastScope.HasFlagResultNodesMatched)
2601 FlagResultNodesMatched.clear();
2603 // Check to see what the offset is at the new MatcherIndex. If it is zero
2604 // we have reached the end of this scope, otherwise we have another child
2605 // in the current scope to try.
2606 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2607 if (NumToSkip & 128)
2608 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2610 // If we have another child in this scope to match, update FailIndex and
2612 if (NumToSkip != 0) {
2613 LastScope.FailIndex = MatcherIndex+NumToSkip;
2617 // End of this scope, pop it and try the next child in the containing
2619 MatchScopes.pop_back();
2626 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2628 raw_string_ostream Msg(msg);
2629 Msg << "Cannot yet select: ";
2631 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2632 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2633 N->getOpcode() != ISD::INTRINSIC_VOID) {
2634 N->printrFull(Msg, CurDAG);
2636 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2638 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2639 if (iid < Intrinsic::num_intrinsics)
2640 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2641 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2642 Msg << "target intrinsic %" << TII->getName(iid);
2644 Msg << "unknown intrinsic #" << iid;
2646 report_fatal_error(Msg.str());
2649 char SelectionDAGISel::ID = 0;